intel: Modify non secure access function
Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70
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@ -74,7 +74,6 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
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socfpga_delay_timer_init();
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socfpga_delay_timer_init();
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init_ncore_ccu();
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init_ncore_ccu();
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init_hard_memory_controller();
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init_hard_memory_controller();
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enable_ns_bridge_access();
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}
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}
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@ -66,6 +66,7 @@
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#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x))
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#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x))
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#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
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#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
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#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
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#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
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#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
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#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
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@ -73,6 +74,8 @@
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#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
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#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
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#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
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#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
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void enable_nonsecure_access(void);
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void enable_ns_peripheral_access(void);
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void enable_ns_bridge_access(void);
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void enable_ns_bridge_access(void);
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#endif
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#endif
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@ -10,6 +10,12 @@
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#include "agilex_system_manager.h"
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#include "agilex_system_manager.h"
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void enable_nonsecure_access(void)
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void enable_nonsecure_access(void)
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{
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enable_ns_peripheral_access();
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enable_ns_bridge_access();
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}
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void enable_ns_peripheral_access(void)
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{
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{
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mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
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mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
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mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
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mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
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@ -4,6 +4,10 @@
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#define S10_FIREWALL_SOC2FPGA 0xffd21200
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#define S10_FIREWALL_LWSOC2FPGA 0xffd21300
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/* L3 Interconnect Register Map */
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#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
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#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
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#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
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#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
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#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
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#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
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@ -59,13 +63,19 @@
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#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
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#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
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#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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/* System Manager Register Map */
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#define S10_SYSMGR_CORE(x) (0xffd12000 + (x))
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#define S10_SYSMGR_CORE(x) (0xffd12000 + (x))
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#define SYSMGR_MMC 0x28
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#define SYSMGR_MMC 0x28
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#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0)
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#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0)
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#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
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#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
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#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
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#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
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#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
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#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
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#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
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#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
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#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
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void enable_nonsecure_access(void);
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void enable_ns_peripheral_access(void);
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void enable_ns_bridge_access(void);
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@ -9,6 +9,12 @@
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#include "s10_system_manager.h"
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#include "s10_system_manager.h"
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void enable_nonsecure_access(void)
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void enable_nonsecure_access(void)
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{
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enable_ns_peripheral_access();
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enable_ns_bridge_access();
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}
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void enable_ns_peripheral_access(void)
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{
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{
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mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
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mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
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mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
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mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
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@ -91,3 +97,8 @@ void enable_nonsecure_access(void)
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}
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}
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void enable_ns_bridge_access(void)
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{
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mmio_write_32(S10_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL);
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mmio_write_32(S10_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL);
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}
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