SPM: Move all SP-related info to SP context struct
Move all information related to a Secure Partition to the struct secure_partition_context_t. This requires an in-depth refactor because most of the previous code of SPM relied on global information. Change-Id: I0a23e93817dcc191ce1d7506b8bc671d376123c4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz
parent
1634cae89d
commit
22282bb68a
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@ -55,8 +55,4 @@ typedef struct secure_partition_boot_info {
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secure_partition_mp_info_t *mp_info;
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} secure_partition_boot_info_t;
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/* Setup function for secure partitions context. */
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void secure_partition_setup(void);
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#endif /* __SECURE_PARTITION_H__ */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -15,46 +15,28 @@
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#include <platform.h>
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#include <secure_partition.h>
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#include <string.h>
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#include <types.h>
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#include <xlat_tables_v2.h>
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#include "spm_private.h"
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#include "spm_shim_private.h"
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/* Place translation tables by default along with the ones used by BL31. */
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#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table"
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#endif
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/* Allocate and initialise the translation context for the secure partition. */
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REGISTER_XLAT_CONTEXT2(secure_partition,
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PLAT_SP_IMAGE_MMAP_REGIONS,
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PLAT_SP_IMAGE_MAX_XLAT_TABLES,
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PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE,
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EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME);
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/* Export a handle on the secure partition translation context */
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xlat_ctx_t *secure_partition_xlat_ctx_handle = &secure_partition_xlat_ctx;
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/* Setup context of the Secure Partition */
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void secure_partition_setup(void)
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void secure_partition_setup(secure_partition_context_t *sp_ctx)
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{
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VERBOSE("S-EL1/S-EL0 context setup start...\n");
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cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
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cpu_context_t *ctx = cm_get_context(SECURE);
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/*
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* Initialize CPU context
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* ----------------------
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*/
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/* Make sure that we got a Secure context. */
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assert(ctx != NULL);
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entry_point_info_t ep_info = {0};
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/* Assert we are in Secure state. */
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assert((read_scr_el3() & SCR_NS_BIT) == 0);
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SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
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ep_info.pc = BL32_BASE;
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ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS);
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/* Disable MMU at EL1. */
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disable_mmu_icache_el1();
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/* Invalidate TLBs at EL1. */
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tlbivmalle1();
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dsbish();
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cm_setup_context(ctx, &ep_info);
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/*
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* General-Purpose registers
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@ -143,13 +125,13 @@ void secure_partition_setup(void)
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MAP_REGION_FLAT(SPM_SHIM_EXCEPTIONS_START,
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SPM_SHIM_EXCEPTIONS_SIZE,
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MT_CODE | MT_SECURE | MT_PRIVILEGED);
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mmap_add_region_ctx(&secure_partition_xlat_ctx,
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mmap_add_region_ctx(sp_ctx->xlat_ctx_handle,
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&sel1_exception_vectors);
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mmap_add_ctx(&secure_partition_xlat_ctx,
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mmap_add_ctx(sp_ctx->xlat_ctx_handle,
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plat_get_secure_partition_mmap(NULL));
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init_xlat_tables_ctx(&secure_partition_xlat_ctx);
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init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle);
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/*
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* MMU-related registers
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@ -222,9 +204,12 @@ void secure_partition_setup(void)
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
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uint64_t *xlat_base =
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((xlat_ctx_t *)sp_ctx->xlat_ctx_handle)->base_table;
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/* Point TTBR0_EL1 at the tables of the context created for the SP. */
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1,
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(u_register_t)secure_partition_base_xlat_table);
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(u_register_t)xlat_base);
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/*
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* Setup other system registers
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@ -312,6 +297,4 @@ void secure_partition_setup(void)
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if (plat_my_core_pos() == sp_mp_info[index].linear_id)
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sp_mp_info[index].flags |= MP_INFO_FLAG_PRIMARY_CPU;
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}
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VERBOSE("S-EL1/S-EL0 context setup end.\n");
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}
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -11,14 +11,11 @@ ifneq (${ARCH},aarch64)
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$(error "Error: SPM is only supported on aarch64.")
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endif
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# SPM sources
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SPM_SOURCES := $(addprefix services/std_svc/spm/, \
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spm_main.c \
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${ARCH}/spm_helpers.S \
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secure_partition_setup.c \
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${ARCH}/spm_shim_exceptions.S)
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${ARCH}/spm_shim_exceptions.S \
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spm_main.c \
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sp_setup.c)
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# Let the top-level Makefile know that we intend to include a BL32 image
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@ -22,203 +22,111 @@
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#include <xlat_tables_v2.h>
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#include "spm_private.h"
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#include "spm_shim_private.h"
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/* Place translation tables by default along with the ones used by BL31. */
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#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table"
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#endif
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/* Allocate and initialise the translation context for the secure partitions. */
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REGISTER_XLAT_CONTEXT2(sp,
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PLAT_SP_IMAGE_MMAP_REGIONS,
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PLAT_SP_IMAGE_MAX_XLAT_TABLES,
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PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE,
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EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME);
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/* Lock used for SP_MEMORY_ATTRIBUTES_GET and SP_MEMORY_ATTRIBUTES_SET */
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static spinlock_t mem_attr_smc_lock;
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/* Get handle of Secure Partition translation context */
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xlat_ctx_t *spm_get_sp_xlat_context(void)
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{
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return &sp_xlat_ctx;
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};
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/*******************************************************************************
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* Secure Partition context information.
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******************************************************************************/
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static secure_partition_context_t sp_ctx;
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/*******************************************************************************
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* Replace the S-EL1 re-entry information with S-EL0 re-entry
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* information
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* This function takes an SP context pointer and prepares the CPU to enter.
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******************************************************************************/
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static void spm_setup_next_eret_into_sel0(const cpu_context_t *secure_context)
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static void spm_sp_prepare_enter(secure_partition_context_t *sp_ctx)
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{
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assert(secure_context == cm_get_context(SECURE));
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assert(sp_ctx != NULL);
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cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1());
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}
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/* Assign the context of the SP to this CPU */
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cm_set_context(&(sp_ctx->cpu_ctx), SECURE);
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/*******************************************************************************
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* This function takes an SP context pointer and:
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* 1. Applies the S-EL1 system register context from sp_ctx->cpu_ctx.
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* 2. Saves the current C runtime state (callee-saved registers) on the stack
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* frame and saves a reference to this state.
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* 3. Calls el3_exit() so that the EL3 system and general purpose registers
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* from the sp_ctx->cpu_ctx are used to enter the secure partition image.
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******************************************************************************/
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static uint64_t spm_synchronous_sp_entry(secure_partition_context_t *sp_ctx_ptr)
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{
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uint64_t rc;
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assert(sp_ctx_ptr != NULL);
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assert(sp_ctx_ptr->c_rt_ctx == 0);
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assert(cm_get_context(SECURE) == &sp_ctx_ptr->cpu_ctx);
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/* Apply the Secure EL1 system register context and switch to it */
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/* Restore the context assigned above */
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cm_el1_sysregs_context_restore(SECURE);
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cm_set_next_eret_context(SECURE);
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VERBOSE("%s: We're about to enter the Secure partition...\n", __func__);
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rc = spm_secure_partition_enter(&sp_ctx_ptr->c_rt_ctx);
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#if ENABLE_ASSERTIONS
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sp_ctx_ptr->c_rt_ctx = 0;
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#endif
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return rc;
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/* Invalidate TLBs at EL1. */
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tlbivmalle1();
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dsbish();
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}
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/*******************************************************************************
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* This function takes a Secure partition context pointer and:
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* 1. Saves the S-EL1 system register context to sp_ctx->cpu_ctx.
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* 2. Restores the current C runtime state (callee saved registers) from the
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* stack frame using the reference to this state saved in
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* spm_secure_partition_enter().
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* 3. It does not need to save any general purpose or EL3 system register state
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* as the generic smc entry routine should have saved those.
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* Enter SP after preparing it with spm_sp_prepare_enter().
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******************************************************************************/
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static void __dead2 spm_synchronous_sp_exit(
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const secure_partition_context_t *sp_ctx_ptr, uint64_t ret)
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static uint64_t spm_sp_enter(secure_partition_context_t *sp_ctx)
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{
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assert(sp_ctx_ptr != NULL);
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/* Save the Secure EL1 system register context */
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assert(cm_get_context(SECURE) == &sp_ctx_ptr->cpu_ctx);
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cm_el1_sysregs_context_save(SECURE);
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assert(sp_ctx_ptr->c_rt_ctx != 0U);
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spm_secure_partition_exit(sp_ctx_ptr->c_rt_ctx, ret);
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/* Should never reach here */
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assert(0);
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/* Enter Secure Partition */
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return spm_secure_partition_enter(&sp_ctx->c_rt_ctx);
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}
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/*******************************************************************************
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* This function passes control to the Secure Partition image (BL32) for the
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* first time on the primary cpu after a cold boot. It assumes that a valid
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* secure context has already been created by spm_setup() which can be directly
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* used. This function performs a synchronous entry into the Secure partition.
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* The SP passes control back to this routine through a SMC.
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* Jump to each Secure Partition for the first time.
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******************************************************************************/
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static int32_t spm_init(void)
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{
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entry_point_info_t *secure_partition_ep_info;
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uint64_t rc;
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uint64_t rc = 0;
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secure_partition_context_t *ctx;
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VERBOSE("%s entry\n", __func__);
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INFO("Secure Partition init...\n");
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/*
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* Get information about the Secure Partition (BL32) image. Its
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* absence is a critical failure.
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*/
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secure_partition_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
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assert(secure_partition_ep_info != NULL);
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ctx = &sp_ctx;
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/*
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* Initialise the common context and then overlay the S-EL0 specific
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* context on top of it.
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*/
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cm_init_my_context(secure_partition_ep_info);
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secure_partition_setup();
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ctx->sp_init_in_progress = 1;
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/*
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* Make all CPUs use the same secure context.
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*/
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for (unsigned int i = 0; i < PLATFORM_CORE_COUNT; i++) {
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cm_set_context_by_index(i, &sp_ctx.cpu_ctx, SECURE);
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}
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/*
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* Arrange for an entry into the secure partition.
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*/
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sp_ctx.sp_init_in_progress = 1;
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rc = spm_synchronous_sp_entry(&sp_ctx);
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spm_sp_prepare_enter(ctx);
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rc |= spm_sp_enter(ctx);
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assert(rc == 0);
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sp_ctx.sp_init_in_progress = 0;
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VERBOSE("SP_MEMORY_ATTRIBUTES_SET_AARCH64 availability has been revoked\n");
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ctx->sp_init_in_progress = 0;
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INFO("Secure Partition initialized.\n");
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return rc;
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}
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/*******************************************************************************
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* Given a secure partition entrypoint info pointer, entry point PC & pointer to
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* a context data structure, this function will initialize the SPM context and
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* entry point info for the secure partition.
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******************************************************************************/
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void spm_init_sp_ep_state(struct entry_point_info *sp_ep_info,
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uint64_t pc,
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secure_partition_context_t *sp_ctx_ptr)
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{
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uint32_t ep_attr;
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assert(sp_ep_info != NULL);
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assert(pc != 0U);
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assert(sp_ctx_ptr != NULL);
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cm_set_context(&sp_ctx_ptr->cpu_ctx, SECURE);
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/* initialise an entrypoint to set up the CPU context */
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ep_attr = SECURE | EP_ST_ENABLE;
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if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0U)
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ep_attr |= EP_EE_BIG;
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SET_PARAM_HEAD(sp_ep_info, PARAM_EP, VERSION_1, ep_attr);
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sp_ep_info->pc = pc;
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/* The secure partition runs in S-EL0. */
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sp_ep_info->spsr = SPSR_64(MODE_EL0,
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MODE_SP_EL0,
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DISABLE_ALL_EXCEPTIONS);
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zeromem(&sp_ep_info->args, sizeof(sp_ep_info->args));
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}
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/*******************************************************************************
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* Secure Partition Manager setup. The SPM finds out the SP entrypoint if not
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* already known and initialises the context for entry into the SP for its
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* initialisation.
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* Initialize contexts of all Secure Partitions.
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******************************************************************************/
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int32_t spm_setup(void)
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{
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entry_point_info_t *secure_partition_ep_info;
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secure_partition_context_t *ctx;
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VERBOSE("%s entry\n", __func__);
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/* Disable MMU at EL1 (initialized by BL2) */
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disable_mmu_icache_el1();
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/*
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* Get information about the Secure Partition (BL32) image. Its
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* absence is a critical failure.
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*/
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secure_partition_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
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if (secure_partition_ep_info == NULL) {
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WARN("No SPM provided by BL2 boot loader, Booting device"
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" without SPM initialization. SMCs destined for SPM"
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" will return SMC_UNK\n");
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return 1;
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}
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/* Initialize context of the SP */
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INFO("Secure Partition context setup start...\n");
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/*
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* If there's no valid entry point for SP, we return a non-zero value
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* signalling failure initializing the service. We bail out without
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* registering any handlers
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*/
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if (secure_partition_ep_info->pc == 0U) {
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return 1;
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}
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ctx = &sp_ctx;
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spm_init_sp_ep_state(secure_partition_ep_info,
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secure_partition_ep_info->pc,
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&sp_ctx);
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/* Assign translation tables context. */
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ctx->xlat_ctx_handle = spm_get_sp_xlat_context();
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/*
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* All SPM initialization done. Now register our init function with
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* BL31 for deferred invocation
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*/
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secure_partition_setup(ctx);
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/* Register init function for deferred init. */
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bl31_register_bl32_init(&spm_init);
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VERBOSE("%s exit\n", __func__);
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INFO("Secure Partition setup done.\n");
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return 0;
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}
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@ -290,13 +198,15 @@ static unsigned int smc_mmap_to_smc_attr(unsigned int attr)
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return smc_attr;
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}
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static int32_t spm_memory_attributes_get_smc_handler(uintptr_t base_va)
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static int32_t spm_memory_attributes_get_smc_handler(
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secure_partition_context_t *sp_ctx,
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uintptr_t base_va)
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{
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uint32_t attributes;
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spin_lock(&mem_attr_smc_lock);
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int rc = get_mem_attributes(secure_partition_xlat_ctx_handle,
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int rc = get_mem_attributes(sp_ctx->xlat_ctx_handle,
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base_va, &attributes);
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spin_unlock(&mem_attr_smc_lock);
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@ -311,7 +221,9 @@ static int32_t spm_memory_attributes_get_smc_handler(uintptr_t base_va)
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}
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}
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static int spm_memory_attributes_set_smc_handler(u_register_t page_address,
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static int spm_memory_attributes_set_smc_handler(
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secure_partition_context_t *sp_ctx,
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u_register_t page_address,
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u_register_t pages_count,
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u_register_t smc_attributes)
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{
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@ -325,8 +237,9 @@ static int spm_memory_attributes_set_smc_handler(u_register_t page_address,
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spin_lock(&mem_attr_smc_lock);
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int ret = change_mem_attributes(secure_partition_xlat_ctx_handle,
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base_va, size, smc_attr_to_mmap_attr(attributes));
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int ret = change_mem_attributes(sp_ctx->xlat_ctx_handle,
|
||||
base_va, size,
|
||||
smc_attr_to_mmap_attr(attributes));
|
||||
|
||||
spin_unlock(&mem_attr_smc_lock);
|
||||
|
||||
|
|
@ -336,7 +249,9 @@ static int spm_memory_attributes_set_smc_handler(u_register_t page_address,
|
|||
return (ret == 0) ? SPM_SUCCESS : SPM_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Secure Partition Manager SMC handler.
|
||||
******************************************************************************/
|
||||
uint64_t spm_smc_handler(uint32_t smc_fid,
|
||||
uint64_t x1,
|
||||
uint64_t x2,
|
||||
|
|
@ -356,17 +271,21 @@ uint64_t spm_smc_handler(uint32_t smc_fid,
|
|||
|
||||
/* Handle SMCs from Secure world. */
|
||||
|
||||
assert(handle == cm_get_context(SECURE));
|
||||
|
||||
/* Make next ERET jump to S-EL0 instead of S-EL1. */
|
||||
cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1());
|
||||
|
||||
switch (smc_fid) {
|
||||
|
||||
case SPM_VERSION_AARCH32:
|
||||
SMC_RET1(handle, SPM_VERSION_COMPILED);
|
||||
|
||||
case SP_EVENT_COMPLETE_AARCH64:
|
||||
assert(handle == cm_get_context(SECURE));
|
||||
/* Save secure state */
|
||||
cm_el1_sysregs_context_save(SECURE);
|
||||
spm_setup_next_eret_into_sel0(handle);
|
||||
|
||||
if (sp_ctx.sp_init_in_progress) {
|
||||
if (sp_ctx.sp_init_in_progress == 1) {
|
||||
/*
|
||||
* SPM reports completion. The SPM must have
|
||||
* initiated the original request through a
|
||||
|
|
@ -374,18 +293,18 @@ uint64_t spm_smc_handler(uint32_t smc_fid,
|
|||
* partition. Jump back to the original C
|
||||
* runtime context.
|
||||
*/
|
||||
spm_synchronous_sp_exit(&sp_ctx, x1);
|
||||
assert(0);
|
||||
spm_secure_partition_exit(sp_ctx.c_rt_ctx, x1);
|
||||
|
||||
/* spm_secure_partition_exit doesn't return */
|
||||
}
|
||||
|
||||
/* Release the Secure Partition context */
|
||||
spin_unlock(&sp_ctx.lock);
|
||||
spin_unlock(&(sp_ctx.lock));
|
||||
|
||||
/*
|
||||
* This is the result from the Secure partition of an
|
||||
* earlier request. Copy the result into the non-secure
|
||||
* context, save the secure state and return to the
|
||||
* non-secure state.
|
||||
* context and return to the non-secure state.
|
||||
*/
|
||||
|
||||
/* Get a reference to the non-secure context */
|
||||
|
|
@ -402,20 +321,24 @@ uint64_t spm_smc_handler(uint32_t smc_fid,
|
|||
case SP_MEMORY_ATTRIBUTES_GET_AARCH64:
|
||||
INFO("Received SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n");
|
||||
|
||||
if (!sp_ctx.sp_init_in_progress) {
|
||||
if (sp_ctx.sp_init_in_progress == 0) {
|
||||
WARN("SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n");
|
||||
SMC_RET1(handle, SPM_NOT_SUPPORTED);
|
||||
}
|
||||
SMC_RET1(handle, spm_memory_attributes_get_smc_handler(x1));
|
||||
SMC_RET1(handle,
|
||||
spm_memory_attributes_get_smc_handler(
|
||||
&sp_ctx, x1));
|
||||
|
||||
case SP_MEMORY_ATTRIBUTES_SET_AARCH64:
|
||||
INFO("Received SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n");
|
||||
|
||||
if (!sp_ctx.sp_init_in_progress) {
|
||||
if (sp_ctx.sp_init_in_progress == 0) {
|
||||
WARN("SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n");
|
||||
SMC_RET1(handle, SPM_NOT_SUPPORTED);
|
||||
}
|
||||
SMC_RET1(handle, spm_memory_attributes_set_smc_handler(x1, x2, x3));
|
||||
SMC_RET1(handle,
|
||||
spm_memory_attributes_set_smc_handler(
|
||||
&sp_ctx, x1, x2, x3));
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -456,16 +379,13 @@ uint64_t spm_smc_handler(uint32_t smc_fid,
|
|||
/* Lock the Secure Partition context. */
|
||||
spin_lock(&sp_ctx.lock);
|
||||
|
||||
/*
|
||||
* Restore the secure world context and prepare for
|
||||
* entry in S-EL0
|
||||
*/
|
||||
assert(&sp_ctx.cpu_ctx == cm_get_context(SECURE));
|
||||
cm_el1_sysregs_context_restore(SECURE);
|
||||
cm_set_next_eret_context(SECURE);
|
||||
/* Jump to the Secure Partition. */
|
||||
|
||||
SMC_RET4(&sp_ctx.cpu_ctx, smc_fid, comm_buffer_address,
|
||||
comm_size_address, plat_my_core_pos());
|
||||
spm_sp_prepare_enter(&sp_ctx);
|
||||
|
||||
SMC_RET4(&(sp_ctx.cpu_ctx), smc_fid,
|
||||
comm_buffer_address, comm_size_address,
|
||||
plat_my_core_pos());
|
||||
}
|
||||
|
||||
case SP_MEMORY_ATTRIBUTES_GET_AARCH64:
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -29,30 +29,26 @@
|
|||
#define SP_C_RT_CTX_SIZE 0x60
|
||||
#define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT)
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <spinlock.h>
|
||||
#include <stdint.h>
|
||||
#include <xlat_tables_v2.h>
|
||||
|
||||
/* Handle on the Secure partition translation context */
|
||||
extern xlat_ctx_t *secure_partition_xlat_ctx_handle;
|
||||
|
||||
struct entry_point_info;
|
||||
|
||||
typedef struct secure_partition_context {
|
||||
uint64_t c_rt_ctx;
|
||||
cpu_context_t cpu_ctx;
|
||||
xlat_ctx_t *xlat_ctx_handle;
|
||||
unsigned int sp_init_in_progress;
|
||||
spinlock_t lock;
|
||||
} secure_partition_context_t;
|
||||
|
||||
/* Assembly helpers */
|
||||
uint64_t spm_secure_partition_enter(uint64_t *c_rt_ctx);
|
||||
void __dead2 spm_secure_partition_exit(uint64_t c_rt_ctx, uint64_t ret);
|
||||
void spm_init_sp_ep_state(struct entry_point_info *sp_ep_info,
|
||||
uint64_t pc,
|
||||
secure_partition_context_t *sp_ctx_ptr);
|
||||
|
||||
void secure_partition_setup(secure_partition_context_t *sp_ctx);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __SPM_PRIVATE_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue