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board/rde1edge: rename sgiclarkh to rde1edge 

Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with
'rde1edge' as per the updated product names.

Change-Id: I14e9b0332851798531de21d70eb54f1e5557a7bd
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
This commit is contained in:
Chandni Cherukuri 2019-02-22 16:44:49 +05:30
parent f717eca9e5
commit 240f03b783
8 changed files with 53 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts → plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
* Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,7 +7,7 @@
/dts-v1/;
/ {
/* compatible string */
compatible = "arm,sgi-clark";
compatible = "arm,rd-e1edge";
/*
* Place holder for system-id node with default values. The

0
plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts → plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts
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6
plat/arm/board/sgiclarkh/include/platform_def.h → plat/arm/board/rde1edge/include/platform_def.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
* Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -18,8 +18,8 @@
#define PLAT_CSS_MHU_BASE UL(0x45400000)
/* Base address of DMC-620 instances */
#define SGICLARKH_DMC620_BASE0 UL(0x4e000000)
#define SGICLARKH_DMC620_BASE1 UL(0x4e100000)
#define RDE1EDGE_DMC620_BASE0 UL(0x4e000000)
#define RDE1EDGE_DMC620_BASE1 UL(0x4e100000)
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2

14
plat/arm/board/sgiclarkh/platform.mk → plat/arm/board/rde1edge/platform.mk
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@ -6,34 +6,34 @@
include plat/arm/css/sgi/sgi-common.mk
SGICLARKH_BASE = plat/arm/board/sgiclarkh
RDE1EDGE_BASE = plat/arm/board/rde1edge
PLAT_INCLUDES += -I${SGICLARKH_BASE}/include/
PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
BL1_SOURCES += ${SGI_CPU_SOURCES}
BL2_SOURCES += ${SGICLARKH_BASE}/sgiclarkh_plat.c \
${SGICLARKH_BASE}/sgiclarkh_security.c \
BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \
${RDE1EDGE_BASE}/rde1edge_security.c \
drivers/arm/tzc/tzc_dmc620.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
${SGICLARKH_BASE}/sgiclarkh_plat.c \
${RDE1EDGE_BASE}/rde1edge_plat.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
# Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_tb_fw_config.dts
FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_nt_fw_config.dts
FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool

0
plat/arm/board/sgiclarkh/sgiclarkh_plat.c → plat/arm/board/rde1edge/rde1edge_plat.c
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40
plat/arm/board/rde1edge/rde1edge_security.c Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/arm/tzc_dmc620.h>
uintptr_t rde1edge_dmc_base[] = {
RDE1EDGE_DMC620_BASE0,
RDE1EDGE_DMC620_BASE1
};
static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = {
.dmc_base = rde1edge_dmc_base,
.dmc_count = ARRAY_SIZE(rde1edge_dmc_base)
};
static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
{
.region_base = ARM_AP_TZC_DRAM1_BASE,
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
.sec_attr = TZC_DMC620_REGION_S_RDWR
}
};
static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
.plat_drv_data = &rde1edge_plat_driver_data,
.plat_acc_addr_data = rde1edge_acc_addr_data,
.acc_addr_count = ARRAY_SIZE(rde1edge_acc_addr_data)
};
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
arm_tzc_dmc620_setup(&rde1edge_plat_config_data);
}

40
plat/arm/board/sgiclarkh/sgiclarkh_security.c
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@ -1,40 +0,0 @@
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/arm/tzc_dmc620.h>
uintptr_t sgiclarkh_dmc_base[] = {
SGICLARKH_DMC620_BASE0,
SGICLARKH_DMC620_BASE1
};
static const tzc_dmc620_driver_data_t sgiclarkh_plat_driver_data = {
.dmc_base = sgiclarkh_dmc_base,
.dmc_count = ARRAY_SIZE(sgiclarkh_dmc_base)
};
static const tzc_dmc620_acc_addr_data_t sgiclarkh_acc_addr_data[] = {
{
.region_base = ARM_AP_TZC_DRAM1_BASE,
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
.sec_attr = TZC_DMC620_REGION_S_RDWR
}
};
static const tzc_dmc620_config_data_t sgiclarkh_plat_config_data = {
.plat_drv_data = &sgiclarkh_plat_driver_data,
.plat_acc_addr_data = sgiclarkh_acc_addr_data,
.acc_addr_count = ARRAY_SIZE(sgiclarkh_acc_addr_data)
};
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
arm_tzc_dmc620_setup(&sgiclarkh_plat_config_data);
}

2
readme.rst
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@ -194,7 +194,7 @@ This release also contains the following platform support:
- Allwinner sun50i_64 and sun50i_h6
- Amlogic Meson S905 (GXBB)
- Arm SGI-575, RDN1Edge, SGI Clark.H and SGM-775
- Arm SGI-575, RDN1Edge, RDE1Edge and SGM-775
- Arm Neoverse N1 System Development Platform
- HiKey, HiKey960 and Poplar boards
- Marvell Armada 3700 and 8K