diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index 94c63f43f..8e169ae8d 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst @@ -427,7 +427,7 @@ Arm Rich IoT Platform ports :|G|: `vishnu-banavath`_ :|F|: plat/arm/board/corstone700 :|F|: plat/arm/board/a5ds -:|F|: plat/arm/board/diphda +:|F|: plat/arm/board/corstone1000 Arm Reference Design platform ports ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/plat/arm/diphda/index.rst b/docs/plat/arm/corstone1000/index.rst similarity index 93% rename from docs/plat/arm/diphda/index.rst rename to docs/plat/arm/corstone1000/index.rst index 27afda43f..b889b7f2e 100644 --- a/docs/plat/arm/diphda/index.rst +++ b/docs/plat/arm/corstone1000/index.rst @@ -1,7 +1,7 @@ -Diphda Platform +Corstone1000 Platform ========================== -Some of the features of the Diphda platform referenced in TF-A include: +Some of the features of the Corstone1000 platform referenced in TF-A include: - Cortex-A35 application processor (64-bit mode) - Secure Enclave @@ -37,7 +37,7 @@ Build Procedure (TF-A only) CC=aarch64-none-elf-gcc \ V=1 \ BUILD_BASE= \ - PLAT=diphda \ + PLAT=corstone1000 \ SPD=spmd \ SPMD_SPM_AT_SEL2=0 \ DEBUG=1 \ diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst index f262dc039..2f6852225 100644 --- a/docs/plat/arm/index.rst +++ b/docs/plat/arm/index.rst @@ -13,7 +13,7 @@ Arm Development Platforms arm_fpga/index arm-build-options morello/index - diphda/index + corstone1000/index This chapter holds documentation related to Arm's development platforms, including both software models (FVPs) and hardware development boards diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S index 38f91fe5f..06e2a069a 100644 --- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S +++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S @@ -1,10 +1,10 @@ /* - * Copyright (c) 2021, ARM Limited. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -/* diphda platform provides custom values for the macros defined in +/* corstone1000 platform provides custom values for the macros defined in * arm_def.h , so only platform_def.h needs to be included */ #if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA) diff --git a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c similarity index 84% rename from plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c rename to plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c index 916c868d2..3ee396c91 100644 --- a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c +++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,7 +44,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), .ep_info.pc = BL32_BASE, - .ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE, + .ep_info.args.arg0 = CORSTONE1000_TOS_FW_CONFIG_BASE, SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), .image_info.image_base = BL32_BASE, @@ -56,9 +56,9 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { /* Fill TOS_FW_CONFIG related information */ { .image_id = TOS_FW_CONFIG_ID, - .image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE, - .image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \ - DIPHDA_TOS_FW_CONFIG_BASE, + .image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE, + .image_info.image_max_size = CORSTONE1000_TOS_FW_CONFIG_LIMIT - \ + CORSTONE1000_TOS_FW_CONFIG_BASE, SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, @@ -71,13 +71,12 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { .image_id = BL33_IMAGE_ID, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), - .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, + .ep_info.pc = BL33_BASE, SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, - .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE - - PLAT_ARM_NS_IMAGE_BASE, + .image_info.image_base = BL33_BASE, + .image_info.image_max_size = BL33_LIMIT - BL33_BASE, .next_handoff_image_id = INVALID_IMAGE_ID, }, diff --git a/plat/arm/board/diphda/common/diphda_err.c b/plat/arm/board/corstone1000/common/corstone1000_err.c similarity index 61% rename from plat/arm/board/diphda/common/diphda_err.c rename to plat/arm/board/corstone1000/common/corstone1000_err.c index 89a3b8249..376799f96 100644 --- a/plat/arm/board/diphda/common/diphda_err.c +++ b/plat/arm/board/corstone1000/common/corstone1000_err.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #include /* - * diphda error handler + * corstone1000 error handler */ void __dead2 plat_arm_error_handler(int err) { diff --git a/plat/arm/board/diphda/common/diphda_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S similarity index 90% rename from plat/arm/board/diphda/common/diphda_helpers.S rename to plat/arm/board/corstone1000/common/corstone1000_helpers.S index c9d2a88de..cbe27c3b5 100644 --- a/plat/arm/board/diphda/common/diphda_helpers.S +++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,7 +29,7 @@ endfunc plat_secondary_cold_boot_setup * unsigned long plat_get_my_entrypoint (void); * * Main job of this routine is to distinguish between a cold and warm - * boot. On diphda, this information can be queried from the power + * boot. On corstone1000, this information can be queried from the power * controller. The Power Control SYS Status Register (PSYSR) indicates * the wake-up reason for the CPU. * @@ -61,7 +61,7 @@ func plat_is_my_cpu_primary mrs x0, mpidr_el1 mov_imm x1, MPIDR_AFFINITY_MASK and x0, x0, x1 - cmp x0, #DIPHDA_PRIMARY_CPU + cmp x0, #CORSTONE1000_PRIMARY_CPU cset w0, eq ret endfunc plat_is_my_cpu_primary diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c new file mode 100644 index 000000000..a96baae06 --- /dev/null +++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +/* + * Table of regions to map using the MMU. + * Replace or extend the below regions as required + */ + +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + ARM_MAP_NS_SHARED_RAM, + ARM_MAP_NS_DRAM1, + CORSTONE1000_MAP_DEVICE, + CORSTONE1000_EXTERNAL_FLASH, + {0} +}; + +static void set_fip_image_source(void) +{ + const struct plat_io_policy *policy; + /* + * metadata for firmware update is written at 0x0000 offset of the flash. + * PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted. + * As per firmware update spec, at a given point of time, only one bank is active. + * This means, TF-A should boot from the same bank as TF-M. + */ + volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG); + if (*boot_bank_flag > 1) { + VERBOSE("Boot_bank is set higher than possible values"); + } + + VERBOSE("Boot bank flag = %u.\n\r", *boot_bank_flag); + + policy = FCONF_GET_PROPERTY(arm, io_policies, FIP_IMAGE_ID); + + assert(policy != NULL); + assert(policy->image_spec != 0UL); + + io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec; + + if ((*boot_bank_flag) == 0) { + VERBOSE("Booting from bank 0: fip offset = 0x%lx\n\r", + PLAT_ARM_FIP_BASE_BANK0); + spec->offset = PLAT_ARM_FIP_BASE_BANK0; + } else { + VERBOSE("Booting from bank 1: fip offset = 0x%lx\n\r", + PLAT_ARM_FIP_BASE_BANK1); + spec->offset = PLAT_ARM_FIP_BASE_BANK1; + } +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); + /* + * Identify the start address of the FIP by reading the boot + * index flag from the flash. + */ + set_fip_image_source(); +} + +/* corstone1000 only has one always-on power domain and there + * is no power control present + */ +void __init plat_arm_pwrc_setup(void) +{ +} + +unsigned int plat_get_syscnt_freq2(void) +{ + /* Returning the Generic Timer Frequency */ + return SYS_COUNTER_FREQ_IN_TICKS; +} + + +/* + * Helper function to initialize ARM interconnect driver. + */ +void plat_arm_interconnect_init(void) +{ +} + +/* + * Helper function to place current master into coherency + */ +void plat_arm_interconnect_enter_coherency(void) +{ +} + +/* + * Helper function to remove current master from coherency + */ +void plat_arm_interconnect_exit_coherency(void) +{ +} + +/* + * This function is invoked during Mbed TLS library initialisation to get a heap + * The function simply returns the default allocated heap. + */ + +#if TRUSTED_BOARD_BOOT +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + assert(heap_addr != NULL); + assert(heap_size != NULL); + + return arm_get_mbedtls_heap(heap_addr, heap_size); +} +#endif diff --git a/plat/arm/board/diphda/common/diphda_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c similarity index 58% rename from plat/arm/board/diphda/common/diphda_pm.c rename to plat/arm/board/corstone1000/common/corstone1000_pm.c index 12b322e27..98dea7963 100644 --- a/plat/arm/board/diphda/common/diphda_pm.c +++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c @@ -6,17 +6,32 @@ #include #include - +#include /******************************************************************************* * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard * platform layer will take care of registering the handlers with PSCI. ******************************************************************************/ + +static void __dead2 corstone1000_system_reset(void) +{ + + uint32_t volatile * const watchdog_ctrl_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_CTRL_REG; + uint32_t volatile * const watchdog_val_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_VAL_REG; + + *(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL; + *watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE; + while (1) { + wfi(); + } +} + plat_psci_ops_t plat_arm_psci_pm_ops = { - /* dummy struct */ + .system_reset = corstone1000_system_reset, .validate_ns_entrypoint = NULL }; const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) { + ops = &plat_arm_psci_pm_ops; return ops; } diff --git a/plat/arm/board/diphda/common/diphda_security.c b/plat/arm/board/corstone1000/common/corstone1000_security.c similarity index 78% rename from plat/arm/board/diphda/common/diphda_security.c rename to plat/arm/board/corstone1000/common/corstone1000_security.c index bf172afca..c88201bcb 100644 --- a/plat/arm/board/diphda/common/diphda_security.c +++ b/plat/arm/board/corstone1000/common/corstone1000_security.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/arm/board/diphda/common/diphda_stack_protector.c b/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c similarity index 91% rename from plat/arm/board/diphda/common/diphda_stack_protector.c rename to plat/arm/board/corstone1000/common/corstone1000_stack_protector.c index 6228b63f2..393235e9d 100644 --- a/plat/arm/board/diphda/common/diphda_stack_protector.c +++ b/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/arm/board/diphda/common/diphda_topology.c b/plat/arm/board/corstone1000/common/corstone1000_topology.c similarity index 72% rename from plat/arm/board/diphda/common/diphda_topology.c rename to plat/arm/board/corstone1000/common/corstone1000_topology.c index 9dfd05d09..5351896e3 100644 --- a/plat/arm/board/diphda/common/diphda_topology.c +++ b/plat/arm/board/corstone1000/common/corstone1000_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,8 +7,8 @@ #include #include -/* The diphda power domain tree descriptor */ -static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT +/* The corstone1000 power domain tree descriptor */ +static unsigned char corstone1000_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT + 2]; /******************************************************************************* * This function dynamically constructs the topology according to @@ -22,13 +22,13 @@ const unsigned char *plat_get_power_domain_tree_desc(void) * The highest level is the system level. The next level is constituted * by clusters and then cores in clusters. */ - diphda_power_domain_tree_desc[0] = 1; - diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT; + corstone1000_power_domain_tree_desc[0] = 1; + corstone1000_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT; for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++) - diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; + corstone1000_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; - return diphda_power_domain_tree_desc; + return corstone1000_power_domain_tree_desc; } /****************************************************************************** diff --git a/plat/arm/board/diphda/common/diphda_trusted_boot.c b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c similarity index 91% rename from plat/arm/board/diphda/common/diphda_trusted_boot.c rename to plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c index ddb41faa6..cec733270 100644 --- a/plat/arm/board/diphda/common/diphda_trusted_boot.c +++ b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,7 +38,7 @@ int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, */ int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) { - *nv_ctr = DIPHDA_FW_NVCTR_VAL; + *nv_ctr = CORSTONE1000_FW_NVCTR_VAL; return 0; } diff --git a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts similarity index 88% rename from plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts rename to plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts index 536bdc39b..8e49ab83f 100644 --- a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts +++ b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h new file mode 100644 index 000000000..2523d72b9 --- /dev/null +++ b/plat/arm/board/corstone1000/common/include/platform_def.h @@ -0,0 +1,436 @@ +/* + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ARM_ROTPK_HEADER_LEN 19 +#define ARM_ROTPK_HASH_LEN 32 + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) + +/* PL011 UART related constants */ +#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ +#undef V2M_IOFPGA_UART0_CLK_IN_HZ +#endif + +#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ +#undef V2M_IOFPGA_UART1_CLK_IN_HZ +#endif + +#define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 +#define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 + +/* Core/Cluster/Thread counts for corstone1000 */ +#define CORSTONE1000_CLUSTER_COUNT U(1) +#define CORSTONE1000_MAX_CPUS_PER_CLUSTER U(4) +#define CORSTONE1000_MAX_PE_PER_CPU U(1) +#define CORSTONE1000_PRIMARY_CPU U(0) + +#define PLAT_ARM_CLUSTER_COUNT CORSTONE1000_CLUSTER_COUNT + +#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ + CORSTONE1000_MAX_CPUS_PER_CLUSTER * \ + CORSTONE1000_MAX_PE_PER_CPU) + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE 0x1a510000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ +#define PLAT_ARM_RUN_UART_BASE 0x1a520000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ +#define ARM_CONSOLE_BAUDRATE 115200 +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ + +/* Memory related constants */ + +/* SRAM (CVM) memory layout + * + * + * + * partition size: sizeof(meminfo_t) = 16 bytes + * + * content: memory info area used by the next BL + * + * + * + * partition size: 4080 bytes + * + * + * + * partition size: 4 KB + * + * content: + * + * Area where BL2 copies the images descriptors + * + * = + * + * partition size: 688 KB + * + * content: + * + * BL32 (optee-os) + * + * = 0x20ae000 + * + * partition size: 8 KB + * + * content: + * + * BL32 config (TOS_FW_CONFIG) + * + * + * + * partition size: 140 KB + * + * content: + * + * BL31 + * + * + * + * partition size: 4 KB + * + * content: + * + * MCUBOOT data needed to verify TF-A BL2 + * + * + * + * partition size: 176 KB + * + * content: + * + * BL2 + * + * = + 1 MB + * + * partition size: 512 KB + * + * content: + * + * BL33 (u-boot) + */ + +/* DDR memory */ +#define ARM_DRAM1_BASE UL(0x80000000) +#define ARM_DRAM1_SIZE (SZ_2G) /* 2GB*/ +#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1) + +/* DRAM1 and DRAM2 are the same for corstone1000 */ +#define ARM_DRAM2_BASE ARM_DRAM1_BASE +#define ARM_DRAM2_SIZE ARM_DRAM1_SIZE +#define ARM_DRAM2_END ARM_DRAM1_END + +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE +\ + ARM_NS_DRAM1_SIZE - 1) + +/* The first 8 KB of Trusted SRAM are used as shared memory */ +#define ARM_TRUSTED_SRAM_BASE UL(0x02000000) +#define ARM_SHARED_RAM_SIZE (SZ_8K) /* 8 KB */ +#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE + +/* The remaining Trusted SRAM is used to load the BL images */ +#define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */ + +/* Last 512KB of CVM is allocated for shared RAM + * as an example openAMP */ +#define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K) + +#define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \ + ARM_NS_SHARED_RAM_SIZE - \ + ARM_SHARED_RAM_SIZE) + +#define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */ + +#define PLAT_ARM_MAX_BL31_SIZE (140 * SZ_1K) /* 140 KB */ + +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ + ARM_SHARED_RAM_SIZE) +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) + +#define BL2_SIGNATURE_SIZE (SZ_4K) /* 4 KB */ + +#define BL2_SIGNATURE_BASE (BL2_LIMIT - \ + PLAT_ARM_MAX_BL2_SIZE) +#define BL2_BASE (BL2_LIMIT - \ + PLAT_ARM_MAX_BL2_SIZE + \ + BL2_SIGNATURE_SIZE) +#define BL2_LIMIT (ARM_BL_RAM_BASE + \ + ARM_BL_RAM_SIZE) + +#define BL31_BASE (BL2_SIGNATURE_BASE - \ + PLAT_ARM_MAX_BL31_SIZE) +#define BL31_LIMIT BL2_SIGNATURE_BASE + +#define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \ + CORSTONE1000_TOS_FW_CONFIG_SIZE) +#define CORSTONE1000_TOS_FW_CONFIG_SIZE (SZ_8K) /* 8 KB */ +#define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE + +#define BL32_BASE ARM_BL_RAM_BASE +#define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - \ + BL32_BASE) + +#define BL32_LIMIT (BL32_BASE + \ + PLAT_ARM_MAX_BL32_SIZE) + +/* SPD_spmd settings */ + +#define PLAT_ARM_SPMC_BASE BL32_BASE +#define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE + +/* NS memory */ + +/* The last 512KB of the SRAM is allocated as shared memory */ +#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \ + (PLAT_ARM_MAX_BL31_SIZE + \ + PLAT_ARM_MAX_BL32_SIZE)) + +#define BL33_BASE ARM_DRAM1_BASE +#define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/ +#define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE) + +/* end of the definition of SRAM memory layout */ + +/* NOR Flash */ + +#define PLAT_ARM_BOOT_BANK_FLAG UL(0x08002000) +#define PLAT_ARM_FIP_BASE_BANK0 UL(0x081EF000) +#define PLAT_ARM_FIP_BASE_BANK1 UL(0x0916F000) +#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ + +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */ + +#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE_BANK0 +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. + * FW_CONFIG is intended to host the device tree. Currently, This area is not + * used because corstone1000 platform doesn't use a device tree at TF-A level. + */ +#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \ + + sizeof(meminfo_t)) +#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE \ + + (ARM_SHARED_RAM_SIZE >> 1)) + +/* + * Boot parameters passed from BL2 to BL31/BL32 are stored here + */ +#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT +#define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE + +/* + * The max number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#define ARM_BL_REGIONS 3 +#define PLAT_ARM_MMAP_ENTRIES 8 +#define MAX_XLAT_TABLES 5 +#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ + ARM_BL_REGIONS) +#define MAX_IO_DEVICES 2 +#define MAX_IO_HANDLES 3 +#define MAX_IO_BLOCK_DEVICES 1 + +/* GIC related constants */ +#define PLAT_ARM_GICD_BASE 0x1C010000 +#define PLAT_ARM_GICC_BASE 0x1C02F000 + +/* MHUv2 Secure Channel receiver and sender */ +#define PLAT_SDK700_MHU0_SEND 0x1B800000 +#define PLAT_SDK700_MHU0_RECV 0x1B810000 + +/* Timer/watchdog related constants */ +#define ARM_SYS_CNTCTL_BASE UL(0x1a200000) +#define ARM_SYS_CNTREAD_BASE UL(0x1a210000) +#define ARM_SYS_TIMCTL_BASE UL(0x1a220000) + +#define SECURE_WATCHDOG_ADDR_CTRL_REG 0x1A320000 +#define SECURE_WATCHDOG_ADDR_VAL_REG 0x1A320008 +#define SECURE_WATCHDOG_MASK_ENABLE 0x01 +#define SECURE_WATCHDOG_COUNTDOWN_VAL 0x1000 + +#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ + +#define CORSTONE1000_IRQ_TZ_WDOG 32 +#define CORSTONE1000_IRQ_SEC_SYS_TIMER 34 + +#define PLAT_MAX_PWR_LVL 2 +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The + * power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 +#define ARM_PWR_LVL2 MPIDR_AFFLVL2 + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define ARM_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define ARM_LOCAL_STATE_RET U(1) +/* Local power state for OFF/power-down. Valid for CPU and cluster + * power domains + */ +#define ARM_LOCAL_STATE_OFF U(2) + +#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) + +#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +/* + * This macro defines the deepest retention state possible. A higher state + * ID will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE 1 + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE 2 + +#define PLATFORM_STACK_SIZE UL(0x440) + +#define CORSTONE1000_EXTERNAL_FLASH MAP_REGION_FLAT( \ + PLAT_ARM_NVM_BASE, \ + PLAT_ARM_NVM_SIZE, \ + MT_DEVICE | MT_RO | MT_SECURE) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \ + ARM_NS_SHARED_RAM_BASE, \ + ARM_NS_SHARED_RAM_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END \ + - BL_CODE_BASE, \ + MT_CODE | MT_SECURE), \ + MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +/* + * Map the region for the optional device tree configuration with read and + * write permissions + */ +#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ + ARM_FW_CONFIG_BASE, \ + (ARM_FW_CONFIG_LIMIT- \ + ARM_FW_CONFIG_BASE), \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define CORSTONE1000_DEVICE_BASE (0x1A000000) +#define CORSTONE1000_DEVICE_SIZE (0x26000000) +#define CORSTONE1000_MAP_DEVICE MAP_REGION_FLAT( \ + CORSTONE1000_DEVICE_BASE, \ + CORSTONE1000_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/diphda/include/plat_macros.S b/plat/arm/board/corstone1000/include/plat_macros.S similarity index 85% rename from plat/arm/board/diphda/include/plat_macros.S rename to plat/arm/board/corstone1000/include/plat_macros.S index 4de8f9502..93342019b 100644 --- a/plat/arm/board/diphda/include/plat_macros.S +++ b/plat/arm/board/corstone1000/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk new file mode 100644 index 000000000..d89169142 --- /dev/null +++ b/plat/arm/board/corstone1000/platform.mk @@ -0,0 +1,83 @@ +# +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Making sure the corstone1000 platform type is specified +ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),) + $(error TARGET_PLATFORM must be fpga or fvp) +endif + +CORSTONE1000_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S + +PLAT_INCLUDES := -Iplat/arm/board/corstone1000/common/include \ + -Iplat/arm/board/corstone1000/include \ + -Iinclude/plat/arm/common \ + -Iinclude/plat/arm/css/common/aarch64 + + +CORSTONE1000_FW_NVCTR_VAL := 255 +TFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL} +NTFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL} + +override NEED_BL1 := no + +override NEED_BL2 := yes +FIP_BL2_ARGS := tb-fw + +override NEED_BL2U := no +override NEED_BL31 := yes +NEED_BL32 := yes +override NEED_BL33 := yes + +# Include GICv2 driver files +include drivers/arm/gic/v2/gicv2.mk + +CORSTONE1000_GIC_SOURCES := ${GICV2_SOURCES} \ + plat/common/plat_gicv2.c \ + plat/arm/common/arm_gicv2.c + + +BL2_SOURCES += plat/arm/board/corstone1000/common/corstone1000_security.c \ + plat/arm/board/corstone1000/common/corstone1000_err.c \ + plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c \ + lib/utils/mem_region.c \ + plat/arm/board/corstone1000/common/corstone1000_helpers.S \ + plat/arm/board/corstone1000/common/corstone1000_plat.c \ + plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \ + ${CORSTONE1000_CPU_LIBS} \ + + +BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ + lib/utils/mem_region.c \ + plat/arm/board/corstone1000/common/corstone1000_helpers.S \ + plat/arm/board/corstone1000/common/corstone1000_topology.c \ + plat/arm/board/corstone1000/common/corstone1000_security.c \ + plat/arm/board/corstone1000/common/corstone1000_plat.c \ + plat/arm/board/corstone1000/common/corstone1000_pm.c \ + ${CORSTONE1000_CPU_LIBS} \ + ${CORSTONE1000_GIC_SOURCES} + +ifneq (${ENABLE_STACK_PROTECTOR},0) + ifneq (${ENABLE_STACK_PROTECTOR},none) + CORSTONE1000_SECURITY_SOURCES := plat/arm/board/corstone1000/common/corstone1000_stack_protector.c + BL2_SOURCES += ${CORSTONE1000_SECURITY_SOURCES} + BL31_SOURCES += ${CORSTONE1000_SECURITY_SOURCES} + endif +endif + +FDT_SOURCES += plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts +CORSTONE1000_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/corstone1000_spmc_manifest.dtb + +# Add the SPMC manifest to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE1000_TOS_FW_CONFIG},--tos-fw-config,${CORSTONE1000_TOS_FW_CONFIG})) + +# Adding TARGET_PLATFORM as a GCC define (-D option) +$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) + +# Adding CORSTONE1000_FW_NVCTR_VAL as a GCC define (-D option) +$(eval $(call add_define,CORSTONE1000_FW_NVCTR_VAL)) + +include plat/arm/common/arm_common.mk +include plat/arm/board/common/board_common.mk diff --git a/plat/arm/board/diphda/common/diphda_plat.c b/plat/arm/board/diphda/common/diphda_plat.c deleted file mode 100644 index 28d15a59e..000000000 --- a/plat/arm/board/diphda/common/diphda_plat.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include - -/* - * Table of regions to map using the MMU. - * Replace or extend the below regions as required - */ - -const mmap_region_t plat_arm_mmap[] = { - ARM_MAP_SHARED_RAM, - ARM_MAP_NS_SHARED_RAM, - ARM_MAP_NS_DRAM1, - DIPHDA_MAP_DEVICE, - DIPHDA_EXTERNAL_FLASH, - {0} -}; - -/* diphda only has one always-on power domain and there - * is no power control present - */ -void __init plat_arm_pwrc_setup(void) -{ -} - -unsigned int plat_get_syscnt_freq2(void) -{ - /* Returning the Generic Timer Frequency */ - return SYS_COUNTER_FREQ_IN_TICKS; -} - - -/* - * Helper function to initialize ARM interconnect driver. - */ -void plat_arm_interconnect_init(void) -{ -} - -/* - * Helper function to place current master into coherency - */ -void plat_arm_interconnect_enter_coherency(void) -{ -} - -/* - * Helper function to remove current master from coherency - */ -void plat_arm_interconnect_exit_coherency(void) -{ -} - -/* - * This function is invoked during Mbed TLS library initialisation to get a heap - * The function simply returns the default allocated heap. - */ - -#if TRUSTED_BOARD_BOOT -int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) -{ - assert(heap_addr != NULL); - assert(heap_size != NULL); - - return arm_get_mbedtls_heap(heap_addr, heap_size); -} -#endif diff --git a/plat/arm/board/diphda/common/include/platform_def.h b/plat/arm/board/diphda/common/include/platform_def.h deleted file mode 100644 index 37fd71b6a..000000000 --- a/plat/arm/board/diphda/common/include/platform_def.h +++ /dev/null @@ -1,416 +0,0 @@ -/* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLATFORM_DEF_H -#define PLATFORM_DEF_H - -#include -#include -#include -#include -#include -#include -#include -#include - -#define ARM_ROTPK_HEADER_LEN 19 -#define ARM_ROTPK_HASH_LEN 32 - -/* Special value used to verify platform parameters from BL2 to BL31 */ -#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) - -/* PL011 UART related constants */ -#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ -#undef V2M_IOFPGA_UART0_CLK_IN_HZ -#endif - -#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ -#undef V2M_IOFPGA_UART1_CLK_IN_HZ -#endif - -#define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 -#define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 - -/* Core/Cluster/Thread counts for diphda */ -#define DIPHDA_CLUSTER_COUNT U(1) -#define DIPHDA_MAX_CPUS_PER_CLUSTER U(4) -#define DIPHDA_MAX_PE_PER_CPU U(1) -#define DIPHDA_PRIMARY_CPU U(0) - -#define PLAT_ARM_CLUSTER_COUNT DIPHDA_CLUSTER_COUNT - -#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ - DIPHDA_MAX_CPUS_PER_CLUSTER * \ - DIPHDA_MAX_PE_PER_CPU) - -/* UART related constants */ -#define PLAT_ARM_BOOT_UART_BASE 0x1a510000 -#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ -#define PLAT_ARM_RUN_UART_BASE 0x1a520000 -#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ -#define ARM_CONSOLE_BAUDRATE 115200 -#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE -#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ - -/* Memory related constants */ - -/* SRAM (CVM) memory layout - * - * - * - * partition size: sizeof(meminfo_t) = 16 bytes - * - * content: memory info area used by the next BL - * - * - * - * partition size: 4080 bytes - * - * - * - * partition size: 4 KB - * - * content: - * - * Area where BL2 copies the images descriptors - * - * = - * - * partition size: 688 KB - * - * content: - * - * BL32 (optee-os) - * - * = 0x20ae000 - * - * partition size: 8 KB - * - * content: - * - * BL32 config (TOS_FW_CONFIG) - * - * - * - * partition size: 140 KB - * - * content: - * - * BL31 - * - * - * - * partition size: 4 KB - * - * content: - * - * MCUBOOT data needed to verify TF-A BL2 - * - * - * - * partition size: 176 KB - * - * content: - * - * BL2 - * - * = + 1 MB - * - * partition size: 3 MB - * - * content: - * - * BL33 (u-boot) - */ - -/* DDR memory */ -#define ARM_DRAM1_BASE UL(0x80000000) -#define ARM_DRAM1_SIZE UL(0x80000000) -#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ - ARM_DRAM1_SIZE - 1) - -/* DRAM1 and DRAM2 are the same for diphda */ -#define ARM_DRAM2_BASE ARM_DRAM1_BASE -#define ARM_DRAM2_SIZE ARM_DRAM1_SIZE -#define ARM_DRAM2_END ARM_DRAM1_END - -#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE -#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE -#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ - ARM_NS_DRAM1_SIZE - 1) - -/* The first 8 KB of Trusted SRAM are used as shared memory */ -#define ARM_TRUSTED_SRAM_BASE UL(0x02000000) -#define ARM_SHARED_RAM_SIZE UL(0x00002000) /* 8 KB */ -#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE - -/* The remaining Trusted SRAM is used to load the BL images */ - -#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00100000) /* 1 MB */ - -#define PLAT_ARM_MAX_BL2_SIZE UL(0x0002d000) /* 180 KB */ - -#define PLAT_ARM_MAX_BL31_SIZE UL(0x00023000) /* 140 KB */ - -#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ - ARM_SHARED_RAM_SIZE) -#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ - ARM_SHARED_RAM_SIZE) - -#define BL2_SIGNATURE_SIZE UL(0x00001000) /* 4 KB */ -#define BL2_SIGNATURE_BASE (BL2_LIMIT - \ - PLAT_ARM_MAX_BL2_SIZE) -#define BL2_BASE (BL2_LIMIT - \ - PLAT_ARM_MAX_BL2_SIZE + \ - BL2_SIGNATURE_SIZE) -#define BL2_LIMIT (ARM_BL_RAM_BASE + \ - ARM_BL_RAM_SIZE) - -#define BL31_BASE (BL2_SIGNATURE_BASE - \ - PLAT_ARM_MAX_BL31_SIZE) -#define BL31_LIMIT BL2_SIGNATURE_BASE - -#define DIPHDA_TOS_FW_CONFIG_BASE (BL31_BASE - \ - DIPHDA_TOS_FW_CONFIG_SIZE) -#define DIPHDA_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */ -#define DIPHDA_TOS_FW_CONFIG_LIMIT BL31_BASE - -#define BL32_BASE ARM_BL_RAM_BASE -#define PLAT_ARM_MAX_BL32_SIZE (DIPHDA_TOS_FW_CONFIG_BASE - \ - BL32_BASE) /* 688 KB */ -#define BL32_LIMIT (BL32_BASE + \ - PLAT_ARM_MAX_BL32_SIZE) - -/* SPD_spmd settings */ - -#define PLAT_ARM_SPMC_BASE BL32_BASE -#define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE - -/* NS memory */ - -/* The last 3 MB of the SRAM is allocated to the non secure area */ -#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + \ - PLAT_ARM_TRUSTED_SRAM_SIZE) -#define ARM_NS_SHARED_RAM_SIZE UL(0x00300000) /* 3 MB */ - -/* end of the definition of SRAM memory layout */ - -/* NOR Flash */ - -#define PLAT_ARM_FIP_BASE UL(0x08131000) -#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ - -#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE -#define PLAT_ARM_NVM_SIZE UL(0x02000000) /* 32 MB */ - -#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE -#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE - -/* - * Some data must be aligned on the biggest cache line size in the platform. - * This is known only to the platform as it might have a combination of - * integrated and external caches. - */ -#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) -#define ARM_CACHE_WRITEBACK_SHIFT 6 - -/* - * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. - * FW_CONFIG is intended to host the device tree. Currently, This area is not - * used because diphda platform doesn't use a device tree at TF-A level. - */ -#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \ - + sizeof(meminfo_t)) -#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE \ - + (ARM_SHARED_RAM_SIZE >> 1)) - -/* - * Boot parameters passed from BL2 to BL31/BL32 are stored here - */ -#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT -#define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE - -/* - * The max number of regions like RO(code), coherent and data required by - * different BL stages which need to be mapped in the MMU. - */ -#define ARM_BL_REGIONS 3 -#define PLAT_ARM_MMAP_ENTRIES 8 -#define MAX_XLAT_TABLES 5 -#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ - ARM_BL_REGIONS) -#define MAX_IO_DEVICES 2 -#define MAX_IO_HANDLES 3 -#define MAX_IO_BLOCK_DEVICES 1 - -/* GIC related constants */ -#define PLAT_ARM_GICD_BASE 0x1C010000 -#define PLAT_ARM_GICC_BASE 0x1C02F000 - -/* MHUv2 Secure Channel receiver and sender */ -#define PLAT_SDK700_MHU0_SEND 0x1B800000 -#define PLAT_SDK700_MHU0_RECV 0x1B810000 - -/* Timer/watchdog related constants */ -#define ARM_SYS_CNTCTL_BASE UL(0x1a200000) -#define ARM_SYS_CNTREAD_BASE UL(0x1a210000) -#define ARM_SYS_TIMCTL_BASE UL(0x1a220000) - -#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ - -#define DIPHDA_IRQ_TZ_WDOG 32 -#define DIPHDA_IRQ_SEC_SYS_TIMER 34 - -#define PLAT_MAX_PWR_LVL 2 -/* - * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The - * power levels have a 1:1 mapping with the MPIDR affinity levels. - */ -#define ARM_PWR_LVL0 MPIDR_AFFLVL0 -#define ARM_PWR_LVL1 MPIDR_AFFLVL1 -#define ARM_PWR_LVL2 MPIDR_AFFLVL2 - -/* - * Macros for local power states in ARM platforms encoded by State-ID field - * within the power-state parameter. - */ -/* Local power state for power domains in Run state. */ -#define ARM_LOCAL_STATE_RUN U(0) -/* Local power state for retention. Valid only for CPU power domains */ -#define ARM_LOCAL_STATE_RET U(1) -/* Local power state for OFF/power-down. Valid for CPU and cluster - * power domains - */ -#define ARM_LOCAL_STATE_OFF U(2) - -#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE -#define PLAT_ARM_NSTIMER_FRAME_ID U(1) - -#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE) - -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) - -/* - * This macro defines the deepest retention state possible. A higher state - * ID will represent an invalid or a power down state. - */ -#define PLAT_MAX_RET_STATE 1 - -/* - * This macro defines the deepest power down states possible. Any state ID - * higher than this is invalid. - */ -#define PLAT_MAX_OFF_STATE 2 - -#define PLATFORM_STACK_SIZE UL(0x440) - -#define DIPHDA_EXTERNAL_FLASH MAP_REGION_FLAT( \ - PLAT_ARM_NVM_BASE, \ - PLAT_ARM_NVM_SIZE, \ - MT_DEVICE | MT_RO | MT_SECURE) - -#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ - ARM_SHARED_RAM_BASE, \ - ARM_SHARED_RAM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \ - ARM_NS_SHARED_RAM_BASE, \ - ARM_NS_SHARED_RAM_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ - ARM_NS_DRAM1_BASE, \ - ARM_NS_DRAM1_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ - BL_CODE_BASE, \ - BL_CODE_END \ - - BL_CODE_BASE, \ - MT_CODE | MT_SECURE), \ - MAP_REGION_FLAT( \ - BL_RO_DATA_BASE, \ - BL_RO_DATA_END \ - - BL_RO_DATA_BASE, \ - MT_RO_DATA | MT_SECURE) -#if USE_COHERENT_MEM -#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ - BL_COHERENT_RAM_BASE, \ - BL_COHERENT_RAM_END \ - - BL_COHERENT_RAM_BASE, \ - MT_DEVICE | MT_RW | MT_SECURE) -#endif - -/* - * Map the region for the optional device tree configuration with read and - * write permissions - */ -#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ - ARM_FW_CONFIG_BASE, \ - (ARM_FW_CONFIG_LIMIT- \ - ARM_FW_CONFIG_BASE), \ - MT_MEMORY | MT_RW | MT_SECURE) - -#define DIPHDA_DEVICE_BASE (0x1A000000) -#define DIPHDA_DEVICE_SIZE (0x26000000) -#define DIPHDA_MAP_DEVICE MAP_REGION_FLAT( \ - DIPHDA_DEVICE_BASE, \ - DIPHDA_DEVICE_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define ARM_IRQ_SEC_PHY_TIMER 29 - -#define ARM_IRQ_SEC_SGI_0 8 -#define ARM_IRQ_SEC_SGI_1 9 -#define ARM_IRQ_SEC_SGI_2 10 -#define ARM_IRQ_SEC_SGI_3 11 -#define ARM_IRQ_SEC_SGI_4 12 -#define ARM_IRQ_SEC_SGI_5 13 -#define ARM_IRQ_SEC_SGI_6 14 -#define ARM_IRQ_SEC_SGI_7 15 - -/* - * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define ARM_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE) - -#define ARM_G0_IRQ_PROPS(grp) \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ - GIC_INTR_CFG_EDGE) - -/* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ - ARM_G1S_IRQ_PROPS(grp), \ - INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \ - GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) - -#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) - -#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/diphda/platform.mk b/plat/arm/board/diphda/platform.mk deleted file mode 100644 index 8b89cee7e..000000000 --- a/plat/arm/board/diphda/platform.mk +++ /dev/null @@ -1,83 +0,0 @@ -# -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -# Making sure the diphda platform type is specified -ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),) - $(error TARGET_PLATFORM must be fpga or fvp) -endif - -DIPHDA_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S - -PLAT_INCLUDES := -Iplat/arm/board/diphda/common/include \ - -Iplat/arm/board/diphda/include \ - -Iinclude/plat/arm/common \ - -Iinclude/plat/arm/css/common/aarch64 - - -DIPHDA_FW_NVCTR_VAL := 255 -TFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL} -NTFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL} - -override NEED_BL1 := no - -override NEED_BL2 := yes -FIP_BL2_ARGS := tb-fw - -override NEED_BL2U := no -override NEED_BL31 := yes -NEED_BL32 := yes -override NEED_BL33 := yes - -# Include GICv2 driver files -include drivers/arm/gic/v2/gicv2.mk - -DIPHDA_GIC_SOURCES := ${GICV2_SOURCES} \ - plat/common/plat_gicv2.c \ - plat/arm/common/arm_gicv2.c - - -BL2_SOURCES += plat/arm/board/diphda/common/diphda_security.c \ - plat/arm/board/diphda/common/diphda_err.c \ - plat/arm/board/diphda/common/diphda_trusted_boot.c \ - lib/utils/mem_region.c \ - plat/arm/board/diphda/common/diphda_helpers.S \ - plat/arm/board/diphda/common/diphda_plat.c \ - plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \ - ${DIPHDA_CPU_LIBS} \ - - -BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ - lib/utils/mem_region.c \ - plat/arm/board/diphda/common/diphda_helpers.S \ - plat/arm/board/diphda/common/diphda_topology.c \ - plat/arm/board/diphda/common/diphda_security.c \ - plat/arm/board/diphda/common/diphda_plat.c \ - plat/arm/board/diphda/common/diphda_pm.c \ - ${DIPHDA_CPU_LIBS} \ - ${DIPHDA_GIC_SOURCES} - -ifneq (${ENABLE_STACK_PROTECTOR},0) - ifneq (${ENABLE_STACK_PROTECTOR},none) - DIPHDA_SECURITY_SOURCES := plat/arm/board/diphda/common/diphda_stack_protector.c - BL2_SOURCES += ${DIPHDA_SECURITY_SOURCES} - BL31_SOURCES += ${DIPHDA_SECURITY_SOURCES} - endif -endif - -FDT_SOURCES += plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts -DIPHDA_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb - -# Add the SPMC manifest to FIP and specify the same to certtool -$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG})) - -# Adding TARGET_PLATFORM as a GCC define (-D option) -$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) - -# Adding DIPHDA_FW_NVCTR_VAL as a GCC define (-D option) -$(eval $(call add_define,DIPHDA_FW_NVCTR_VAL)) - -include plat/arm/common/arm_common.mk -include plat/arm/board/common/board_common.mk diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index c45e04556..6d7aa2df5 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -282,7 +282,7 @@ endif ifeq (${JUNO_AARCH32_EL3_RUNTIME},1) BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c else -ifneq (${PLAT}, diphda) +ifneq (${PLAT}, corstone1000) BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c endif endif