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Merge "feat(plat/imx8m): add SiP call for secondary boot" into integration

This commit is contained in:
Madhukar Pappireddy 2021-06-02 15:45:29 +02:00 committed by TrustedFirmware Code Review
parent 203d48adca 9ce232fe98
commit 2512d0480f
5 changed files with 50 additions and 0 deletions
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32
plat/imx/common/imx_sip_handler.c
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@ -14,6 +14,7 @@
#include <common/runtime_svc.h>
#include <imx_sip_svc.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/mmio.h>
#include <sci/sci.h>
#if defined(PLAT_imx8qm) || defined(PLAT_imx8qx)
@ -145,6 +146,37 @@ int imx_misc_set_temp_handler(uint32_t smc_fid,
#endif /* defined(PLAT_imx8qm) || defined(PLAT_imx8qx) */
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
int imx_src_handler(uint32_t smc_fid,
u_register_t x1,
u_register_t x2,
u_register_t x3,
void *handle)
{
uint32_t val;
switch (x1) {
case IMX_SIP_SRC_SET_SECONDARY_BOOT:
if (x2 != 0U) {
mmio_setbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
SRC_GPR10_PERSIST_SECONDARY_BOOT);
} else {
mmio_clrbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
SRC_GPR10_PERSIST_SECONDARY_BOOT);
}
break;
case IMX_SIP_SRC_IS_SECONDARY_BOOT:
val = mmio_read_32(IMX_SRC_BASE + SRC_GPR10_OFFSET);
return !!(val & SRC_GPR10_PERSIST_SECONDARY_BOOT);
default:
return SMC_UNK;
};
return 0;
}
#endif /* defined(PLAT_imx8mm) || defined(PLAT_imx8mq) */
static uint64_t imx_get_commit_hash(u_register_t x2,
u_register_t x3,
u_register_t x4)

5
plat/imx/common/imx_sip_svc.c
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@ -47,6 +47,11 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid,
return imx_otp_handler(smc_fid, handle, x1, x2);
case IMX_SIP_MISC_SET_TEMP:
SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4));
#endif
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
case IMX_SIP_SRC:
SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle));
break;
#endif
case IMX_SIP_BUILDINFO:
SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4));

9
plat/imx/common/include/imx_sip_svc.h
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@ -17,6 +17,10 @@
#define IMX_SIP_BUILDINFO 0xC2000003
#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
#define IMX_SIP_SRC 0xC2000005
#define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10
#define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11
#define IMX_SIP_GET_SOC_INFO 0xC2000006
#define IMX_SIP_WAKEUP_SRC 0xC2000009
@ -38,6 +42,11 @@ int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3);
#endif
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
int imx_src_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3, void *handle);
#endif
#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3);

2
plat/imx/imx8m/imx8mm/include/platform_def.h
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@ -124,6 +124,8 @@
#define SRC_OTG1PHY_SCR U(0x20)
#define SRC_OTG2PHY_SCR U(0x24)
#define SRC_GPR1_OFFSET U(0x74)
#define SRC_GPR10_OFFSET U(0x98)
#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define SNVS_LPCR U(0x38)
#define SNVS_LPCR_SRTC_ENV BIT(0)

2
plat/imx/imx8m/imx8mq/include/platform_def.h
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@ -103,6 +103,8 @@
#define SRC_OTG1PHY_SCR U(0x20)
#define SRC_OTG2PHY_SCR U(0x24)
#define SRC_GPR1_OFFSET U(0x74)
#define SRC_GPR10_OFFSET U(0x98)
#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define SNVS_LPCR U(0x38)
#define SNVS_LPCR_SRTC_ENV BIT(0)