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Tegra186: trampoline: update "System Suspend" exit criteria 

The TZRAM memory loses its state during "System Suspend". This patch
check if TZRAM base address contains valid data, to decide if the system
is exiting from "System Suspend". To enable TZDRAM encryption, the Memory
Controller's TZDRAM base/size registers would be populated by the BPMP
when the system "wakes up".

Change-Id: I5fc8ba1ae3bce12f0ece493f6f9f5f4d92a46344
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2016-08-08 11:53:14 -07:00
parent 53451898a1
commit 25621454d5
1 changed files with 7 additions and 11 deletions
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18
plat/nvidia/tegra/soc/t186/plat_trampoline.S
View File

@ -42,18 +42,14 @@
/* CPU reset handler routine */ /* CPU reset handler routine */
func tegra186_cpu_reset_handler func tegra186_cpu_reset_handler
/* /*
* The Memory Controller loses state during System Suspend. We * The TZRAM loses state during System Suspend. We use this
* use this information to decide if the reset handler is running * information to decide if the reset handler is running after a
* after a System Suspend. Resume from system suspend requires * System Suspend. Resume from system suspend requires restoring
* restoring the entire state from TZDRAM to TZRAM. * the entire state from TZDRAM to TZRAM.
*/ */
mov x1, #TEGRA_MC_BASE mov x0, #BL31_BASE
ldr w0, [x1, #MC_SECURITY_CFG3_0] ldr x0, [x0]
lsl x0, x0, #32 cbnz x0, boot_cpu
ldr w0, [x1, #MC_SECURITY_CFG0_0]
adr x1, tegra186_cpu_reset_handler
cmp x0, x1
beq boot_cpu
/* resume from system suspend */ /* resume from system suspend */
mov x0, #BL31_BASE mov x0, #BL31_BASE