Merge changes I4bd4612a,Id13a06d4,I0ea7f610,Ie6a7063b into integration
* changes: mediatek: mt8192: Add Vcore DVFS driver mediatek: mt8192: Add SPM suspend driver mediatek: mt8192: supports mcusys off when system suspend mediatek: mt8192: Add lpm driver
This commit is contained in:
commit
258f6a2d40
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@ -0,0 +1,110 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <mt_lp_rm.h>
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#include <stddef.h>
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struct platform_mt_resource_manager {
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unsigned int count;
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struct mt_resource_manager *plat_rm;
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};
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static struct platform_mt_resource_manager plat_mt_rm;
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int mt_lp_rm_register(struct mt_resource_manager *rm)
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{
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unsigned int i;
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struct mt_resource_constraint *const *rc;
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if ((rm == NULL) || (rm->consts == NULL) ||
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(plat_mt_rm.plat_rm != NULL)) {
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return MT_RM_STATUS_BAD;
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}
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for (i = 0U, rc = rm->consts; *rc != NULL; i++, rc++) {
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if ((*rc)->init != NULL) {
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(*rc)->init();
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}
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}
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plat_mt_rm.plat_rm = rm;
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plat_mt_rm.count = i;
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return MT_RM_STATUS_OK;
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}
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int mt_lp_rm_reset_constraint(int idx, unsigned int cpuid, int stateid)
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{
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struct mt_resource_constraint const *rc = NULL;
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if ((plat_mt_rm.plat_rm == NULL) || (idx < 0) ||
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(idx >= plat_mt_rm.count)) {
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return MT_RM_STATUS_BAD;
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}
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rc = plat_mt_rm.plat_rm->consts[idx];
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if ((rc == NULL) || (rc->reset == NULL)) {
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return MT_RM_STATUS_BAD;
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}
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return rc->reset(cpuid, stateid);
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}
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int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
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int stateid, void *priv)
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{
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int i, res = MT_RM_STATUS_BAD;
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struct mt_resource_constraint *const *rc;
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struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
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if ((rm == NULL) || (idx < 0) || (idx >= plat_mt_rm.count)) {
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return res;
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}
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/* If subsys clk/mtcmos is on, add block-resource-off flag */
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if (rm->update != NULL) {
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res = rm->update(rm->consts, stateid, priv);
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if (res != 0) {
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return res;
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}
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}
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for (i = idx, rc = (rm->consts + idx); *rc != NULL; i++, rc++) {
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if (((*rc)->is_valid != NULL) &&
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((*rc)->is_valid(cpuid, stateid))) {
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if (((*rc)->run != NULL) &&
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((*rc)->run(cpuid, stateid) == 0)) {
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res = i;
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break;
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}
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}
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}
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return res;
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}
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int mt_lp_rm_do_update(int stateid, int type, void const *p)
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{
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int res = MT_RM_STATUS_BAD;
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struct mt_resource_constraint *const *rc;
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struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
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if (rm == NULL) {
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return res;
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}
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for (rc = rm->consts; *rc != NULL; rc++) {
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if ((*rc)->update != NULL) {
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res = (*rc)->update(stateid, type, p);
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if (res != MT_RM_STATUS_OK) {
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break;
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}
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}
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}
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return res;
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}
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_LP_RM_H
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#define MT_LP_RM_H
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#include <stdbool.h>
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#define MT_RM_STATUS_OK 0
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#define MT_RM_STATUS_BAD -1
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enum PLAT_MT_LPM_RC_TYPE {
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PLAT_RC_UPDATE_CONDITION,
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PLAT_RC_UPDATE_REMAIN_IRQS
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};
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struct mt_resource_constraint {
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int level;
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int (*init)(void);
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bool (*is_valid)(unsigned int cpu, int stateid);
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int (*update)(int stateid, int type, const void *p);
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int (*run)(unsigned int cpu, int stateid);
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int (*reset)(unsigned int cpu, int stateid);
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unsigned int (*allow)(int stateid);
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};
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struct mt_resource_manager {
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int (*update)(struct mt_resource_constraint **con,
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int stateid, void *priv);
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struct mt_resource_constraint **consts;
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};
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extern int mt_lp_rm_register(struct mt_resource_manager *rm);
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extern int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
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int stateid, void *priv);
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extern int mt_lp_rm_reset_constraint(int constraint_id, unsigned int cpuid,
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int stateid);
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extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
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#endif /* MT_LP_RM_H */
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@ -31,6 +31,10 @@
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#define MTK_SIP_KERNEL_BOOT_AARCH32 0x82000200
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#define MTK_SIP_KERNEL_BOOT_AARCH64 0xC2000200
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/* VCORE */
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#define MTK_SIP_VCORE_CONTROL_ARCH32 0x82000506
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#define MTK_SIP_VCORE_CONTROL_ARCH64 0xC2000506
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/* Mediatek SiP Calls error code */
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enum {
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MTK_SIP_E_SUCCESS = 0,
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@ -19,6 +19,8 @@ const mmap_region_t plat_mmap[] = {
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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{ 0 }
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};
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@ -19,6 +19,7 @@
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#include <emi_mpu/emi_mpu.h>
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#include <gpio/mtgpio.h>
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#include <mt_gic_v3.h>
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#include <mt_spm.h>
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#include <mt_timer.h>
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#include <mtk_dcm.h>
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#include <plat_params.h>
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@ -100,6 +101,7 @@ void bl31_platform_setup(void)
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plat_mt8192_gpio_init();
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mt_systimer_init();
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generic_delay_timer_init();
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spm_boot_init();
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}
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/*******************************************************************************
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@ -12,6 +12,8 @@
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#include <lib/spinlock.h>
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#include <mt_cpu_pm_cpc.h>
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#include <mt_lp_irqremain.h>
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#include <mt_lp_rm.h>
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#include <mt_mcdi.h>
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#include <plat_mtk_lpm.h>
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#include <plat_pm.h>
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@ -73,27 +75,49 @@ static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state)
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static int pwr_mcusys_pwron_finished(unsigned int cpu,
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const psci_power_state_t *state)
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{
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int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
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if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
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return -1;
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}
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mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id);
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mt_lp_irqremain_release();
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return 0;
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}
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static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
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{
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int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
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if (!IS_MCUSYS_OFF_STATE(state)) {
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goto mt_pwr_mcusysoff_break;
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}
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if (mcdi_try_init() != 0) { /* not ready to process mcusys-off */
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if (mcdi_try_init() != 0) {
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goto mt_pwr_mcusysoff_break;
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}
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if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) {
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goto mt_pwr_mcusysoff_break;
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}
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plat_mt_lp_cpu_rc =
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mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL);
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if (plat_mt_lp_cpu_rc < 0) {
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goto mt_pwr_mcusysoff_reflect;
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}
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mt_lp_irqremain_aquire();
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return 0;
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mt_pwr_mcusysoff_break:
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mt_pwr_mcusysoff_reflect:
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mtk_cpc_mcusys_off_reflect();
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mt_pwr_mcusysoff_break:
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plat_mt_lp_cpu_rc = -1;
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return -1;
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@ -119,5 +143,7 @@ const struct mt_lpm_tz *mt_plat_cpu_pm_init(void)
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INFO("MCDI init done.\n");
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}
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mt_lp_irqremain_init();
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return &plat_pm;
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}
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|
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@ -0,0 +1,150 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <mt_lp_rm.h>
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#include <mt_lp_irqremain.h>
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#include <plat_mtk_lpm.h>
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#include <plat_mt_cirq.h>
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#define EDMA0_IRQ_ID U(448)
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#define MDLA_IRQ_ID U(446)
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#define MALI4_IRQ_ID U(399)
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#define MALI3_IRQ_ID U(398)
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#define MALI2_IRQ_ID U(397)
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#define MALI1_IRQ_ID U(396)
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#define MALI0_IRQ_ID U(395)
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#define VPU_CORE1_IRQ_ID U(453)
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#define VPU_CORE0_IRQ_ID U(452)
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#define MD_WDT_IRQ_ID U(110)
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#define KEYPAD_IRQ_ID U(106)
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#define MD_WDT_WAKESRC 0x2000000
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#define KEYPAD_WAKESRC 0x4
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static struct mt_irqremain remain_irqs;
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int mt_lp_irqremain_submit(void)
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{
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if (remain_irqs.count == 0) {
|
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return -1;
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}
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set_wakeup_sources(remain_irqs.irqs, remain_irqs.count);
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mt_lp_rm_do_update(-1, PLAT_RC_UPDATE_REMAIN_IRQS, &remain_irqs);
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|
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return 0;
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}
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|
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int mt_lp_irqremain_aquire(void)
|
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{
|
||||
if (remain_irqs.count == 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
mt_cirq_sw_reset();
|
||||
mt_cirq_clone_gic();
|
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mt_cirq_enable();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt_lp_irqremain_release(void)
|
||||
{
|
||||
if (remain_irqs.count == 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
mt_cirq_flush();
|
||||
mt_cirq_disable();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mt_lp_irqremain_init(void)
|
||||
{
|
||||
uint32_t idx;
|
||||
|
||||
remain_irqs.count = 0;
|
||||
|
||||
/* level edma0 */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = EDMA0_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = 0;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* level mdla */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = MDLA_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = 0;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* level mali4 */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = MALI4_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = 0;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* level mali3 */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = MALI3_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = 0;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* level mali2 */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = MALI2_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = 0;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* level mali1 */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = MALI1_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = 0;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* level mali0 */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = MALI0_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = 0;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* level vpu core1 */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = VPU_CORE1_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = 0;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* level vpu core0 */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = VPU_CORE0_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = 0;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* edge mdwdt */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = MD_WDT_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = MD_WDT_WAKESRC;
|
||||
remain_irqs.count++;
|
||||
|
||||
/* edge keypad */
|
||||
idx = remain_irqs.count;
|
||||
remain_irqs.irqs[idx] = KEYPAD_IRQ_ID;
|
||||
remain_irqs.wakeupsrc_cat[idx] = 0;
|
||||
remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC;
|
||||
remain_irqs.count++;
|
||||
|
||||
mt_lp_irqremain_submit();
|
||||
}
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_LP_IRQREMAIN_H
|
||||
#define MT_LP_IRQREMAIN_H
|
||||
|
||||
extern int mt_lp_irqremain_submit(void);
|
||||
extern int mt_lp_irqremain_aquire(void);
|
||||
extern int mt_lp_irqremain_release(void);
|
||||
extern void mt_lp_irqremain_init(void);
|
||||
#endif /* MT_LP_IRQREMAIN_H */
|
|
@ -5,6 +5,7 @@
|
|||
*/
|
||||
|
||||
#include <cdefs.h>
|
||||
#include <common/debug.h>
|
||||
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
@ -144,5 +145,7 @@ int mcdi_try_init(void)
|
|||
mcdi_init_status = MCDI_INIT_DONE;
|
||||
}
|
||||
|
||||
INFO("mcdi ready for mcusys-off-idle and system suspend\n");
|
||||
|
||||
return (mcdi_init_status == MCDI_INIT_DONE) ? 0 : mcdi_init_status;
|
||||
}
|
||||
|
|
|
@ -0,0 +1,68 @@
|
|||
#
|
||||
# Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Enable or disable spm feature
|
||||
MT_SPM_FEATURE_SUPPORT = yes
|
||||
|
||||
# Enable or disable cirq restore
|
||||
MT_SPM_CIRQ_FEATURE_SUPPORT = yes
|
||||
|
||||
# sspm notifier support
|
||||
MT_SPM_SSPM_NOTIFIER_SUPPORT = yes
|
||||
|
||||
CUR_SPM_FOLDER = ${MTK_PLAT_SOC}/drivers/spm
|
||||
|
||||
# spm common files
|
||||
PLAT_SPM_SOURCE_FILES_COMMON += \
|
||||
${CUR_SPM_FOLDER}/mt_spm.c \
|
||||
${CUR_SPM_FOLDER}/mt_spm_conservation.c \
|
||||
${CUR_SPM_FOLDER}/mt_spm_internal.c \
|
||||
${CUR_SPM_FOLDER}/mt_spm_pmic_wrap.c \
|
||||
${CUR_SPM_FOLDER}/mt_spm_vcorefs.c
|
||||
|
||||
# spm platform dependcy files
|
||||
PLAT_SPM_SOURCE_FILES += \
|
||||
${CUR_SPM_FOLDER}/constraints/mt_spm_rc_bus26m.c \
|
||||
${CUR_SPM_FOLDER}/constraints/mt_spm_rc_cpu_buck_ldo.c \
|
||||
${CUR_SPM_FOLDER}/constraints/mt_spm_rc_dram.c \
|
||||
${CUR_SPM_FOLDER}/constraints/mt_spm_rc_syspll.c \
|
||||
${CUR_SPM_FOLDER}/mt_spm_cond.c \
|
||||
${CUR_SPM_FOLDER}/mt_spm_suspend.c \
|
||||
${CUR_SPM_FOLDER}/mt_spm_idle.c
|
||||
|
||||
ifeq (${MT_SPM_FEATURE_SUPPORT}, no)
|
||||
PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_UNSUPPORT
|
||||
BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${PLAT_SPM_SOURCE_FILES_COMMON}
|
||||
else
|
||||
BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \
|
||||
${PLAT_SPM_SOURCE_FILES_COMMON} \
|
||||
${PLAT_SPM_SOURCE_FILES}
|
||||
endif
|
||||
|
||||
ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT}, no)
|
||||
PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_CIRQ_UNSUPPORT
|
||||
endif
|
||||
|
||||
ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT}, no)
|
||||
PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
|
||||
else
|
||||
BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \
|
||||
${CUR_SPM_FOLDER}/notifier/mt_spm_sspm_notifier.c
|
||||
endif
|
||||
|
||||
$(info --------------------------------------)
|
||||
$(info SPM build flags: ${PLAT_SPM_DEBUG_CFLAGS})
|
||||
$(info SPM build files: ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES})
|
||||
$(info --------------------------------------)
|
||||
|
||||
# Common makefile for platform.mk
|
||||
PLAT_INCLUDES += \
|
||||
${PLAT_SPM_DEBUG_CFLAGS} \
|
||||
-I${CUR_SPM_FOLDER}/ \
|
||||
-I${CUR_SPM_FOLDER}/constraints/ \
|
||||
-I${CUR_SPM_FOLDER}/notifier/
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES}
|
|
@ -0,0 +1,230 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
|
||||
#include <mt_lp_rm.h>
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_cond.h>
|
||||
#include <mt_spm_constraint.h>
|
||||
#include <mt_spm_conservation.h>
|
||||
#include <mt_spm_idle.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_notifier.h>
|
||||
#include <mt_spm_rc_internal.h>
|
||||
#include <mt_spm_resource_req.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_suspend.h>
|
||||
#include <plat_pm.h>
|
||||
#include <plat_mtk_lpm.h>
|
||||
|
||||
#ifndef ATF_PLAT_CIRQ_UNSUPPORT
|
||||
#include <mt_gic_v3.h>
|
||||
#include <plat_mt_cirq.h>
|
||||
#endif
|
||||
|
||||
#define CONSTRAINT_BUS26M_ALLOW \
|
||||
(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
|
||||
MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
|
||||
MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
|
||||
MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
|
||||
MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
|
||||
MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
|
||||
|
||||
#define CONSTRAINT_BUS26M_PCM_FLAG \
|
||||
(SPM_FLAG_DISABLE_INFRA_PDN | \
|
||||
SPM_FLAG_DISABLE_VCORE_DVS | \
|
||||
SPM_FLAG_DISABLE_VCORE_DFS | \
|
||||
SPM_FLAG_SRAM_SLEEP_CTRL | \
|
||||
SPM_FLAG_ENABLE_TIA_WORKAROUND | \
|
||||
SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
|
||||
SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
|
||||
|
||||
#define CONSTRAINT_BUS26M_PCM_FLAG1 \
|
||||
(SPM_FLAG1_DISABLE_MD26M_CK_OFF)
|
||||
|
||||
#define CONSTRAINT_BUS26M_RESOURCE_REQ 0U
|
||||
|
||||
static unsigned int bus26m_ext_opand;
|
||||
static struct mt_irqremain *refer2remain_irq;
|
||||
static struct mt_spm_cond_tables cond_bus26m = {
|
||||
.name = "bus26m",
|
||||
.table_cg = {
|
||||
0x07CBF1FC, /* MTCMOS1 */
|
||||
0x0A0D8856, /* INFRA0 */
|
||||
0x03AF9A00, /* INFRA1 */
|
||||
0x86000650, /* INFRA2 */
|
||||
0xC800C000, /* INFRA3 */
|
||||
0x00000000, /* INFRA4 */
|
||||
0x4000007C, /* INFRA5 */
|
||||
0x280E0800, /* MMSYS0 */
|
||||
0x00000001, /* MMSYS1 */
|
||||
0x00000000, /* MMSYS2 */
|
||||
},
|
||||
.table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL |
|
||||
PLL_BIT_MSDCPLL | PLL_BIT_TVDPLL |
|
||||
PLL_BIT_MMPLL),
|
||||
};
|
||||
|
||||
static struct mt_spm_cond_tables cond_bus26m_res = {
|
||||
.table_cg = { 0U },
|
||||
.table_pll = 0U,
|
||||
};
|
||||
|
||||
static struct constraint_status status = {
|
||||
.id = MT_RM_CONSTRAINT_ID_BUS26M,
|
||||
.valid = (MT_SPM_RC_VALID_SW |
|
||||
MT_SPM_RC_VALID_COND_LATCH),
|
||||
.cond_block = 0U,
|
||||
.enter_cnt = 0U,
|
||||
.cond_res = &cond_bus26m_res,
|
||||
};
|
||||
|
||||
/*
|
||||
* Cirq will take the place of gic when gic is off.
|
||||
* However, cirq cannot work if 26m clk is turned off when system idle/suspend.
|
||||
* Therefore, we need to set irq pending for specific wakeup source.
|
||||
*/
|
||||
#ifdef ATF_PLAT_CIRQ_UNSUPPORT
|
||||
#define do_irqs_delivery()
|
||||
#else
|
||||
static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
|
||||
unsigned int irq_index,
|
||||
struct wake_status *wakeup)
|
||||
{
|
||||
INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
|
||||
wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
|
||||
wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
|
||||
wakeup->tr.comm.b_sw_flag1);
|
||||
|
||||
INFO("irq:%u(0x%08x) set pending\n",
|
||||
irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
|
||||
}
|
||||
|
||||
static void do_irqs_delivery(void)
|
||||
{
|
||||
unsigned int idx;
|
||||
int res = 0;
|
||||
struct wake_status *wakeup = NULL;
|
||||
struct mt_irqremain *irqs = refer2remain_irq;
|
||||
|
||||
res = spm_conservation_get_result(&wakeup);
|
||||
|
||||
if ((res != 0) && (irqs == NULL)) {
|
||||
return;
|
||||
}
|
||||
|
||||
for (idx = 0U; idx < irqs->count; ++idx) {
|
||||
if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
|
||||
((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
|
||||
if ((irqs->wakeupsrc_cat[idx] &
|
||||
MT_IRQ_REMAIN_CAT_LOG) != 0U) {
|
||||
mt_spm_irq_remain_dump(irqs, idx, wakeup);
|
||||
}
|
||||
|
||||
mt_irq_set_pending(irqs->irqs[idx]);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp,
|
||||
unsigned int *resource_req)
|
||||
{
|
||||
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
|
||||
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
|
||||
*resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
|
||||
}
|
||||
|
||||
bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
|
||||
{
|
||||
(void)cpu;
|
||||
(void)state_id;
|
||||
|
||||
return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
|
||||
}
|
||||
|
||||
int spm_update_rc_bus26m(int state_id, int type, const void *val)
|
||||
{
|
||||
const struct mt_spm_cond_tables *tlb;
|
||||
const struct mt_spm_cond_tables *tlb_check;
|
||||
int res = MT_RM_STATUS_OK;
|
||||
|
||||
if (val == NULL) {
|
||||
return MT_RM_STATUS_BAD;
|
||||
}
|
||||
|
||||
if (type == PLAT_RC_UPDATE_CONDITION) {
|
||||
tlb = (const struct mt_spm_cond_tables *)val;
|
||||
tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
|
||||
|
||||
status.cond_block =
|
||||
mt_spm_cond_check(state_id, tlb, tlb_check,
|
||||
((status.valid &
|
||||
MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
|
||||
&cond_bus26m_res : NULL);
|
||||
} else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
|
||||
refer2remain_irq = (struct mt_irqremain *)val;
|
||||
} else {
|
||||
res = MT_RM_STATUS_BAD;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
unsigned int spm_allow_rc_bus26m(int state_id)
|
||||
{
|
||||
(void)state_id;
|
||||
|
||||
return CONSTRAINT_BUS26M_ALLOW;
|
||||
}
|
||||
|
||||
int spm_run_rc_bus26m(unsigned int cpu, int state_id)
|
||||
{
|
||||
(void)cpu;
|
||||
|
||||
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
|
||||
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
|
||||
(IS_PLAT_SUSPEND_ID(state_id) ?
|
||||
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
|
||||
#endif
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
mt_spm_suspend_enter(state_id,
|
||||
(MT_SPM_EX_OP_SET_WDT |
|
||||
MT_SPM_EX_OP_HW_S1_DETECT |
|
||||
bus26m_ext_opand),
|
||||
CONSTRAINT_BUS26M_RESOURCE_REQ);
|
||||
} else {
|
||||
mt_spm_idle_generic_enter(state_id, MT_SPM_EX_OP_HW_S1_DETECT,
|
||||
spm_bus26m_conduct);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
|
||||
{
|
||||
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
|
||||
|
||||
(void)cpu;
|
||||
|
||||
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
|
||||
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
|
||||
#endif
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
|
||||
mt_spm_suspend_resume(state_id, ext_op, NULL);
|
||||
bus26m_ext_opand = 0U;
|
||||
} else {
|
||||
mt_spm_idle_generic_resume(state_id, ext_op, NULL);
|
||||
status.enter_cnt++;
|
||||
}
|
||||
|
||||
do_irqs_delivery();
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_cond.h>
|
||||
#include <mt_spm_constraint.h>
|
||||
#include <mt_spm_conservation.h>
|
||||
#include <mt_spm_idle.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_notifier.h>
|
||||
#include <mt_spm_rc_internal.h>
|
||||
#include <mt_spm_resource_req.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_suspend.h>
|
||||
#include <plat_pm.h>
|
||||
|
||||
#define CONSTRAINT_CPU_BUCK_PCM_FLAG \
|
||||
(SPM_FLAG_DISABLE_INFRA_PDN | \
|
||||
SPM_FLAG_DISABLE_VCORE_DVS | \
|
||||
SPM_FLAG_DISABLE_VCORE_DFS | \
|
||||
SPM_FLAG_SRAM_SLEEP_CTRL | \
|
||||
SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
|
||||
|
||||
#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 0U
|
||||
|
||||
#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ \
|
||||
(MT_SPM_DRAM_S1 | \
|
||||
MT_SPM_DRAM_S0 | \
|
||||
MT_SPM_SYSPLL | \
|
||||
MT_SPM_INFRA | \
|
||||
MT_SPM_26M | \
|
||||
MT_SPM_XO_FPM)
|
||||
|
||||
|
||||
static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW;
|
||||
static unsigned int cpubuckldo_enter_cnt;
|
||||
|
||||
static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp,
|
||||
unsigned int *resource_req)
|
||||
{
|
||||
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
|
||||
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
|
||||
*resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
|
||||
}
|
||||
|
||||
bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
|
||||
{
|
||||
(void)cpu;
|
||||
(void)state_id;
|
||||
|
||||
return IS_MT_RM_RC_READY(cpubuckldo_status);
|
||||
}
|
||||
|
||||
unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
|
||||
{
|
||||
(void)state_id;
|
||||
|
||||
return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
|
||||
}
|
||||
|
||||
int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
|
||||
{
|
||||
(void)cpu;
|
||||
|
||||
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
|
||||
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
|
||||
(IS_PLAT_SUSPEND_ID(state_id) ?
|
||||
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
|
||||
#endif
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
mt_spm_suspend_enter(state_id,
|
||||
MT_SPM_EX_OP_SET_WDT,
|
||||
CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
|
||||
} else {
|
||||
mt_spm_idle_generic_enter(state_id, 0U,
|
||||
spm_cpu_bcuk_ldo_conduct);
|
||||
}
|
||||
|
||||
cpubuckldo_enter_cnt++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
|
||||
{
|
||||
(void)cpu;
|
||||
|
||||
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
|
||||
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
|
||||
#endif
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
|
||||
} else {
|
||||
mt_spm_idle_generic_resume(state_id, 0U, NULL);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
|
||||
#include <mt_lp_rm.h>
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_cond.h>
|
||||
#include <mt_spm_constraint.h>
|
||||
#include <mt_spm_conservation.h>
|
||||
#include <mt_spm_idle.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_notifier.h>
|
||||
#include <mt_spm_resource_req.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_rc_internal.h>
|
||||
#include <mt_spm_suspend.h>
|
||||
#include <plat_pm.h>
|
||||
#include <plat_mtk_lpm.h>
|
||||
|
||||
#define CONSTRAINT_DRAM_ALLOW \
|
||||
(MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
|
||||
MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
|
||||
MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
|
||||
|
||||
#define CONSTRAINT_DRAM_PCM_FLAG \
|
||||
(SPM_FLAG_DISABLE_INFRA_PDN | \
|
||||
SPM_FLAG_DISABLE_VCORE_DVS | \
|
||||
SPM_FLAG_DISABLE_VCORE_DFS | \
|
||||
SPM_FLAG_SRAM_SLEEP_CTRL | \
|
||||
SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
|
||||
|
||||
#define CONSTRAINT_DRAM_PCM_FLAG1 0U
|
||||
|
||||
#define CONSTRAINT_DRAM_RESOURCE_REQ \
|
||||
(MT_SPM_SYSPLL | \
|
||||
MT_SPM_INFRA | \
|
||||
MT_SPM_26M)
|
||||
|
||||
static struct mt_spm_cond_tables cond_dram = {
|
||||
.name = "dram",
|
||||
.table_cg = {
|
||||
0x078BF1FC, /* MTCMOS1 */
|
||||
0x080D8856, /* INFRA0 */
|
||||
0x03AF9A00, /* INFRA1 */
|
||||
0x86000640, /* INFRA2 */
|
||||
0xC800C000, /* INFRA3 */
|
||||
0x00000000, /* INFRA4 */
|
||||
0x00000000, /* INFRA5 */
|
||||
0x200C0000, /* MMSYS0 */
|
||||
0x00000000, /* MMSYS1 */
|
||||
0x00000000, /* MMSYS2 */
|
||||
},
|
||||
.table_pll = 0U,
|
||||
};
|
||||
|
||||
static struct mt_spm_cond_tables cond_dram_res = {
|
||||
.table_cg = { 0U },
|
||||
.table_pll = 0U,
|
||||
};
|
||||
|
||||
static struct constraint_status status = {
|
||||
.id = MT_RM_CONSTRAINT_ID_DRAM,
|
||||
.valid = (MT_SPM_RC_VALID_SW |
|
||||
MT_SPM_RC_VALID_COND_LATCH |
|
||||
MT_SPM_RC_VALID_XSOC_BBLPM),
|
||||
.cond_block = 0U,
|
||||
.enter_cnt = 0U,
|
||||
.cond_res = &cond_dram_res,
|
||||
};
|
||||
|
||||
static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
|
||||
unsigned int *resource_req)
|
||||
{
|
||||
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
|
||||
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
|
||||
*resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
|
||||
}
|
||||
|
||||
bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
|
||||
{
|
||||
(void)cpu;
|
||||
(void)state_id;
|
||||
|
||||
return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
|
||||
}
|
||||
|
||||
int spm_update_rc_dram(int state_id, int type, const void *val)
|
||||
{
|
||||
const struct mt_spm_cond_tables *tlb;
|
||||
const struct mt_spm_cond_tables *tlb_check;
|
||||
int res = MT_RM_STATUS_OK;
|
||||
|
||||
if (val == NULL) {
|
||||
return MT_RM_STATUS_BAD;
|
||||
}
|
||||
|
||||
if (type == PLAT_RC_UPDATE_CONDITION) {
|
||||
tlb = (const struct mt_spm_cond_tables *)val;
|
||||
tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
|
||||
status.cond_block =
|
||||
mt_spm_cond_check(state_id, tlb, tlb_check,
|
||||
((status.valid &
|
||||
MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
|
||||
&cond_dram_res : NULL);
|
||||
} else {
|
||||
res = MT_RM_STATUS_BAD;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
unsigned int spm_allow_rc_dram(int state_id)
|
||||
{
|
||||
(void)state_id;
|
||||
|
||||
return CONSTRAINT_DRAM_ALLOW;
|
||||
}
|
||||
|
||||
int spm_run_rc_dram(unsigned int cpu, int state_id)
|
||||
{
|
||||
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
|
||||
unsigned int allows = CONSTRAINT_DRAM_ALLOW;
|
||||
|
||||
(void)cpu;
|
||||
|
||||
if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
|
||||
#ifdef MT_SPM_USING_SRCLKEN_RC
|
||||
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
|
||||
#else
|
||||
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
|
||||
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
|
||||
(IS_PLAT_SUSPEND_ID(state_id) ?
|
||||
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
|
||||
#else
|
||||
(void)allows;
|
||||
#endif
|
||||
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
mt_spm_suspend_enter(state_id,
|
||||
(MT_SPM_EX_OP_SET_WDT |
|
||||
MT_SPM_EX_OP_HW_S1_DETECT),
|
||||
CONSTRAINT_DRAM_RESOURCE_REQ);
|
||||
} else {
|
||||
mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spm_reset_rc_dram(unsigned int cpu, int state_id)
|
||||
{
|
||||
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
|
||||
unsigned int allows = CONSTRAINT_DRAM_ALLOW;
|
||||
|
||||
(void)cpu;
|
||||
|
||||
if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
|
||||
#ifdef MT_SPM_USING_SRCLKEN_RC
|
||||
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
|
||||
#else
|
||||
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
|
||||
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
|
||||
#else
|
||||
(void)allows;
|
||||
#endif
|
||||
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
mt_spm_suspend_resume(state_id,
|
||||
(MT_SPM_EX_OP_SET_WDT |
|
||||
MT_SPM_EX_OP_HW_S1_DETECT),
|
||||
NULL);
|
||||
} else {
|
||||
mt_spm_idle_generic_resume(state_id, ext_op, NULL);
|
||||
status.enter_cnt++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_RC_INTERNAL_H
|
||||
#define MT_SPM_RC_INTERNAL_H
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#define SPM_FLAG_SRAM_SLEEP_CTRL \
|
||||
(SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP | \
|
||||
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
|
||||
SPM_FLAG_DISABLE_SYSRAM_SLEEP | \
|
||||
SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP | \
|
||||
SPM_FLAG_DISABLE_SRAM_EVENT)
|
||||
|
||||
/* cpu buck/ldo constraint function */
|
||||
bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
|
||||
unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
|
||||
int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
|
||||
int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
|
||||
|
||||
/* spm resource dram constraint function */
|
||||
bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
|
||||
int spm_update_rc_dram(int state_id, int type, const void *val);
|
||||
unsigned int spm_allow_rc_dram(int state_id);
|
||||
int spm_run_rc_dram(unsigned int cpu, int state_id);
|
||||
int spm_reset_rc_dram(unsigned int cpu, int state_id);
|
||||
|
||||
/* spm resource syspll constraint function */
|
||||
bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
|
||||
int spm_update_rc_syspll(int state_id, int type, const void *val);
|
||||
unsigned int spm_allow_rc_syspll(int state_id);
|
||||
int spm_run_rc_syspll(unsigned int cpu, int state_id);
|
||||
int spm_reset_rc_syspll(unsigned int cpu, int state_id);
|
||||
|
||||
/* spm resource bus26m constraint function */
|
||||
bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
|
||||
int spm_update_rc_bus26m(int state_id, int type, const void *val);
|
||||
unsigned int spm_allow_rc_bus26m(int state_id);
|
||||
int spm_run_rc_bus26m(unsigned int cpu, int state_id);
|
||||
int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
|
||||
#endif /* MT_SPM_RC_INTERNAL_H */
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
|
||||
#include <mt_lp_rm.h>
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_cond.h>
|
||||
#include <mt_spm_constraint.h>
|
||||
#include <mt_spm_conservation.h>
|
||||
#include <mt_spm_idle.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_notifier.h>
|
||||
#include <mt_spm_rc_internal.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_resource_req.h>
|
||||
#include <mt_spm_suspend.h>
|
||||
#include <plat_pm.h>
|
||||
#include <plat_mtk_lpm.h>
|
||||
|
||||
#define CONSTRAINT_SYSPLL_ALLOW \
|
||||
(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
|
||||
MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
|
||||
MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
|
||||
MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
|
||||
|
||||
#define CONSTRAINT_SYSPLL_PCM_FLAG \
|
||||
(SPM_FLAG_DISABLE_INFRA_PDN | \
|
||||
SPM_FLAG_DISABLE_VCORE_DVS | \
|
||||
SPM_FLAG_DISABLE_VCORE_DFS | \
|
||||
SPM_FLAG_SRAM_SLEEP_CTRL | \
|
||||
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
|
||||
SPM_FLAG_ENABLE_6315_CTRL | \
|
||||
SPM_FLAG_USE_SRCCLKENO2)
|
||||
|
||||
#define CONSTRAINT_SYSPLL_PCM_FLAG1 0U
|
||||
#define CONSTRAINT_SYSPLL_RESOURCE_REQ \
|
||||
(MT_SPM_26M)
|
||||
|
||||
static struct mt_spm_cond_tables cond_syspll = {
|
||||
.name = "syspll",
|
||||
.table_cg = {
|
||||
0x078BF1FC, /* MTCMOS1 */
|
||||
0x080D8856, /* INFRA0 */
|
||||
0x03AF9A00, /* INFRA1 */
|
||||
0x86000640, /* INFRA2 */
|
||||
0xC800C000, /* INFRA3 */
|
||||
0x00000000, /* INFRA4 */
|
||||
0x0000007C, /* INFRA5 */
|
||||
0x280E0800, /* MMSYS0 */
|
||||
0x00000001, /* MMSYS1 */
|
||||
0x00000000, /* MMSYS2 */
|
||||
},
|
||||
.table_pll = 0U,
|
||||
};
|
||||
|
||||
static struct mt_spm_cond_tables cond_syspll_res = {
|
||||
.table_cg = { 0U },
|
||||
.table_pll = 0U,
|
||||
};
|
||||
|
||||
static struct constraint_status status = {
|
||||
.id = MT_RM_CONSTRAINT_ID_SYSPLL,
|
||||
.valid = (MT_SPM_RC_VALID_SW |
|
||||
MT_SPM_RC_VALID_COND_LATCH |
|
||||
MT_SPM_RC_VALID_XSOC_BBLPM),
|
||||
.cond_block = 0U,
|
||||
.enter_cnt = 0U,
|
||||
.cond_res = &cond_syspll_res,
|
||||
};
|
||||
|
||||
static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
|
||||
unsigned int *resource_req)
|
||||
{
|
||||
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
|
||||
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
|
||||
*resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
|
||||
}
|
||||
|
||||
bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
|
||||
{
|
||||
(void)cpu;
|
||||
(void)state_id;
|
||||
|
||||
return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
|
||||
}
|
||||
|
||||
int spm_update_rc_syspll(int state_id, int type, const void *val)
|
||||
{
|
||||
const struct mt_spm_cond_tables *tlb;
|
||||
const struct mt_spm_cond_tables *tlb_check;
|
||||
int res = MT_RM_STATUS_OK;
|
||||
|
||||
if (val == NULL) {
|
||||
return MT_RM_STATUS_BAD;
|
||||
}
|
||||
|
||||
if (type == PLAT_RC_UPDATE_CONDITION) {
|
||||
tlb = (const struct mt_spm_cond_tables *)val;
|
||||
tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
|
||||
|
||||
status.cond_block =
|
||||
mt_spm_cond_check(state_id, tlb, tlb_check,
|
||||
((status.valid &
|
||||
MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
|
||||
&cond_syspll_res : NULL);
|
||||
} else {
|
||||
res = MT_RM_STATUS_BAD;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
unsigned int spm_allow_rc_syspll(int state_id)
|
||||
{
|
||||
(void)state_id;
|
||||
|
||||
return CONSTRAINT_SYSPLL_ALLOW;
|
||||
}
|
||||
|
||||
int spm_run_rc_syspll(unsigned int cpu, int state_id)
|
||||
{
|
||||
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
|
||||
unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
|
||||
|
||||
(void)cpu;
|
||||
|
||||
if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
|
||||
#ifdef MT_SPM_USING_SRCLKEN_RC
|
||||
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
|
||||
#else
|
||||
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
|
||||
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
|
||||
(IS_PLAT_SUSPEND_ID(state_id) ?
|
||||
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
|
||||
#else
|
||||
(void)allows;
|
||||
#endif
|
||||
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
mt_spm_suspend_enter(state_id,
|
||||
(MT_SPM_EX_OP_SET_WDT |
|
||||
MT_SPM_EX_OP_HW_S1_DETECT |
|
||||
MT_SPM_EX_OP_SET_SUSPEND_MODE),
|
||||
CONSTRAINT_SYSPLL_RESOURCE_REQ);
|
||||
} else {
|
||||
mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spm_reset_rc_syspll(unsigned int cpu, int state_id)
|
||||
{
|
||||
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
|
||||
unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
|
||||
|
||||
(void)cpu;
|
||||
|
||||
if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
|
||||
#ifdef MT_SPM_USING_SRCLKEN_RC
|
||||
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
|
||||
#else
|
||||
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
|
||||
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
|
||||
#else
|
||||
(void)allows;
|
||||
#endif
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
mt_spm_suspend_resume(state_id,
|
||||
(MT_SPM_EX_OP_SET_SUSPEND_MODE |
|
||||
MT_SPM_EX_OP_SET_WDT |
|
||||
MT_SPM_EX_OP_HW_S1_DETECT),
|
||||
NULL);
|
||||
} else {
|
||||
mt_spm_idle_generic_resume(state_id, ext_op, NULL);
|
||||
status.enter_cnt++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
#include <common/debug.h>
|
||||
#include <lib/bakery_lock.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <mt_lp_rm.h>
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_cond.h>
|
||||
#include <mt_spm_conservation.h>
|
||||
#include <mt_spm_constraint.h>
|
||||
#include <mt_spm_idle.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_pmic_wrap.h>
|
||||
#include <mt_spm_rc_internal.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_resource_req.h>
|
||||
#include <mt_spm_suspend.h>
|
||||
#include <mtk_plat_common.h>
|
||||
#include <plat_mtk_lpm.h>
|
||||
#include <plat_pm.h>
|
||||
#include <platform_def.h>
|
||||
#include <sleep_def.h>
|
||||
|
||||
#ifdef MT_SPM_USING_BAKERY_LOCK
|
||||
DEFINE_BAKERY_LOCK(spm_lock);
|
||||
#define plat_spm_lock_init() bakery_lock_init(&spm_lock)
|
||||
#else
|
||||
spinlock_t spm_lock;
|
||||
#define plat_spm_lock_init()
|
||||
#endif
|
||||
|
||||
/* CLK_SCP_CFG_0 */
|
||||
#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
|
||||
#define SPM_CK_CONTROL_EN 0x3FF
|
||||
|
||||
/* CLK_SCP_CFG_1 */
|
||||
#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x210)
|
||||
#define CLK_SCP_CFG_1_MASK 0x100C
|
||||
#define CLK_SCP_CFG_1_SPM 0x3
|
||||
|
||||
struct mt_resource_constraint plat_constraint_bus26m = {
|
||||
.is_valid = spm_is_valid_rc_bus26m,
|
||||
.update = spm_update_rc_bus26m,
|
||||
.allow = spm_allow_rc_bus26m,
|
||||
.run = spm_run_rc_bus26m,
|
||||
.reset = spm_reset_rc_bus26m,
|
||||
};
|
||||
|
||||
struct mt_resource_constraint plat_constraint_syspll = {
|
||||
.is_valid = spm_is_valid_rc_syspll,
|
||||
.update = spm_update_rc_syspll,
|
||||
.allow = spm_allow_rc_syspll,
|
||||
.run = spm_run_rc_syspll,
|
||||
.reset = spm_reset_rc_syspll,
|
||||
};
|
||||
|
||||
struct mt_resource_constraint plat_constraint_dram = {
|
||||
.is_valid = spm_is_valid_rc_dram,
|
||||
.update = spm_update_rc_dram,
|
||||
.allow = spm_allow_rc_dram,
|
||||
.run = spm_run_rc_dram,
|
||||
.reset = spm_reset_rc_dram,
|
||||
};
|
||||
|
||||
struct mt_resource_constraint plat_constraint_cpu = {
|
||||
.is_valid = spm_is_valid_rc_cpu_buck_ldo,
|
||||
.update = NULL,
|
||||
.allow = spm_allow_rc_cpu_buck_ldo,
|
||||
.run = spm_run_rc_cpu_buck_ldo,
|
||||
.reset = spm_reset_rc_cpu_buck_ldo,
|
||||
};
|
||||
|
||||
struct mt_resource_constraint *plat_constraints[] = {
|
||||
&plat_constraint_bus26m,
|
||||
&plat_constraint_syspll,
|
||||
&plat_constraint_dram,
|
||||
&plat_constraint_cpu,
|
||||
NULL,
|
||||
};
|
||||
|
||||
struct mt_resource_manager plat_mt8192_rm = {
|
||||
.update = mt_spm_cond_update,
|
||||
.consts = plat_constraints,
|
||||
};
|
||||
|
||||
void spm_boot_init(void)
|
||||
{
|
||||
/* switch ck_off/axi_26m control to SPM */
|
||||
mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
|
||||
mmio_clrsetbits_32(CLK_SCP_CFG_1, CLK_SCP_CFG_1_MASK,
|
||||
CLK_SCP_CFG_1_SPM);
|
||||
|
||||
plat_spm_lock_init();
|
||||
mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
|
||||
mt_lp_rm_register(&plat_mt8192_rm);
|
||||
mt_spm_idle_generic_init();
|
||||
mt_spm_suspend_init();
|
||||
}
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_H
|
||||
#define MT_SPM_H
|
||||
|
||||
#include <lib/bakery_lock.h>
|
||||
#include <lib/spinlock.h>
|
||||
|
||||
#include <plat_mtk_lpm.h>
|
||||
|
||||
/*
|
||||
* ARM v8.2, the cache will turn off automatically when cpu
|
||||
* power down. So, there is no doubt to use the spin_lock here
|
||||
*/
|
||||
#if !HW_ASSISTED_COHERENCY
|
||||
#define MT_SPM_USING_BAKERY_LOCK
|
||||
#endif
|
||||
|
||||
#ifdef MT_SPM_USING_BAKERY_LOCK
|
||||
DECLARE_BAKERY_LOCK(spm_lock);
|
||||
#define plat_spm_lock() bakery_lock_get(&spm_lock)
|
||||
#define plat_spm_unlock() bakery_lock_release(&spm_lock)
|
||||
#else
|
||||
extern spinlock_t spm_lock;
|
||||
#define plat_spm_lock() spin_lock(&spm_lock)
|
||||
#define plat_spm_unlock() spin_unlock(&spm_lock)
|
||||
#endif
|
||||
|
||||
#define MT_SPM_USING_SRCLKEN_RC
|
||||
|
||||
/* spm extern operand definition */
|
||||
#define MT_SPM_EX_OP_CLR_26M_RECORD (1U << 0)
|
||||
#define MT_SPM_EX_OP_SET_WDT (1U << 1)
|
||||
#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ (1U << 2)
|
||||
#define MT_SPM_EX_OP_SET_SUSPEND_MODE (1U << 3)
|
||||
#define MT_SPM_EX_OP_SET_IS_ADSP (1U << 4)
|
||||
#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM (1U << 5)
|
||||
#define MT_SPM_EX_OP_HW_S1_DETECT (1U << 6)
|
||||
|
||||
typedef enum {
|
||||
WR_NONE = 0,
|
||||
WR_UART_BUSY = 1,
|
||||
WR_ABORT = 2,
|
||||
WR_PCM_TIMER = 3,
|
||||
WR_WAKE_SRC = 4,
|
||||
WR_DVFSRC = 5,
|
||||
WR_TWAM = 6,
|
||||
WR_PMSR = 7,
|
||||
WR_SPM_ACK_CHK = 8,
|
||||
WR_UNKNOWN = 9,
|
||||
} wake_reason_t;
|
||||
|
||||
static inline void spm_lock_get(void)
|
||||
{
|
||||
plat_spm_lock();
|
||||
}
|
||||
|
||||
static inline void spm_lock_release(void)
|
||||
{
|
||||
plat_spm_unlock();
|
||||
}
|
||||
|
||||
extern void spm_boot_init(void);
|
||||
#endif /* MT_SPM_H */
|
|
@ -0,0 +1,214 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <mt_spm_cond.h>
|
||||
#include <mt_spm_conservation.h>
|
||||
#include <mt_spm_constraint.h>
|
||||
#include <plat_mtk_lpm.h>
|
||||
#include <plat_pm.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
|
||||
#define MT_LP_TZ_MM_REG(ofs) (MMSYS_BASE + ofs)
|
||||
#define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
|
||||
#define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEN_BASE + ofs)
|
||||
#define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs)
|
||||
|
||||
#define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C)
|
||||
#define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170)
|
||||
#define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0094)
|
||||
#define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0090)
|
||||
#define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC)
|
||||
#define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8)
|
||||
#define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00D8)
|
||||
#define INFRA_SW_CG5 MT_LP_TZ_INFRA_REG(0x00E8)
|
||||
#define MMSYS_CG_CON0 MT_LP_TZ_MM_REG(0x100)
|
||||
#define MMSYS_CG_CON1 MT_LP_TZ_MM_REG(0x110)
|
||||
#define MMSYS_CG_CON2 MT_LP_TZ_MM_REG(0x1A0)
|
||||
|
||||
/***********************************************************
|
||||
* Check clkmux registers
|
||||
***********************************************************/
|
||||
#define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x20 + id * 0x10)
|
||||
#define PDN_CHECK BIT(7)
|
||||
#define CLK_CHECK BIT(31)
|
||||
|
||||
enum {
|
||||
CLKMUX_DISP = 0,
|
||||
CLKMUX_MDP = 1,
|
||||
CLKMUX_IMG1 = 2,
|
||||
CLKMUX_IMG2 = 3,
|
||||
NF_CLKMUX,
|
||||
};
|
||||
|
||||
static bool is_clkmux_pdn(unsigned int clkmux_id)
|
||||
{
|
||||
unsigned int reg, val, idx;
|
||||
|
||||
if ((clkmux_id & CLK_CHECK) != 0U) {
|
||||
clkmux_id = (clkmux_id & ~CLK_CHECK);
|
||||
reg = clkmux_id / 4U;
|
||||
val = mmio_read_32(CLK_CFG(reg));
|
||||
idx = clkmux_id % 4U;
|
||||
val = (val >> (idx * 8U)) & PDN_CHECK;
|
||||
return (val != 0U);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static struct mt_spm_cond_tables spm_cond_t;
|
||||
|
||||
struct idle_cond_info {
|
||||
unsigned int subsys_mask;
|
||||
uintptr_t addr;
|
||||
bool bBitflip;
|
||||
unsigned int clkmux_id;
|
||||
};
|
||||
|
||||
#define IDLE_CG(mask, addr, bitflip, clkmux) \
|
||||
{mask, (uintptr_t)addr, bitflip, clkmux}
|
||||
|
||||
static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
|
||||
IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
|
||||
IDLE_CG(0x00000200, INFRA_SW_CG0, true, 0U),
|
||||
IDLE_CG(0x00000200, INFRA_SW_CG1, true, 0U),
|
||||
IDLE_CG(0x00000200, INFRA_SW_CG2, true, 0U),
|
||||
IDLE_CG(0x00000200, INFRA_SW_CG3, true, 0U),
|
||||
IDLE_CG(0x00000200, INFRA_SW_CG4, true, 0U),
|
||||
IDLE_CG(0x00000200, INFRA_SW_CG5, true, 0U),
|
||||
IDLE_CG(0x00100000, MMSYS_CG_CON0, true, (CLK_CHECK | CLKMUX_DISP)),
|
||||
IDLE_CG(0x00100000, MMSYS_CG_CON1, true, (CLK_CHECK | CLKMUX_DISP)),
|
||||
IDLE_CG(0x00100000, MMSYS_CG_CON2, true, (CLK_CHECK | CLKMUX_DISP)),
|
||||
};
|
||||
|
||||
/***********************************************************
|
||||
* Check pll idle condition
|
||||
***********************************************************/
|
||||
#define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x268)
|
||||
#define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x360)
|
||||
#define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x308)
|
||||
#define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x350)
|
||||
#define PLL_TVDPLL MT_LP_TZ_APMIXEDSYS(0x380)
|
||||
|
||||
unsigned int mt_spm_cond_check(int state_id,
|
||||
const struct mt_spm_cond_tables *src,
|
||||
const struct mt_spm_cond_tables *dest,
|
||||
struct mt_spm_cond_tables *res)
|
||||
{
|
||||
unsigned int blocked = 0U, i;
|
||||
bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
|
||||
|
||||
if ((src == NULL) || (dest == NULL)) {
|
||||
return SPM_COND_CHECK_FAIL;
|
||||
}
|
||||
|
||||
for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
|
||||
if (res != NULL) {
|
||||
res->table_cg[i] =
|
||||
(src->table_cg[i] & dest->table_cg[i]);
|
||||
|
||||
if (is_system_suspend && (res->table_cg[i] != 0U)) {
|
||||
INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
|
||||
dest->name, i, idle_cg_info[i].addr,
|
||||
res->table_cg[i]);
|
||||
}
|
||||
|
||||
if (res->table_cg[i] != 0U) {
|
||||
blocked |= (1U << i);
|
||||
}
|
||||
} else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
|
||||
blocked |= (1U << i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (res != NULL) {
|
||||
res->table_pll = (src->table_pll & dest->table_pll);
|
||||
|
||||
if (res->table_pll != 0U) {
|
||||
blocked |=
|
||||
(res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
|
||||
SPM_COND_CHECK_BLOCKED_PLL;
|
||||
}
|
||||
} else if ((src->table_pll & dest->table_pll) != 0U) {
|
||||
blocked |= SPM_COND_CHECK_BLOCKED_PLL;
|
||||
}
|
||||
|
||||
return blocked;
|
||||
}
|
||||
|
||||
#define IS_MT_SPM_PWR_OFF(mask) \
|
||||
(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
|
||||
((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
|
||||
|
||||
int mt_spm_cond_update(struct mt_resource_constraint **con,
|
||||
int stateid, void *priv)
|
||||
{
|
||||
int res;
|
||||
uint32_t i;
|
||||
struct mt_resource_constraint *const *rc;
|
||||
|
||||
/* read all cg state */
|
||||
for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
|
||||
spm_cond_t.table_cg[i] = 0U;
|
||||
|
||||
/* check mtcmos, if off set idle_value and clk to 0 disable */
|
||||
if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* check clkmux */
|
||||
if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
|
||||
~mmio_read_32(idle_cg_info[i].addr) :
|
||||
mmio_read_32(idle_cg_info[i].addr);
|
||||
}
|
||||
|
||||
spm_cond_t.table_pll = 0U;
|
||||
if ((mmio_read_32(PLL_MFGPLL) & 0x1) != 0U) {
|
||||
spm_cond_t.table_pll |= PLL_BIT_MFGPLL;
|
||||
}
|
||||
|
||||
if ((mmio_read_32(PLL_MMPLL) & 0x1) != 0U) {
|
||||
spm_cond_t.table_pll |= PLL_BIT_MMPLL;
|
||||
}
|
||||
|
||||
if ((mmio_read_32(PLL_UNIVPLL) & 0x1) != 0U) {
|
||||
spm_cond_t.table_pll |= PLL_BIT_UNIVPLL;
|
||||
}
|
||||
|
||||
if ((mmio_read_32(PLL_MSDCPLL) & 0x1) != 0U) {
|
||||
spm_cond_t.table_pll |= PLL_BIT_MSDCPLL;
|
||||
}
|
||||
|
||||
if ((mmio_read_32(PLL_TVDPLL) & 0x1) != 0U) {
|
||||
spm_cond_t.table_pll |= PLL_BIT_TVDPLL;
|
||||
}
|
||||
|
||||
spm_cond_t.priv = priv;
|
||||
for (rc = con; *rc != NULL; rc++) {
|
||||
if (((*rc)->update) == NULL) {
|
||||
continue;
|
||||
}
|
||||
|
||||
res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION,
|
||||
(void const *)&spm_cond_t);
|
||||
if (res != MT_RM_STATUS_OK) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_CONDIT_H
|
||||
#define MT_SPM_CONDIT_H
|
||||
|
||||
#include <mt_lp_rm.h>
|
||||
|
||||
enum PLAT_SPM_COND {
|
||||
PLAT_SPM_COND_MTCMOS1 = 0,
|
||||
PLAT_SPM_COND_CG_INFRA_0,
|
||||
PLAT_SPM_COND_CG_INFRA_1,
|
||||
PLAT_SPM_COND_CG_INFRA_2,
|
||||
PLAT_SPM_COND_CG_INFRA_3,
|
||||
PLAT_SPM_COND_CG_INFRA_4,
|
||||
PLAT_SPM_COND_CG_INFRA_5,
|
||||
PLAT_SPM_COND_CG_MMSYS_0,
|
||||
PLAT_SPM_COND_CG_MMSYS_1,
|
||||
PLAT_SPM_COND_CG_MMSYS_2,
|
||||
PLAT_SPM_COND_MAX,
|
||||
};
|
||||
|
||||
enum PLAT_SPM_COND_PLL {
|
||||
PLAT_SPM_COND_PLL_UNIVPLL = 0,
|
||||
PLAT_SPM_COND_PLL_MFGPLL,
|
||||
PLAT_SPM_COND_PLL_MSDCPLL,
|
||||
PLAT_SPM_COND_PLL_TVDPLL,
|
||||
PLAT_SPM_COND_PLL_MMPLL,
|
||||
PLAT_SPM_COND_PLL_MAX,
|
||||
};
|
||||
|
||||
#define PLL_BIT_MFGPLL (PLAT_SPM_COND_PLL_MFGPLL)
|
||||
#define PLL_BIT_MMPLL (PLAT_SPM_COND_PLL_MMPLL)
|
||||
#define PLL_BIT_UNIVPLL (PLAT_SPM_COND_PLL_UNIVPLL)
|
||||
#define PLL_BIT_MSDCPLL (PLAT_SPM_COND_PLL_MSDCPLL)
|
||||
#define PLL_BIT_TVDPLL (PLAT_SPM_COND_PLL_TVDPLL)
|
||||
|
||||
/* Definition about SPM_COND_CHECK_BLOCKED
|
||||
* bit [00 ~ 15]: cg blocking index
|
||||
* bit [16 ~ 29]: pll blocking index
|
||||
* bit [30] : pll blocking information
|
||||
* bit [31] : idle condition check fail
|
||||
*/
|
||||
#define SPM_COND_BLOCKED_CG_IDX U(0)
|
||||
#define SPM_COND_BLOCKED_PLL_IDX U(16)
|
||||
#define SPM_COND_CHECK_BLOCKED_PLL BIT(30)
|
||||
#define SPM_COND_CHECK_FAIL BIT(31)
|
||||
|
||||
struct mt_spm_cond_tables {
|
||||
char *name;
|
||||
unsigned int table_cg[PLAT_SPM_COND_MAX];
|
||||
unsigned int table_pll;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
extern unsigned int mt_spm_cond_check(int state_id,
|
||||
const struct mt_spm_cond_tables *src,
|
||||
const struct mt_spm_cond_tables *dest,
|
||||
struct mt_spm_cond_tables *res);
|
||||
extern int mt_spm_cond_update(struct mt_resource_constraint **con,
|
||||
int stateid, void *priv);
|
||||
#endif /* MT_SPM_CONDIT_H */
|
|
@ -0,0 +1,155 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_conservation.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_vcorefs.h>
|
||||
#include <plat_mtk_lpm.h>
|
||||
#include <plat_pm.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
struct wake_status spm_wakesta; /* record last wakesta */
|
||||
|
||||
static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
|
||||
struct spm_lp_scen *spm_lp,
|
||||
unsigned int resource_req)
|
||||
{
|
||||
int ret = 0;
|
||||
struct pwr_ctrl *pwrctrl;
|
||||
uint32_t cpu = plat_my_core_pos();
|
||||
|
||||
pwrctrl = spm_lp->pwrctrl;
|
||||
|
||||
__spm_set_cpu_status(cpu);
|
||||
__spm_set_power_control(pwrctrl);
|
||||
__spm_set_wakeup_event(pwrctrl);
|
||||
__spm_sync_vcore_dvfs_power_control(pwrctrl, __spm_vcorefs.pwrctrl);
|
||||
__spm_set_pcm_flags(pwrctrl);
|
||||
__spm_src_req_update(pwrctrl, resource_req);
|
||||
|
||||
if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
|
||||
__spm_set_pcm_wdt(1);
|
||||
}
|
||||
|
||||
if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
|
||||
__spm_xo_soc_bblpm(1);
|
||||
}
|
||||
|
||||
if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
|
||||
spm_hw_s1_state_monitor_resume();
|
||||
}
|
||||
|
||||
/* Disable auto resume by PCM in system suspend stage */
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
__spm_disable_pcm_timer();
|
||||
__spm_set_pcm_wdt(0);
|
||||
}
|
||||
|
||||
__spm_send_cpu_wakeup_event();
|
||||
|
||||
INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n",
|
||||
cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE),
|
||||
mmio_read_32(PCM_TIMER_VAL) / 32768);
|
||||
INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n",
|
||||
pwrctrl->pcm_flags, pwrctrl->pcm_flags1,
|
||||
mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS),
|
||||
mmio_read_32(PWR_STATUS_2ND));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
|
||||
struct spm_lp_scen *spm_lp,
|
||||
struct wake_status **status)
|
||||
{
|
||||
unsigned int ext_status = 0U;
|
||||
|
||||
/* system watchdog will be resumed at kernel stage */
|
||||
if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
|
||||
__spm_set_pcm_wdt(0);
|
||||
}
|
||||
|
||||
if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
|
||||
__spm_xo_soc_bblpm(0);
|
||||
}
|
||||
|
||||
if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
|
||||
spm_hw_s1_state_monitor_pause(&ext_status);
|
||||
}
|
||||
|
||||
__spm_ext_int_wakeup_req_clr();
|
||||
__spm_get_wakeup_status(&spm_wakesta, ext_status);
|
||||
|
||||
if (status != NULL) {
|
||||
*status = &spm_wakesta;
|
||||
}
|
||||
|
||||
__spm_clean_after_wakeup();
|
||||
|
||||
if (IS_PLAT_SUSPEND_ID(state_id)) {
|
||||
__spm_output_wake_reason(state_id, &spm_wakesta);
|
||||
}
|
||||
}
|
||||
|
||||
int spm_conservation(int state_id, unsigned int ext_opand,
|
||||
struct spm_lp_scen *spm_lp, unsigned int resource_req)
|
||||
{
|
||||
if (spm_lp == NULL) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
spm_lock_get();
|
||||
go_to_spm_before_wfi(state_id, ext_opand, spm_lp, resource_req);
|
||||
spm_lock_release();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spm_conservation_finish(int state_id, unsigned int ext_opand,
|
||||
struct spm_lp_scen *spm_lp,
|
||||
struct wake_status **status)
|
||||
{
|
||||
spm_lock_get();
|
||||
go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
|
||||
spm_lock_release();
|
||||
}
|
||||
|
||||
int spm_conservation_get_result(struct wake_status **res)
|
||||
{
|
||||
if (res == NULL) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
*res = &spm_wakesta;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define GPIO_BANK (GPIO_BASE + 0x6F0)
|
||||
#define TRAP_UFS_FIRST BIT(11) /* bit 11, 0: UFS, 1: eMMC */
|
||||
|
||||
void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
if (pwrctrl == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* For ufs, emmc storage type */
|
||||
if ((mmio_read_32(GPIO_BANK) & TRAP_UFS_FIRST) != 0U) {
|
||||
/* If eMMC is used, mask UFS req */
|
||||
pwrctrl->reg_ufs_srcclkena_mask_b = 0;
|
||||
pwrctrl->reg_ufs_infra_req_mask_b = 0;
|
||||
pwrctrl->reg_ufs_apsrc_req_mask_b = 0;
|
||||
pwrctrl->reg_ufs_vrf18_req_mask_b = 0;
|
||||
pwrctrl->reg_ufs_ddr_en_mask_b = 0;
|
||||
}
|
||||
}
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_CONSERVATION_H
|
||||
#define MT_SPM_CONSERVATION_H
|
||||
|
||||
#include <mt_spm_internal.h>
|
||||
|
||||
extern int spm_conservation(int state_id, unsigned int ext_opand,
|
||||
struct spm_lp_scen *spm_lp,
|
||||
unsigned int resource_req);
|
||||
extern void spm_conservation_finish(int state_id, unsigned int ext_opand,
|
||||
struct spm_lp_scen *spm_lp,
|
||||
struct wake_status **status);
|
||||
extern int spm_conservation_get_result(struct wake_status **res);
|
||||
extern void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl);
|
||||
#endif /* MT_SPM_CONSERVATION_H */
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_CONSTRAINT_H
|
||||
#define MT_SPM_CONSTRAINT_H
|
||||
|
||||
#include <mt_lp_rm.h>
|
||||
|
||||
#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF (1U << 0)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 (1U << 1)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 (1U << 2)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP (1U << 3)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN (1U << 4)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF (1U << 5)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND (1U << 6)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_BBLPM (1U << 7)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_XO_UFS (1U << 8)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE (1U << 9)
|
||||
#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE (1U << 10)
|
||||
|
||||
#define MT_SPM_RC_INVALID 0x0
|
||||
#define MT_SPM_RC_VALID_SW (1U << 0)
|
||||
#define MT_SPM_RC_VALID_FW (1U << 1)
|
||||
#define MT_SPM_RC_VALID_RESIDNECY (1U << 2)
|
||||
#define MT_SPM_RC_VALID_COND_CHECK (1U << 3)
|
||||
#define MT_SPM_RC_VALID_COND_LATCH (1U << 4)
|
||||
#define MT_SPM_RC_VALID_UFS_H8 (1U << 5)
|
||||
#define MT_SPM_RC_VALID_FLIGHTMODE (1U << 6)
|
||||
#define MT_SPM_RC_VALID_XSOC_BBLPM (1U << 7)
|
||||
#define MT_SPM_RC_VALID_TRACE_EVENT (1U << 8)
|
||||
|
||||
#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW)
|
||||
|
||||
#define IS_MT_RM_RC_READY(status) \
|
||||
((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
|
||||
|
||||
#define MT_SPM_RC_BBLPM_MODE \
|
||||
(MT_SPM_RC_VALID_UFS_H8 | \
|
||||
MT_SPM_RC_VALID_FLIGHTMODE | \
|
||||
MT_SPM_RC_VALID_XSOC_BBLPM)
|
||||
|
||||
#define IS_MT_SPM_RC_BBLPM_MODE(st) \
|
||||
((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
|
||||
|
||||
struct constraint_status {
|
||||
uint16_t id;
|
||||
uint16_t valid;
|
||||
uint32_t cond_block;
|
||||
uint32_t enter_cnt;
|
||||
struct mt_spm_cond_tables *cond_res;
|
||||
};
|
||||
|
||||
enum MT_SPM_RM_RC_TYPE {
|
||||
MT_RM_CONSTRAINT_ID_BUS26M,
|
||||
MT_RM_CONSTRAINT_ID_SYSPLL,
|
||||
MT_RM_CONSTRAINT_ID_DRAM,
|
||||
MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
|
||||
MT_RM_CONSTRAINT_ID_ALL,
|
||||
};
|
||||
#endif /* MT_SPM_CONSTRAINT_H */
|
|
@ -0,0 +1,249 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_conservation.h>
|
||||
#include <mt_spm_idle.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_resource_req.h>
|
||||
#include <plat_pm.h>
|
||||
|
||||
#define __WAKE_SRC_FOR_IDLE_COMMON__ \
|
||||
(R12_PCM_TIMER | \
|
||||
R12_KP_IRQ_B | \
|
||||
R12_APWDT_EVENT_B | \
|
||||
R12_APXGPT1_EVENT_B | \
|
||||
R12_CONN2AP_SPM_WAKEUP_B | \
|
||||
R12_EINT_EVENT_B | \
|
||||
R12_CONN_WDT_IRQ_B | \
|
||||
R12_CCIF0_EVENT_B | \
|
||||
R12_SSPM2SPM_WAKEUP_B | \
|
||||
R12_SCP2SPM_WAKEUP_B | \
|
||||
R12_ADSP2SPM_WAKEUP_B | \
|
||||
R12_USBX_CDSC_B | \
|
||||
R12_USBX_POWERDWN_B | \
|
||||
R12_SYS_TIMER_EVENT_B | \
|
||||
R12_EINT_EVENT_SECURE_B | \
|
||||
R12_CCIF1_EVENT_B | \
|
||||
R12_AFE_IRQ_MCU_B | \
|
||||
R12_SYS_CIRQ_IRQ_B | \
|
||||
R12_MD2AP_PEER_EVENT_B | \
|
||||
R12_MD1_WDT_B | \
|
||||
R12_CLDMA_EVENT_B | \
|
||||
R12_REG_CPU_WAKEUP | \
|
||||
R12_APUSYS_WAKE_HOST_B | \
|
||||
R12_PCIE_BRIDGE_IRQ | \
|
||||
R12_PCIE_IRQ)
|
||||
|
||||
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
|
||||
#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
|
||||
#else
|
||||
#define WAKE_SRC_FOR_IDLE \
|
||||
(__WAKE_SRC_FOR_IDLE_COMMON__ | \
|
||||
R12_SEJ_EVENT_B)
|
||||
#endif
|
||||
|
||||
static struct pwr_ctrl idle_spm_pwr = {
|
||||
.timer_val = 0x28000,
|
||||
.wake_src = WAKE_SRC_FOR_IDLE,
|
||||
|
||||
/* Auto-gen Start */
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
.reg_wfi_op = 0,
|
||||
.reg_wfi_type = 0,
|
||||
.reg_mp0_cputop_idle_mask = 0,
|
||||
.reg_mp1_cputop_idle_mask = 0,
|
||||
.reg_mcusys_idle_mask = 0,
|
||||
.reg_md_apsrc_1_sel = 0,
|
||||
.reg_md_apsrc_0_sel = 0,
|
||||
.reg_conn_apsrc_sel = 0,
|
||||
|
||||
/* SPM_SRC6_MASK */
|
||||
.reg_dpmaif_srcclkena_mask_b = 1,
|
||||
.reg_dpmaif_infra_req_mask_b = 1,
|
||||
.reg_dpmaif_apsrc_req_mask_b = 1,
|
||||
.reg_dpmaif_vrf18_req_mask_b = 1,
|
||||
.reg_dpmaif_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC_REQ */
|
||||
.reg_spm_apsrc_req = 1,
|
||||
.reg_spm_f26m_req = 1,
|
||||
.reg_spm_infra_req = 1,
|
||||
.reg_spm_vrf18_req = 1,
|
||||
.reg_spm_ddr_en_req = 1,
|
||||
.reg_spm_dvfs_req = 0,
|
||||
.reg_spm_sw_mailbox_req = 0,
|
||||
.reg_spm_sspm_mailbox_req = 0,
|
||||
.reg_spm_adsp_mailbox_req = 0,
|
||||
.reg_spm_scp_mailbox_req = 0,
|
||||
|
||||
/* SPM_SRC_MASK */
|
||||
.reg_md_srcclkena_0_mask_b = 1,
|
||||
.reg_md_srcclkena2infra_req_0_mask_b = 0,
|
||||
.reg_md_apsrc2infra_req_0_mask_b = 1,
|
||||
.reg_md_apsrc_req_0_mask_b = 1,
|
||||
.reg_md_vrf18_req_0_mask_b = 1,
|
||||
.reg_md_ddr_en_0_mask_b = 1,
|
||||
.reg_md_srcclkena_1_mask_b = 0,
|
||||
.reg_md_srcclkena2infra_req_1_mask_b = 0,
|
||||
.reg_md_apsrc2infra_req_1_mask_b = 0,
|
||||
.reg_md_apsrc_req_1_mask_b = 0,
|
||||
.reg_md_vrf18_req_1_mask_b = 0,
|
||||
.reg_md_ddr_en_1_mask_b = 0,
|
||||
.reg_conn_srcclkena_mask_b = 1,
|
||||
.reg_conn_srcclkenb_mask_b = 0,
|
||||
.reg_conn_infra_req_mask_b = 1,
|
||||
.reg_conn_apsrc_req_mask_b = 1,
|
||||
.reg_conn_vrf18_req_mask_b = 1,
|
||||
.reg_conn_ddr_en_mask_b = 1,
|
||||
.reg_conn_vfe28_mask_b = 0,
|
||||
.reg_srcclkeni0_srcclkena_mask_b = 1,
|
||||
.reg_srcclkeni0_infra_req_mask_b = 1,
|
||||
.reg_srcclkeni1_srcclkena_mask_b = 0,
|
||||
.reg_srcclkeni1_infra_req_mask_b = 0,
|
||||
.reg_srcclkeni2_srcclkena_mask_b = 0,
|
||||
.reg_srcclkeni2_infra_req_mask_b = 0,
|
||||
.reg_infrasys_apsrc_req_mask_b = 0,
|
||||
.reg_infrasys_ddr_en_mask_b = 1,
|
||||
.reg_md32_srcclkena_mask_b = 1,
|
||||
.reg_md32_infra_req_mask_b = 1,
|
||||
.reg_md32_apsrc_req_mask_b = 1,
|
||||
.reg_md32_vrf18_req_mask_b = 1,
|
||||
.reg_md32_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC2_MASK */
|
||||
.reg_scp_srcclkena_mask_b = 1,
|
||||
.reg_scp_infra_req_mask_b = 1,
|
||||
.reg_scp_apsrc_req_mask_b = 1,
|
||||
.reg_scp_vrf18_req_mask_b = 1,
|
||||
.reg_scp_ddr_en_mask_b = 1,
|
||||
.reg_audio_dsp_srcclkena_mask_b = 1,
|
||||
.reg_audio_dsp_infra_req_mask_b = 1,
|
||||
.reg_audio_dsp_apsrc_req_mask_b = 1,
|
||||
.reg_audio_dsp_vrf18_req_mask_b = 1,
|
||||
.reg_audio_dsp_ddr_en_mask_b = 1,
|
||||
.reg_ufs_srcclkena_mask_b = 1,
|
||||
.reg_ufs_infra_req_mask_b = 1,
|
||||
.reg_ufs_apsrc_req_mask_b = 1,
|
||||
.reg_ufs_vrf18_req_mask_b = 1,
|
||||
.reg_ufs_ddr_en_mask_b = 1,
|
||||
.reg_disp0_apsrc_req_mask_b = 1,
|
||||
.reg_disp0_ddr_en_mask_b = 1,
|
||||
.reg_disp1_apsrc_req_mask_b = 1,
|
||||
.reg_disp1_ddr_en_mask_b = 1,
|
||||
.reg_gce_infra_req_mask_b = 1,
|
||||
.reg_gce_apsrc_req_mask_b = 1,
|
||||
.reg_gce_vrf18_req_mask_b = 1,
|
||||
.reg_gce_ddr_en_mask_b = 1,
|
||||
.reg_apu_srcclkena_mask_b = 1,
|
||||
.reg_apu_infra_req_mask_b = 1,
|
||||
.reg_apu_apsrc_req_mask_b = 1,
|
||||
.reg_apu_vrf18_req_mask_b = 1,
|
||||
.reg_apu_ddr_en_mask_b = 1,
|
||||
.reg_cg_check_srcclkena_mask_b = 0,
|
||||
.reg_cg_check_apsrc_req_mask_b = 0,
|
||||
.reg_cg_check_vrf18_req_mask_b = 0,
|
||||
.reg_cg_check_ddr_en_mask_b = 0,
|
||||
|
||||
/* SPM_SRC3_MASK */
|
||||
.reg_dvfsrc_event_trigger_mask_b = 1,
|
||||
.reg_sw2spm_int0_mask_b = 0,
|
||||
.reg_sw2spm_int1_mask_b = 0,
|
||||
.reg_sw2spm_int2_mask_b = 0,
|
||||
.reg_sw2spm_int3_mask_b = 0,
|
||||
.reg_sc_adsp2spm_wakeup_mask_b = 0,
|
||||
.reg_sc_sspm2spm_wakeup_mask_b = 0,
|
||||
.reg_sc_scp2spm_wakeup_mask_b = 0,
|
||||
.reg_csyspwrreq_mask = 1,
|
||||
.reg_spm_srcclkena_reserved_mask_b = 0,
|
||||
.reg_spm_infra_req_reserved_mask_b = 0,
|
||||
.reg_spm_apsrc_req_reserved_mask_b = 0,
|
||||
.reg_spm_vrf18_req_reserved_mask_b = 0,
|
||||
.reg_spm_ddr_en_reserved_mask_b = 0,
|
||||
.reg_mcupm_srcclkena_mask_b = 1,
|
||||
.reg_mcupm_infra_req_mask_b = 1,
|
||||
.reg_mcupm_apsrc_req_mask_b = 1,
|
||||
.reg_mcupm_vrf18_req_mask_b = 1,
|
||||
.reg_mcupm_ddr_en_mask_b = 1,
|
||||
.reg_msdc0_srcclkena_mask_b = 1,
|
||||
.reg_msdc0_infra_req_mask_b = 1,
|
||||
.reg_msdc0_apsrc_req_mask_b = 1,
|
||||
.reg_msdc0_vrf18_req_mask_b = 1,
|
||||
.reg_msdc0_ddr_en_mask_b = 1,
|
||||
.reg_msdc1_srcclkena_mask_b = 1,
|
||||
.reg_msdc1_infra_req_mask_b = 1,
|
||||
.reg_msdc1_apsrc_req_mask_b = 1,
|
||||
.reg_msdc1_vrf18_req_mask_b = 1,
|
||||
.reg_msdc1_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC4_MASK */
|
||||
.ccif_event_mask_b = 0xFFF,
|
||||
.reg_bak_psri_srcclkena_mask_b = 0,
|
||||
.reg_bak_psri_infra_req_mask_b = 0,
|
||||
.reg_bak_psri_apsrc_req_mask_b = 0,
|
||||
.reg_bak_psri_vrf18_req_mask_b = 0,
|
||||
.reg_bak_psri_ddr_en_mask_b = 0,
|
||||
.reg_dramc0_md32_infra_req_mask_b = 1,
|
||||
.reg_dramc0_md32_vrf18_req_mask_b = 0,
|
||||
.reg_dramc1_md32_infra_req_mask_b = 1,
|
||||
.reg_dramc1_md32_vrf18_req_mask_b = 0,
|
||||
.reg_conn_srcclkenb2pwrap_mask_b = 0,
|
||||
.reg_dramc0_md32_wakeup_mask = 1,
|
||||
.reg_dramc1_md32_wakeup_mask = 1,
|
||||
|
||||
/* SPM_SRC5_MASK */
|
||||
.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
|
||||
.reg_mcusys_merge_ddr_en_mask_b = 0x11,
|
||||
.reg_msdc2_srcclkena_mask_b = 1,
|
||||
.reg_msdc2_infra_req_mask_b = 1,
|
||||
.reg_msdc2_apsrc_req_mask_b = 1,
|
||||
.reg_msdc2_vrf18_req_mask_b = 1,
|
||||
.reg_msdc2_ddr_en_mask_b = 1,
|
||||
.reg_pcie_srcclkena_mask_b = 1,
|
||||
.reg_pcie_infra_req_mask_b = 1,
|
||||
.reg_pcie_apsrc_req_mask_b = 1,
|
||||
.reg_pcie_vrf18_req_mask_b = 1,
|
||||
.reg_pcie_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
.reg_wakeup_event_mask = 0x01282202,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
|
||||
|
||||
/* Auto-gen End */
|
||||
};
|
||||
|
||||
struct spm_lp_scen idle_spm_lp = {
|
||||
.pwrctrl = &idle_spm_pwr,
|
||||
};
|
||||
|
||||
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
|
||||
spm_idle_conduct fn)
|
||||
{
|
||||
unsigned int src_req = 0;
|
||||
|
||||
if (fn != NULL) {
|
||||
fn(&idle_spm_lp, &src_req);
|
||||
}
|
||||
|
||||
return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
|
||||
}
|
||||
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
|
||||
struct wake_status **status)
|
||||
{
|
||||
spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
|
||||
}
|
||||
|
||||
void mt_spm_idle_generic_init(void)
|
||||
{
|
||||
spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
|
||||
}
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_IDLE_H
|
||||
#define MT_SPM_IDLE_H
|
||||
|
||||
typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp,
|
||||
unsigned int *resource_req);
|
||||
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
|
||||
spm_idle_conduct fn);
|
||||
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
|
||||
struct wake_status **status);
|
||||
void mt_spm_idle_generic_init(void);
|
||||
#endif /* MT_SPM_IDLE_H */
|
|
@ -0,0 +1,588 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
#include <assert.h>
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_pmic_wrap.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_resource_req.h>
|
||||
#include <platform_def.h>
|
||||
#include <plat_pm.h>
|
||||
|
||||
/**************************************
|
||||
* Define and Declare
|
||||
**************************************/
|
||||
#define ROOT_CORE_ADDR_OFFSET 0x20000000
|
||||
#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff
|
||||
#define SPM_INIT_DONE_US 20
|
||||
|
||||
static unsigned int mt_spm_bblpm_cnt;
|
||||
|
||||
const char *wakeup_src_str[32] = {
|
||||
[0] = "R12_PCM_TIMER",
|
||||
[1] = "R12_RESERVED_DEBUG_B",
|
||||
[2] = "R12_KP_IRQ_B",
|
||||
[3] = "R12_APWDT_EVENT_B",
|
||||
[4] = "R12_APXGPT1_EVENT_B",
|
||||
[5] = "R12_CONN2AP_SPM_WAKEUP_B",
|
||||
[6] = "R12_EINT_EVENT_B",
|
||||
[7] = "R12_CONN_WDT_IRQ_B",
|
||||
[8] = "R12_CCIF0_EVENT_B",
|
||||
[9] = "R12_LOWBATTERY_IRQ_B",
|
||||
[10] = "R12_SC_SSPM2SPM_WAKEUP_B",
|
||||
[11] = "R12_SC_SCP2SPM_WAKEUP_B",
|
||||
[12] = "R12_SC_ADSP2SPM_WAKEUP_B",
|
||||
[13] = "R12_PCM_WDT_WAKEUP_B",
|
||||
[14] = "R12_USB_CDSC_B",
|
||||
[15] = "R12_USB_POWERDWN_B",
|
||||
[16] = "R12_SYS_TIMER_EVENT_B",
|
||||
[17] = "R12_EINT_EVENT_SECURE_B",
|
||||
[18] = "R12_CCIF1_EVENT_B",
|
||||
[19] = "R12_UART0_IRQ_B",
|
||||
[20] = "R12_AFE_IRQ_MCU_B",
|
||||
[21] = "R12_THERM_CTRL_EVENT_B",
|
||||
[22] = "R12_SYS_CIRQ_IRQ_B",
|
||||
[23] = "R12_MD2AP_PEER_EVENT_B",
|
||||
[24] = "R12_CSYSPWREQ_B",
|
||||
[25] = "R12_MD1_WDT_B",
|
||||
[26] = "R12_AP2AP_PEER_WAKEUPEVENT_B",
|
||||
[27] = "R12_SEJ_EVENT_B",
|
||||
[28] = "R12_SPM_CPU_WAKEUPEVENT_B",
|
||||
[29] = "R12_APUSYS",
|
||||
[30] = "R12_PCIE_BRIDGE_IRQ",
|
||||
[31] = "R12_PCIE_IRQ",
|
||||
};
|
||||
|
||||
/**************************************
|
||||
* Function and API
|
||||
**************************************/
|
||||
|
||||
wake_reason_t __spm_output_wake_reason(int state_id,
|
||||
const struct wake_status *wakesta)
|
||||
{
|
||||
uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
|
||||
wake_reason_t wr = WR_UNKNOWN;
|
||||
|
||||
if (wakesta == NULL) {
|
||||
return WR_UNKNOWN;
|
||||
}
|
||||
|
||||
if (wakesta->abort != 0U) {
|
||||
ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
|
||||
wakesta->abort, wakesta->timer_out);
|
||||
} else {
|
||||
for (i = 0U; i < 32U; i++) {
|
||||
if ((wakesta->r12 & (1U << i)) != 0U) {
|
||||
INFO("wake up by %s, timer_out = %u\n",
|
||||
wakeup_src_str[i], wakesta->timer_out);
|
||||
wr = WR_WAKE_SRC;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
|
||||
wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
|
||||
wakesta->debug_flag1);
|
||||
INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
|
||||
wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
|
||||
wakesta->md32pcm_event_sta, wakesta->idle_sta,
|
||||
wakesta->cg_check_sta);
|
||||
INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
|
||||
wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
|
||||
wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
|
||||
INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
|
||||
wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
|
||||
INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
|
||||
wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
|
||||
INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
|
||||
wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
|
||||
wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
|
||||
INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
|
||||
wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
|
||||
mmio_read_32(SYS_TIMER_VALUE_H));
|
||||
|
||||
if (wakesta->timer_out != 0U) {
|
||||
bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
|
||||
spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
|
||||
INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
|
||||
}
|
||||
|
||||
return wr;
|
||||
}
|
||||
|
||||
void __spm_set_cpu_status(unsigned int cpu)
|
||||
{
|
||||
uint32_t root_core_addr;
|
||||
|
||||
if (cpu < 8U) {
|
||||
mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu));
|
||||
root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
|
||||
root_core_addr += ROOT_CORE_ADDR_OFFSET;
|
||||
mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
|
||||
/* Notify MCUPM that preferred cpu wakeup */
|
||||
mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
|
||||
} else {
|
||||
ERROR("%s: error cpu number %d\n", __func__, cpu);
|
||||
}
|
||||
}
|
||||
|
||||
void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
|
||||
unsigned int resource_usage)
|
||||
{
|
||||
uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
|
||||
1 : pwrctrl->reg_spm_apsrc_req;
|
||||
uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
|
||||
1 : pwrctrl->reg_spm_ddr_en_req;
|
||||
uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
|
||||
1 : pwrctrl->reg_spm_vrf18_req;
|
||||
uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
|
||||
1 : pwrctrl->reg_spm_infra_req;
|
||||
uint8_t f26m_req = ((resource_usage &
|
||||
(MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
|
||||
1 : pwrctrl->reg_spm_f26m_req;
|
||||
|
||||
mmio_write_32(SPM_SRC_REQ,
|
||||
((apsrc_req & 0x1) << 0) |
|
||||
((f26m_req & 0x1) << 1) |
|
||||
((infra_req & 0x1) << 3) |
|
||||
((vrf18_req & 0x1) << 4) |
|
||||
((ddr_en_req & 0x1) << 7) |
|
||||
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
|
||||
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
|
||||
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
|
||||
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
|
||||
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
|
||||
}
|
||||
|
||||
void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
/* Auto-gen Start */
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
mmio_write_32(SPM_AP_STANDBY_CON,
|
||||
((pwrctrl->reg_wfi_op & 0x1) << 0) |
|
||||
((pwrctrl->reg_wfi_type & 0x1) << 1) |
|
||||
((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
|
||||
((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
|
||||
((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
|
||||
((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
|
||||
((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
|
||||
((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
|
||||
|
||||
/* SPM_SRC6_MASK */
|
||||
mmio_write_32(SPM_SRC6_MASK,
|
||||
((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) |
|
||||
((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) |
|
||||
((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) |
|
||||
((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) |
|
||||
((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4));
|
||||
|
||||
/* SPM_SRC_REQ */
|
||||
mmio_write_32(SPM_SRC_REQ,
|
||||
((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
|
||||
((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
|
||||
((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
|
||||
((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
|
||||
((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
|
||||
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
|
||||
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
|
||||
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
|
||||
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
|
||||
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
|
||||
|
||||
/* SPM_SRC_MASK */
|
||||
mmio_write_32(SPM_SRC_MASK,
|
||||
((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) |
|
||||
((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) |
|
||||
((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) |
|
||||
((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) |
|
||||
((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) |
|
||||
((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) |
|
||||
((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) |
|
||||
((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) |
|
||||
((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) |
|
||||
((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) |
|
||||
((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) |
|
||||
((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) |
|
||||
((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) |
|
||||
((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) |
|
||||
((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) |
|
||||
((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) |
|
||||
((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) |
|
||||
((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) |
|
||||
((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) |
|
||||
((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) |
|
||||
((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) |
|
||||
((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) |
|
||||
((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) |
|
||||
((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) |
|
||||
((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) |
|
||||
((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
|
||||
((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) |
|
||||
((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) |
|
||||
((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) |
|
||||
((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) |
|
||||
((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) |
|
||||
((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31));
|
||||
|
||||
/* SPM_SRC2_MASK */
|
||||
mmio_write_32(SPM_SRC2_MASK,
|
||||
((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
|
||||
((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
|
||||
((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
|
||||
((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
|
||||
((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) |
|
||||
((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
|
||||
((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
|
||||
((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
|
||||
((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
|
||||
((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) |
|
||||
((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
|
||||
((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
|
||||
((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
|
||||
((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
|
||||
((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) |
|
||||
((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
|
||||
((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) |
|
||||
((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
|
||||
((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) |
|
||||
((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
|
||||
((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
|
||||
((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
|
||||
((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) |
|
||||
((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
|
||||
((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
|
||||
((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
|
||||
((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
|
||||
((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) |
|
||||
((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
|
||||
((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
|
||||
((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
|
||||
((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31));
|
||||
|
||||
/* SPM_SRC3_MASK */
|
||||
mmio_write_32(SPM_SRC3_MASK,
|
||||
((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
|
||||
((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) |
|
||||
((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) |
|
||||
((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) |
|
||||
((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) |
|
||||
((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) |
|
||||
((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) |
|
||||
((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) |
|
||||
((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) |
|
||||
((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) |
|
||||
((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) |
|
||||
((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) |
|
||||
((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) |
|
||||
((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) |
|
||||
((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
|
||||
((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
|
||||
((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
|
||||
((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
|
||||
((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) |
|
||||
((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
|
||||
((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
|
||||
((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
|
||||
((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
|
||||
((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) |
|
||||
((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
|
||||
((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
|
||||
((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
|
||||
((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
|
||||
((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31));
|
||||
|
||||
/* SPM_SRC4_MASK */
|
||||
mmio_write_32(SPM_SRC4_MASK,
|
||||
((pwrctrl->ccif_event_mask_b & 0xffff) << 0) |
|
||||
((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
|
||||
((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
|
||||
((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
|
||||
((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
|
||||
((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) |
|
||||
((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) |
|
||||
((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) |
|
||||
((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) |
|
||||
((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) |
|
||||
((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
|
||||
((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) |
|
||||
((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27));
|
||||
|
||||
/* SPM_SRC5_MASK */
|
||||
mmio_write_32(SPM_SRC5_MASK,
|
||||
((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
|
||||
((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
|
||||
((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) |
|
||||
((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) |
|
||||
((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) |
|
||||
((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) |
|
||||
((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) |
|
||||
((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) |
|
||||
((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) |
|
||||
((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) |
|
||||
((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) |
|
||||
((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27));
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
mmio_write_32(SPM_WAKEUP_EVENT_MASK,
|
||||
((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
|
||||
((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
|
||||
|
||||
/* Auto-gen End */
|
||||
}
|
||||
|
||||
void __spm_disable_pcm_timer(void)
|
||||
{
|
||||
mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
|
||||
}
|
||||
|
||||
void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
uint32_t val, mask;
|
||||
|
||||
/* toggle event counter clear */
|
||||
mmio_setbits_32(PCM_CON1,
|
||||
SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
|
||||
|
||||
/* toggle for reset SYS TIMER start point */
|
||||
mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
|
||||
|
||||
if (pwrctrl->timer_val_cust == 0U) {
|
||||
val = pwrctrl->timer_val;
|
||||
} else {
|
||||
val = pwrctrl->timer_val_cust;
|
||||
}
|
||||
|
||||
mmio_write_32(PCM_TIMER_VAL, val);
|
||||
mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
|
||||
|
||||
/* unmask AP wakeup source */
|
||||
if (pwrctrl->wake_src_cust == 0U) {
|
||||
mask = pwrctrl->wake_src;
|
||||
} else {
|
||||
mask = pwrctrl->wake_src_cust;
|
||||
}
|
||||
|
||||
if (pwrctrl->reg_csyspwrreq_mask != 0U) {
|
||||
mask &= ~R12_CSYSPWREQ_B;
|
||||
}
|
||||
|
||||
mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
|
||||
|
||||
/* unmask SPM ISR (keep TWAM setting) */
|
||||
mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
|
||||
|
||||
/* toggle event counter clear */
|
||||
mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB,
|
||||
SPM_REGWR_CFG_KEY);
|
||||
/* toggle for reset SYS TIMER start point */
|
||||
mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
|
||||
}
|
||||
|
||||
void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
/* set PCM flags and data */
|
||||
if (pwrctrl->pcm_flags_cust_clr != 0U) {
|
||||
pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
|
||||
}
|
||||
|
||||
if (pwrctrl->pcm_flags_cust_set != 0U) {
|
||||
pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
|
||||
}
|
||||
|
||||
if (pwrctrl->pcm_flags1_cust_clr != 0U) {
|
||||
pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
|
||||
}
|
||||
|
||||
if (pwrctrl->pcm_flags1_cust_set != 0U) {
|
||||
pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
|
||||
}
|
||||
|
||||
mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
|
||||
mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
|
||||
mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
|
||||
mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
|
||||
}
|
||||
|
||||
void __spm_get_wakeup_status(struct wake_status *wakesta,
|
||||
unsigned int ext_status)
|
||||
{
|
||||
wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
|
||||
wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
|
||||
wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
|
||||
wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
|
||||
wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
|
||||
wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
|
||||
wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
|
||||
wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
|
||||
wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
|
||||
wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
|
||||
|
||||
if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
|
||||
wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
|
||||
SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
|
||||
mmio_write_32(PCM_WDT_LATCH_SPARE_0,
|
||||
wakesta->tr.comm.debug_flag);
|
||||
}
|
||||
|
||||
wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
|
||||
wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
|
||||
|
||||
/* record below spm info for debug */
|
||||
wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
|
||||
wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
|
||||
wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
|
||||
wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
|
||||
wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
|
||||
wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
|
||||
wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
|
||||
|
||||
/* backup of SPM_WAKEUP_MISC */
|
||||
wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
|
||||
|
||||
/* get sleep time, backup of PCM_TIMER_OUT */
|
||||
wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
|
||||
|
||||
/* get other SYS and co-clock status */
|
||||
wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
|
||||
wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
|
||||
wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
|
||||
wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
|
||||
wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
|
||||
wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
|
||||
wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
|
||||
|
||||
/* get HW CG check status */
|
||||
wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
|
||||
|
||||
/* get debug flag for PCM execution check */
|
||||
wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
|
||||
wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
|
||||
|
||||
/* get backup SW flag status */
|
||||
wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
|
||||
wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
|
||||
|
||||
wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
|
||||
wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
|
||||
wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
|
||||
wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
|
||||
wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
|
||||
|
||||
/* get ISR status */
|
||||
wakesta->isr = mmio_read_32(SPM_IRQ_STA);
|
||||
|
||||
/* get SW flag status */
|
||||
wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
|
||||
wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
|
||||
|
||||
/* get CLK SETTLE */
|
||||
wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
|
||||
|
||||
/* check abort */
|
||||
wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) |
|
||||
(wakesta->debug_flag1 & DEBUG_ABORT_MASK_1);
|
||||
}
|
||||
|
||||
void __spm_clean_after_wakeup(void)
|
||||
{
|
||||
mmio_write_32(SPM_BK_WAKE_EVENT,
|
||||
mmio_read_32(SPM_WAKEUP_STA) |
|
||||
mmio_read_32(SPM_BK_WAKE_EVENT));
|
||||
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
|
||||
|
||||
/*
|
||||
* clean wakeup event raw status (for edge trigger event)
|
||||
* bit[28] for cpu wake up event
|
||||
*/
|
||||
mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
|
||||
|
||||
/* clean ISR status (except TWAM) */
|
||||
mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
|
||||
mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
|
||||
mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
|
||||
}
|
||||
|
||||
void __spm_set_pcm_wdt(int en)
|
||||
{
|
||||
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
|
||||
SPM_REGWR_CFG_KEY);
|
||||
|
||||
if (en == 1) {
|
||||
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
|
||||
SPM_REGWR_CFG_KEY);
|
||||
|
||||
if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
|
||||
mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
|
||||
}
|
||||
|
||||
mmio_write_32(PCM_WDT_VAL,
|
||||
mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
|
||||
mmio_setbits_32(PCM_CON1,
|
||||
SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
|
||||
}
|
||||
}
|
||||
|
||||
void __spm_send_cpu_wakeup_event(void)
|
||||
{
|
||||
/* SPM will clear SPM_CPU_WAKEUP_EVENT */
|
||||
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
|
||||
}
|
||||
|
||||
void __spm_ext_int_wakeup_req_clr(void)
|
||||
{
|
||||
mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
|
||||
|
||||
/* Clear spm2mcupm wakeup interrupt status */
|
||||
mmio_write_32(SPM2MCUPM_CON, 0);
|
||||
}
|
||||
|
||||
void __spm_xo_soc_bblpm(int en)
|
||||
{
|
||||
if (en == 1) {
|
||||
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
|
||||
RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC);
|
||||
assert(mt_spm_bblpm_cnt == 0);
|
||||
mt_spm_bblpm_cnt += 1;
|
||||
} else {
|
||||
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
|
||||
RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM);
|
||||
mt_spm_bblpm_cnt -= 1;
|
||||
}
|
||||
}
|
||||
|
||||
void __spm_hw_s1_state_monitor(int en, unsigned int *status)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = mmio_read_32(SPM_ACK_CHK_CON_3);
|
||||
|
||||
if (en == 1) {
|
||||
reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
|
||||
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
|
||||
reg |= SPM_ACK_CHK_3_CON_EN;
|
||||
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
|
||||
} else {
|
||||
if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
|
||||
(status != NULL)) {
|
||||
*status |= SPM_INTERNAL_STATUS_HW_S1;
|
||||
}
|
||||
|
||||
mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
|
||||
SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
|
||||
SPM_ACK_CHK_3_CON_CLR_ALL);
|
||||
}
|
||||
}
|
|
@ -0,0 +1,637 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_INTERNAL_H
|
||||
#define MT_SPM_INTERNAL_H
|
||||
|
||||
#include "mt_spm.h"
|
||||
|
||||
/**************************************
|
||||
* Config and Parameter
|
||||
**************************************/
|
||||
#define POWER_ON_VAL0_DEF 0x0000F100
|
||||
#define POWER_ON_VAL1_DEF 0x80015860
|
||||
#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
|
||||
#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
|
||||
|
||||
/**************************************
|
||||
* Define and Declare
|
||||
**************************************/
|
||||
/* PCM_PWR_IO_EN */
|
||||
#define PCM_PWRIO_EN_R0 (1U << 0)
|
||||
#define PCM_PWRIO_EN_R7 (1U << 7)
|
||||
#define PCM_RF_SYNC_R0 (1U << 16)
|
||||
#define PCM_RF_SYNC_R6 (1U << 22)
|
||||
#define PCM_RF_SYNC_R7 (1U << 23)
|
||||
|
||||
/* SPM_SWINT */
|
||||
#define PCM_SW_INT0 (1U << 0)
|
||||
#define PCM_SW_INT1 (1U << 1)
|
||||
#define PCM_SW_INT2 (1U << 2)
|
||||
#define PCM_SW_INT3 (1U << 3)
|
||||
#define PCM_SW_INT4 (1U << 4)
|
||||
#define PCM_SW_INT5 (1U << 5)
|
||||
#define PCM_SW_INT6 (1U << 6)
|
||||
#define PCM_SW_INT7 (1U << 7)
|
||||
#define PCM_SW_INT8 (1U << 8)
|
||||
#define PCM_SW_INT9 (1U << 9)
|
||||
#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
|
||||
PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
|
||||
PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
|
||||
PCM_SW_INT0)
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
#define WFI_OP_AND 1
|
||||
#define WFI_OP_OR 0
|
||||
|
||||
/* SPM_IRQ_MASK */
|
||||
#define ISRM_TWAM (1U << 2)
|
||||
#define ISRM_PCM_RETURN (1U << 3)
|
||||
#define ISRM_RET_IRQ0 (1U << 8)
|
||||
#define ISRM_RET_IRQ1 (1U << 9)
|
||||
#define ISRM_RET_IRQ2 (1U << 10)
|
||||
#define ISRM_RET_IRQ3 (1U << 11)
|
||||
#define ISRM_RET_IRQ4 (1U << 12)
|
||||
#define ISRM_RET_IRQ5 (1U << 13)
|
||||
#define ISRM_RET_IRQ6 (1U << 14)
|
||||
#define ISRM_RET_IRQ7 (1U << 15)
|
||||
#define ISRM_RET_IRQ8 (1U << 16)
|
||||
#define ISRM_RET_IRQ9 (1U << 17)
|
||||
#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
|
||||
(ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
|
||||
(ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
|
||||
(ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
|
||||
(ISRM_RET_IRQ1))
|
||||
#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
|
||||
#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
|
||||
|
||||
/* SPM_IRQ_STA */
|
||||
#define ISRS_TWAM (1U << 2)
|
||||
#define ISRS_PCM_RETURN (1U << 3)
|
||||
#define ISRC_TWAM ISRS_TWAM
|
||||
#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
|
||||
#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
|
||||
|
||||
/* SPM_WAKEUP_MISC */
|
||||
#define WAKE_MISC_GIC_WAKEUP 0x3FF
|
||||
#define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB
|
||||
#define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
|
||||
#define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB
|
||||
#define WAKE_MISC_PMIC_OUT_B ((1U << 19) | (1U << 20))
|
||||
#define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB
|
||||
#define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB
|
||||
#define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB
|
||||
#define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB
|
||||
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB
|
||||
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB
|
||||
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB
|
||||
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB
|
||||
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
|
||||
#define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB
|
||||
#define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB
|
||||
|
||||
/* ABORT MASK for DEBUG FOORTPRINT */
|
||||
#define DEBUG_ABORT_MASK \
|
||||
(SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
|
||||
SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
|
||||
|
||||
#define DEBUG_ABORT_MASK_1 \
|
||||
(SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
|
||||
SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
|
||||
SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
|
||||
SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
|
||||
SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
|
||||
SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
|
||||
SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
|
||||
|
||||
#define MCUPM_MBOX_WAKEUP_CPU 0x0C55FD10
|
||||
|
||||
struct pwr_ctrl {
|
||||
uint32_t pcm_flags;
|
||||
uint32_t pcm_flags_cust;
|
||||
uint32_t pcm_flags_cust_set;
|
||||
uint32_t pcm_flags_cust_clr;
|
||||
uint32_t pcm_flags1;
|
||||
uint32_t pcm_flags1_cust;
|
||||
uint32_t pcm_flags1_cust_set;
|
||||
uint32_t pcm_flags1_cust_clr;
|
||||
uint32_t timer_val;
|
||||
uint32_t timer_val_cust;
|
||||
uint32_t timer_val_ramp_en;
|
||||
uint32_t timer_val_ramp_en_sec;
|
||||
uint32_t wake_src;
|
||||
uint32_t wake_src_cust;
|
||||
uint32_t wakelock_timer_val;
|
||||
uint8_t wdt_disable;
|
||||
|
||||
/* Auto-gen Start */
|
||||
|
||||
/* SPM_CLK_CON */
|
||||
uint8_t reg_srcclken0_ctl;
|
||||
uint8_t reg_srcclken1_ctl;
|
||||
uint8_t reg_spm_lock_infra_dcm;
|
||||
uint8_t reg_srcclken_mask;
|
||||
uint8_t reg_md1_c32rm_en;
|
||||
uint8_t reg_md2_c32rm_en;
|
||||
uint8_t reg_clksq0_sel_ctrl;
|
||||
uint8_t reg_clksq1_sel_ctrl;
|
||||
uint8_t reg_srcclken0_en;
|
||||
uint8_t reg_srcclken1_en;
|
||||
uint32_t reg_sysclk0_src_mask_b;
|
||||
uint32_t reg_sysclk1_src_mask_b;
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
uint8_t reg_wfi_op;
|
||||
uint8_t reg_wfi_type;
|
||||
uint8_t reg_mp0_cputop_idle_mask;
|
||||
uint8_t reg_mp1_cputop_idle_mask;
|
||||
uint8_t reg_mcusys_idle_mask;
|
||||
uint8_t reg_md_apsrc_1_sel;
|
||||
uint8_t reg_md_apsrc_0_sel;
|
||||
uint8_t reg_conn_apsrc_sel;
|
||||
|
||||
/* SPM_SRC6_MASK */
|
||||
uint8_t reg_dpmaif_srcclkena_mask_b;
|
||||
uint8_t reg_dpmaif_infra_req_mask_b;
|
||||
uint8_t reg_dpmaif_apsrc_req_mask_b;
|
||||
uint8_t reg_dpmaif_vrf18_req_mask_b;
|
||||
uint8_t reg_dpmaif_ddr_en_mask_b;
|
||||
/* SPM_SRC_REQ */
|
||||
uint8_t reg_spm_apsrc_req;
|
||||
uint8_t reg_spm_f26m_req;
|
||||
uint8_t reg_spm_infra_req;
|
||||
uint8_t reg_spm_vrf18_req;
|
||||
uint8_t reg_spm_ddr_en_req;
|
||||
uint8_t reg_spm_dvfs_req;
|
||||
uint8_t reg_spm_sw_mailbox_req;
|
||||
uint8_t reg_spm_sspm_mailbox_req;
|
||||
uint8_t reg_spm_adsp_mailbox_req;
|
||||
uint8_t reg_spm_scp_mailbox_req;
|
||||
|
||||
/* SPM_SRC_MASK */
|
||||
uint8_t reg_md_srcclkena_0_mask_b;
|
||||
uint8_t reg_md_srcclkena2infra_req_0_mask_b;
|
||||
uint8_t reg_md_apsrc2infra_req_0_mask_b;
|
||||
uint8_t reg_md_apsrc_req_0_mask_b;
|
||||
uint8_t reg_md_vrf18_req_0_mask_b;
|
||||
uint8_t reg_md_ddr_en_0_mask_b;
|
||||
uint8_t reg_md_srcclkena_1_mask_b;
|
||||
uint8_t reg_md_srcclkena2infra_req_1_mask_b;
|
||||
uint8_t reg_md_apsrc2infra_req_1_mask_b;
|
||||
uint8_t reg_md_apsrc_req_1_mask_b;
|
||||
uint8_t reg_md_vrf18_req_1_mask_b;
|
||||
uint8_t reg_md_ddr_en_1_mask_b;
|
||||
uint8_t reg_conn_srcclkena_mask_b;
|
||||
uint8_t reg_conn_srcclkenb_mask_b;
|
||||
uint8_t reg_conn_infra_req_mask_b;
|
||||
uint8_t reg_conn_apsrc_req_mask_b;
|
||||
uint8_t reg_conn_vrf18_req_mask_b;
|
||||
uint8_t reg_conn_ddr_en_mask_b;
|
||||
uint8_t reg_conn_vfe28_mask_b;
|
||||
uint8_t reg_srcclkeni0_srcclkena_mask_b;
|
||||
uint8_t reg_srcclkeni0_infra_req_mask_b;
|
||||
uint8_t reg_srcclkeni1_srcclkena_mask_b;
|
||||
uint8_t reg_srcclkeni1_infra_req_mask_b;
|
||||
uint8_t reg_srcclkeni2_srcclkena_mask_b;
|
||||
uint8_t reg_srcclkeni2_infra_req_mask_b;
|
||||
uint8_t reg_infrasys_apsrc_req_mask_b;
|
||||
uint8_t reg_infrasys_ddr_en_mask_b;
|
||||
uint8_t reg_md32_srcclkena_mask_b;
|
||||
uint8_t reg_md32_infra_req_mask_b;
|
||||
uint8_t reg_md32_apsrc_req_mask_b;
|
||||
uint8_t reg_md32_vrf18_req_mask_b;
|
||||
uint8_t reg_md32_ddr_en_mask_b;
|
||||
|
||||
/* SPM_SRC2_MASK */
|
||||
uint8_t reg_scp_srcclkena_mask_b;
|
||||
uint8_t reg_scp_infra_req_mask_b;
|
||||
uint8_t reg_scp_apsrc_req_mask_b;
|
||||
uint8_t reg_scp_vrf18_req_mask_b;
|
||||
uint8_t reg_scp_ddr_en_mask_b;
|
||||
uint8_t reg_audio_dsp_srcclkena_mask_b;
|
||||
uint8_t reg_audio_dsp_infra_req_mask_b;
|
||||
uint8_t reg_audio_dsp_apsrc_req_mask_b;
|
||||
uint8_t reg_audio_dsp_vrf18_req_mask_b;
|
||||
uint8_t reg_audio_dsp_ddr_en_mask_b;
|
||||
uint8_t reg_ufs_srcclkena_mask_b;
|
||||
uint8_t reg_ufs_infra_req_mask_b;
|
||||
uint8_t reg_ufs_apsrc_req_mask_b;
|
||||
uint8_t reg_ufs_vrf18_req_mask_b;
|
||||
uint8_t reg_ufs_ddr_en_mask_b;
|
||||
uint8_t reg_disp0_apsrc_req_mask_b;
|
||||
uint8_t reg_disp0_ddr_en_mask_b;
|
||||
uint8_t reg_disp1_apsrc_req_mask_b;
|
||||
uint8_t reg_disp1_ddr_en_mask_b;
|
||||
uint8_t reg_gce_infra_req_mask_b;
|
||||
uint8_t reg_gce_apsrc_req_mask_b;
|
||||
uint8_t reg_gce_vrf18_req_mask_b;
|
||||
uint8_t reg_gce_ddr_en_mask_b;
|
||||
uint8_t reg_apu_srcclkena_mask_b;
|
||||
uint8_t reg_apu_infra_req_mask_b;
|
||||
uint8_t reg_apu_apsrc_req_mask_b;
|
||||
uint8_t reg_apu_vrf18_req_mask_b;
|
||||
uint8_t reg_apu_ddr_en_mask_b;
|
||||
uint8_t reg_cg_check_srcclkena_mask_b;
|
||||
uint8_t reg_cg_check_apsrc_req_mask_b;
|
||||
uint8_t reg_cg_check_vrf18_req_mask_b;
|
||||
uint8_t reg_cg_check_ddr_en_mask_b;
|
||||
|
||||
/* SPM_SRC3_MASK */
|
||||
uint8_t reg_dvfsrc_event_trigger_mask_b;
|
||||
uint8_t reg_sw2spm_int0_mask_b;
|
||||
uint8_t reg_sw2spm_int1_mask_b;
|
||||
uint8_t reg_sw2spm_int2_mask_b;
|
||||
uint8_t reg_sw2spm_int3_mask_b;
|
||||
uint8_t reg_sc_adsp2spm_wakeup_mask_b;
|
||||
uint8_t reg_sc_sspm2spm_wakeup_mask_b;
|
||||
uint8_t reg_sc_scp2spm_wakeup_mask_b;
|
||||
uint8_t reg_csyspwrreq_mask;
|
||||
uint8_t reg_spm_srcclkena_reserved_mask_b;
|
||||
uint8_t reg_spm_infra_req_reserved_mask_b;
|
||||
uint8_t reg_spm_apsrc_req_reserved_mask_b;
|
||||
uint8_t reg_spm_vrf18_req_reserved_mask_b;
|
||||
uint8_t reg_spm_ddr_en_reserved_mask_b;
|
||||
uint8_t reg_mcupm_srcclkena_mask_b;
|
||||
uint8_t reg_mcupm_infra_req_mask_b;
|
||||
uint8_t reg_mcupm_apsrc_req_mask_b;
|
||||
uint8_t reg_mcupm_vrf18_req_mask_b;
|
||||
uint8_t reg_mcupm_ddr_en_mask_b;
|
||||
uint8_t reg_msdc0_srcclkena_mask_b;
|
||||
uint8_t reg_msdc0_infra_req_mask_b;
|
||||
uint8_t reg_msdc0_apsrc_req_mask_b;
|
||||
uint8_t reg_msdc0_vrf18_req_mask_b;
|
||||
uint8_t reg_msdc0_ddr_en_mask_b;
|
||||
uint8_t reg_msdc1_srcclkena_mask_b;
|
||||
uint8_t reg_msdc1_infra_req_mask_b;
|
||||
uint8_t reg_msdc1_apsrc_req_mask_b;
|
||||
uint8_t reg_msdc1_vrf18_req_mask_b;
|
||||
uint8_t reg_msdc1_ddr_en_mask_b;
|
||||
|
||||
/* SPM_SRC4_MASK */
|
||||
uint32_t ccif_event_mask_b;
|
||||
uint8_t reg_bak_psri_srcclkena_mask_b;
|
||||
uint8_t reg_bak_psri_infra_req_mask_b;
|
||||
uint8_t reg_bak_psri_apsrc_req_mask_b;
|
||||
uint8_t reg_bak_psri_vrf18_req_mask_b;
|
||||
uint8_t reg_bak_psri_ddr_en_mask_b;
|
||||
uint8_t reg_dramc0_md32_infra_req_mask_b;
|
||||
uint8_t reg_dramc0_md32_vrf18_req_mask_b;
|
||||
uint8_t reg_dramc1_md32_infra_req_mask_b;
|
||||
uint8_t reg_dramc1_md32_vrf18_req_mask_b;
|
||||
uint8_t reg_conn_srcclkenb2pwrap_mask_b;
|
||||
uint8_t reg_dramc0_md32_wakeup_mask;
|
||||
uint8_t reg_dramc1_md32_wakeup_mask;
|
||||
|
||||
/* SPM_SRC5_MASK */
|
||||
uint32_t reg_mcusys_merge_apsrc_req_mask_b;
|
||||
uint32_t reg_mcusys_merge_ddr_en_mask_b;
|
||||
uint8_t reg_msdc2_srcclkena_mask_b;
|
||||
uint8_t reg_msdc2_infra_req_mask_b;
|
||||
uint8_t reg_msdc2_apsrc_req_mask_b;
|
||||
uint8_t reg_msdc2_vrf18_req_mask_b;
|
||||
uint8_t reg_msdc2_ddr_en_mask_b;
|
||||
uint8_t reg_pcie_srcclkena_mask_b;
|
||||
uint8_t reg_pcie_infra_req_mask_b;
|
||||
uint8_t reg_pcie_apsrc_req_mask_b;
|
||||
uint8_t reg_pcie_vrf18_req_mask_b;
|
||||
uint8_t reg_pcie_ddr_en_mask_b;
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
uint32_t reg_wakeup_event_mask;
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
uint32_t reg_ext_wakeup_event_mask;
|
||||
|
||||
/* Auto-gen End */
|
||||
};
|
||||
|
||||
/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
|
||||
enum pwr_ctrl_enum {
|
||||
PW_PCM_FLAGS,
|
||||
PW_PCM_FLAGS_CUST,
|
||||
PW_PCM_FLAGS_CUST_SET,
|
||||
PW_PCM_FLAGS_CUST_CLR,
|
||||
PW_PCM_FLAGS1,
|
||||
PW_PCM_FLAGS1_CUST,
|
||||
PW_PCM_FLAGS1_CUST_SET,
|
||||
PW_PCM_FLAGS1_CUST_CLR,
|
||||
PW_TIMER_VAL,
|
||||
PW_TIMER_VAL_CUST,
|
||||
PW_TIMER_VAL_RAMP_EN,
|
||||
PW_TIMER_VAL_RAMP_EN_SEC,
|
||||
PW_WAKE_SRC,
|
||||
PW_WAKE_SRC_CUST,
|
||||
PW_WAKELOCK_TIMER_VAL,
|
||||
PW_WDT_DISABLE,
|
||||
|
||||
/* SPM_CLK_CON */
|
||||
PW_REG_SRCCLKEN0_CTL,
|
||||
PW_REG_SRCCLKEN1_CTL,
|
||||
PW_REG_SPM_LOCK_INFRA_DCM,
|
||||
PW_REG_SRCCLKEN_MASK,
|
||||
PW_REG_MD1_C32RM_EN,
|
||||
PW_REG_MD2_C32RM_EN,
|
||||
PW_REG_CLKSQ0_SEL_CTRL,
|
||||
PW_REG_CLKSQ1_SEL_CTRL,
|
||||
PW_REG_SRCCLKEN0_EN,
|
||||
PW_REG_SRCCLKEN1_EN,
|
||||
PW_REG_SYSCLK0_SRC_MASK_B,
|
||||
PW_REG_SYSCLK1_SRC_MASK_B,
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
PW_REG_WFI_OP,
|
||||
PW_REG_WFI_TYPE,
|
||||
PW_REG_MP0_CPUTOP_IDLE_MASK,
|
||||
PW_REG_MP1_CPUTOP_IDLE_MASK,
|
||||
PW_REG_MCUSYS_IDLE_MASK,
|
||||
PW_REG_MD_APSRC_1_SEL,
|
||||
PW_REG_MD_APSRC_0_SEL,
|
||||
PW_REG_CONN_APSRC_SEL,
|
||||
|
||||
/* SPM_SRC6_MASK */
|
||||
PW_REG_DPMAIF_SRCCLKENA_MASK_B,
|
||||
PW_REG_DPMAIF_INFRA_REQ_MASK_B,
|
||||
PW_REG_DPMAIF_APSRC_REQ_MASK_B,
|
||||
PW_REG_DPMAIF_VRF18_REQ_MASK_B,
|
||||
PW_REG_DPMAIF_DDR_EN_MASK_B,
|
||||
|
||||
/* SPM_SRC_REQ */
|
||||
PW_REG_SPM_APSRC_REQ,
|
||||
PW_REG_SPM_F26M_REQ,
|
||||
PW_REG_SPM_INFRA_REQ,
|
||||
PW_REG_SPM_VRF18_REQ,
|
||||
PW_REG_SPM_DDR_EN_REQ,
|
||||
PW_REG_SPM_DVFS_REQ,
|
||||
PW_REG_SPM_SW_MAILBOX_REQ,
|
||||
PW_REG_SPM_SSPM_MAILBOX_REQ,
|
||||
PW_REG_SPM_ADSP_MAILBOX_REQ,
|
||||
PW_REG_SPM_SCP_MAILBOX_REQ,
|
||||
|
||||
/* SPM_SRC_MASK */
|
||||
PW_REG_MD_SRCCLKENA_0_MASK_B,
|
||||
PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
|
||||
PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
|
||||
PW_REG_MD_APSRC_REQ_0_MASK_B,
|
||||
PW_REG_MD_VRF18_REQ_0_MASK_B,
|
||||
PW_REG_MD_DDR_EN_0_MASK_B,
|
||||
PW_REG_MD_SRCCLKENA_1_MASK_B,
|
||||
PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
|
||||
PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
|
||||
PW_REG_MD_APSRC_REQ_1_MASK_B,
|
||||
PW_REG_MD_VRF18_REQ_1_MASK_B,
|
||||
PW_REG_MD_DDR_EN_1_MASK_B,
|
||||
PW_REG_CONN_SRCCLKENA_MASK_B,
|
||||
PW_REG_CONN_SRCCLKENB_MASK_B,
|
||||
PW_REG_CONN_INFRA_REQ_MASK_B,
|
||||
PW_REG_CONN_APSRC_REQ_MASK_B,
|
||||
PW_REG_CONN_VRF18_REQ_MASK_B,
|
||||
PW_REG_CONN_DDR_EN_MASK_B,
|
||||
PW_REG_CONN_VFE28_MASK_B,
|
||||
PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
|
||||
PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
|
||||
PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
|
||||
PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
|
||||
PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
|
||||
PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
|
||||
PW_REG_INFRASYS_APSRC_REQ_MASK_B,
|
||||
PW_REG_INFRASYS_DDR_EN_MASK_B,
|
||||
PW_REG_MD32_SRCCLKENA_MASK_B,
|
||||
PW_REG_MD32_INFRA_REQ_MASK_B,
|
||||
PW_REG_MD32_APSRC_REQ_MASK_B,
|
||||
PW_REG_MD32_VRF18_REQ_MASK_B,
|
||||
PW_REG_MD32_DDR_EN_MASK_B,
|
||||
|
||||
/* SPM_SRC2_MASK */
|
||||
PW_REG_SCP_SRCCLKENA_MASK_B,
|
||||
PW_REG_SCP_INFRA_REQ_MASK_B,
|
||||
PW_REG_SCP_APSRC_REQ_MASK_B,
|
||||
PW_REG_SCP_VRF18_REQ_MASK_B,
|
||||
PW_REG_SCP_DDR_EN_MASK_B,
|
||||
PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
|
||||
PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
|
||||
PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
|
||||
PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
|
||||
PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
|
||||
PW_REG_UFS_SRCCLKENA_MASK_B,
|
||||
PW_REG_UFS_INFRA_REQ_MASK_B,
|
||||
PW_REG_UFS_APSRC_REQ_MASK_B,
|
||||
PW_REG_UFS_VRF18_REQ_MASK_B,
|
||||
PW_REG_UFS_DDR_EN_MASK_B,
|
||||
PW_REG_DISP0_APSRC_REQ_MASK_B,
|
||||
PW_REG_DISP0_DDR_EN_MASK_B,
|
||||
PW_REG_DISP1_APSRC_REQ_MASK_B,
|
||||
PW_REG_DISP1_DDR_EN_MASK_B,
|
||||
PW_REG_GCE_INFRA_REQ_MASK_B,
|
||||
PW_REG_GCE_APSRC_REQ_MASK_B,
|
||||
PW_REG_GCE_VRF18_REQ_MASK_B,
|
||||
PW_REG_GCE_DDR_EN_MASK_B,
|
||||
PW_REG_APU_SRCCLKENA_MASK_B,
|
||||
PW_REG_APU_INFRA_REQ_MASK_B,
|
||||
PW_REG_APU_APSRC_REQ_MASK_B,
|
||||
PW_REG_APU_VRF18_REQ_MASK_B,
|
||||
PW_REG_APU_DDR_EN_MASK_B,
|
||||
PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
|
||||
PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
|
||||
PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
|
||||
PW_REG_CG_CHECK_DDR_EN_MASK_B,
|
||||
|
||||
/* SPM_SRC3_MASK */
|
||||
PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
|
||||
PW_REG_SW2SPM_INT0_MASK_B,
|
||||
PW_REG_SW2SPM_INT1_MASK_B,
|
||||
PW_REG_SW2SPM_INT2_MASK_B,
|
||||
PW_REG_SW2SPM_INT3_MASK_B,
|
||||
PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
|
||||
PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
|
||||
PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
|
||||
PW_REG_CSYSPWRREQ_MASK,
|
||||
PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
|
||||
PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
|
||||
PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
|
||||
PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
|
||||
PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
|
||||
PW_REG_MCUPM_SRCCLKENA_MASK_B,
|
||||
PW_REG_MCUPM_INFRA_REQ_MASK_B,
|
||||
PW_REG_MCUPM_APSRC_REQ_MASK_B,
|
||||
PW_REG_MCUPM_VRF18_REQ_MASK_B,
|
||||
PW_REG_MCUPM_DDR_EN_MASK_B,
|
||||
PW_REG_MSDC0_SRCCLKENA_MASK_B,
|
||||
PW_REG_MSDC0_INFRA_REQ_MASK_B,
|
||||
PW_REG_MSDC0_APSRC_REQ_MASK_B,
|
||||
PW_REG_MSDC0_VRF18_REQ_MASK_B,
|
||||
PW_REG_MSDC0_DDR_EN_MASK_B,
|
||||
PW_REG_MSDC1_SRCCLKENA_MASK_B,
|
||||
PW_REG_MSDC1_INFRA_REQ_MASK_B,
|
||||
PW_REG_MSDC1_APSRC_REQ_MASK_B,
|
||||
PW_REG_MSDC1_VRF18_REQ_MASK_B,
|
||||
PW_REG_MSDC1_DDR_EN_MASK_B,
|
||||
|
||||
/* SPM_SRC4_MASK */
|
||||
PW_CCIF_EVENT_MASK_B,
|
||||
PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
|
||||
PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
|
||||
PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
|
||||
PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
|
||||
PW_REG_BAK_PSRI_DDR_EN_MASK_B,
|
||||
PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
|
||||
PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
|
||||
PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
|
||||
PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
|
||||
PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
|
||||
PW_REG_DRAMC0_MD32_WAKEUP_MASK,
|
||||
PW_REG_DRAMC1_MD32_WAKEUP_MASK,
|
||||
|
||||
/* SPM_SRC5_MASK */
|
||||
PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
|
||||
PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
|
||||
PW_REG_MSDC2_SRCCLKENA_MASK_B,
|
||||
PW_REG_MSDC2_INFRA_REQ_MASK_B,
|
||||
PW_REG_MSDC2_APSRC_REQ_MASK_B,
|
||||
PW_REG_MSDC2_VRF18_REQ_MASK_B,
|
||||
PW_REG_MSDC2_DDR_EN_MASK_B,
|
||||
PW_REG_PCIE_SRCCLKENA_MASK_B,
|
||||
PW_REG_PCIE_INFRA_REQ_MASK_B,
|
||||
PW_REG_PCIE_APSRC_REQ_MASK_B,
|
||||
PW_REG_PCIE_VRF18_REQ_MASK_B,
|
||||
PW_REG_PCIE_DDR_EN_MASK_B,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
PW_REG_WAKEUP_EVENT_MASK,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
PW_REG_EXT_WAKEUP_EVENT_MASK,
|
||||
|
||||
PW_MAX_COUNT,
|
||||
};
|
||||
|
||||
#define SPM_INTERNAL_STATUS_HW_S1 (1U << 0)
|
||||
#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098
|
||||
#define SPM_ACK_CHK_3_HW_S1_CNT 1
|
||||
#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG 0x800
|
||||
#define SPM_ACK_CHK_3_CON_EN 0x110
|
||||
#define SPM_ACK_CHK_3_CON_CLR_ALL 0x2
|
||||
#define SPM_ACK_CHK_3_CON_RESULT 0x8000
|
||||
|
||||
struct wake_status_trace_comm {
|
||||
uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
|
||||
uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
|
||||
uint32_t timer_out; /* SPM_SW_RSV_6*/
|
||||
uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
|
||||
uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */
|
||||
uint32_t r12; /* SPM_SW_RSV_0 */
|
||||
uint32_t r13; /* PCM_REG13_DATA */
|
||||
uint32_t req_sta0; /* SRC_REQ_STA_0 */
|
||||
uint32_t req_sta1; /* SRC_REQ_STA_1 */
|
||||
uint32_t req_sta2; /* SRC_REQ_STA_2 */
|
||||
uint32_t req_sta3; /* SRC_REQ_STA_3 */
|
||||
uint32_t req_sta4; /* SRC_REQ_STA_4 */
|
||||
};
|
||||
|
||||
struct wake_status_trace {
|
||||
struct wake_status_trace_comm comm;
|
||||
};
|
||||
|
||||
struct wake_status {
|
||||
struct wake_status_trace tr;
|
||||
uint32_t r12; /* SPM_BK_WAKE_EVENT */
|
||||
uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */
|
||||
uint32_t raw_sta; /* SPM_WAKEUP_STA */
|
||||
uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */
|
||||
uint32_t md32pcm_wakeup_sta; /* MD32CPM_WAKEUP_STA */
|
||||
uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
|
||||
uint32_t wake_misc; /* SPM_BK_WAKE_MISC */
|
||||
uint32_t timer_out; /* SPM_BK_PCM_TIMER */
|
||||
uint32_t r13; /* PCM_REG13_DATA */
|
||||
uint32_t idle_sta; /* SUBSYS_IDLE_STA */
|
||||
uint32_t req_sta0; /* SRC_REQ_STA_0 */
|
||||
uint32_t req_sta1; /* SRC_REQ_STA_1 */
|
||||
uint32_t req_sta2; /* SRC_REQ_STA_2 */
|
||||
uint32_t req_sta3; /* SRC_REQ_STA_3 */
|
||||
uint32_t req_sta4; /* SRC_REQ_STA_4 */
|
||||
uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */
|
||||
uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
|
||||
uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
|
||||
uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
|
||||
uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
|
||||
uint32_t isr; /* SPM_IRQ_STA */
|
||||
uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
|
||||
uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
|
||||
uint32_t clk_settle; /* SPM_CLK_SETTLE */
|
||||
uint32_t src_req; /* SPM_SRC_REQ */
|
||||
uint32_t log_index;
|
||||
uint32_t abort;
|
||||
uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */
|
||||
uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */
|
||||
uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */
|
||||
uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */
|
||||
uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */
|
||||
uint32_t mcupm_req_sta;
|
||||
};
|
||||
|
||||
struct spm_lp_scen {
|
||||
struct pcm_desc *pcmdesc;
|
||||
struct pwr_ctrl *pwrctrl;
|
||||
};
|
||||
|
||||
extern struct spm_lp_scen __spm_vcorefs;
|
||||
extern void __spm_set_cpu_status(unsigned int cpu);
|
||||
extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
|
||||
extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
|
||||
extern void __spm_init_pcm_register(void);
|
||||
extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
|
||||
unsigned int resource_usage);
|
||||
extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
|
||||
extern void __spm_disable_pcm_timer(void);
|
||||
extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
|
||||
extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
|
||||
extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
|
||||
extern void __spm_send_cpu_wakeup_event(void);
|
||||
extern void __spm_get_wakeup_status(struct wake_status *wakesta,
|
||||
unsigned int ext_status);
|
||||
extern void __spm_clean_after_wakeup(void);
|
||||
extern wake_reason_t
|
||||
__spm_output_wake_reason(int state_id, const struct wake_status *wakesta);
|
||||
extern void
|
||||
__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
|
||||
const struct pwr_ctrl *src_pwr_ctrl);
|
||||
extern void __spm_set_pcm_wdt(int en);
|
||||
extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
|
||||
extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
|
||||
extern void __spm_ext_int_wakeup_req_clr(void);
|
||||
extern void __spm_xo_soc_bblpm(int en);
|
||||
|
||||
static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
|
||||
uint32_t flags)
|
||||
{
|
||||
if (pwrctrl->pcm_flags_cust == 0U) {
|
||||
pwrctrl->pcm_flags = flags;
|
||||
} else {
|
||||
pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
|
||||
uint32_t flags)
|
||||
{
|
||||
if (pwrctrl->pcm_flags1_cust == 0U) {
|
||||
pwrctrl->pcm_flags1 = flags;
|
||||
} else {
|
||||
pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
|
||||
}
|
||||
}
|
||||
|
||||
extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
|
||||
|
||||
static inline void spm_hw_s1_state_monitor_resume(void)
|
||||
{
|
||||
__spm_hw_s1_state_monitor(1, NULL);
|
||||
}
|
||||
|
||||
static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
|
||||
{
|
||||
__spm_hw_s1_state_monitor(0, status);
|
||||
}
|
||||
#endif /* MT_SPM_INTERNAL_H */
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_pmic_wrap.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <plat_pm.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
/* PMIC_WRAP MT6359 */
|
||||
#define VCORE_BASE_UV 40000
|
||||
#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
|
||||
#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
|
||||
|
||||
#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
|
||||
#define SPM_DATA_SHIFT 16
|
||||
|
||||
#define BUCK_VGPU11_ELR0 0x15B4
|
||||
#define TOP_SPI_CON0 0x0456
|
||||
#define BUCK_TOP_CON1 0x1443
|
||||
#define TOP_CON 0x0013
|
||||
#define TOP_DIG_WPK 0x03a9
|
||||
#define TOP_CON_LOCK 0x03a8
|
||||
#define TOP_CLK_CON0 0x0134
|
||||
|
||||
struct pmic_wrap_cmd {
|
||||
unsigned long cmd_addr;
|
||||
unsigned long cmd_wdata;
|
||||
};
|
||||
|
||||
struct pmic_wrap_setting {
|
||||
enum pmic_wrap_phase_id phase;
|
||||
struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
|
||||
struct {
|
||||
struct {
|
||||
unsigned long cmd_addr;
|
||||
unsigned long cmd_wdata;
|
||||
} _[NR_PMIC_WRAP_CMD];
|
||||
const int nr_idx;
|
||||
} set[NR_PMIC_WRAP_PHASE];
|
||||
};
|
||||
|
||||
static struct pmic_wrap_setting pw = {
|
||||
.phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
|
||||
.addr = { {0UL, 0UL} },
|
||||
.set[PMIC_WRAP_PHASE_ALLINONE] = {
|
||||
._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(72500),},
|
||||
._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
|
||||
._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
|
||||
._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(57500),},
|
||||
._[CMD_4] = {TOP_SPI_CON0, 0x1,},
|
||||
._[CMD_5] = {TOP_SPI_CON0, 0x0,},
|
||||
._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
|
||||
._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
|
||||
._[CMD_8] = {TOP_CON, 0x3,},
|
||||
._[CMD_9] = {TOP_CON, 0x0,},
|
||||
._[CMD_10] = {TOP_DIG_WPK, 0x63,},
|
||||
._[CMD_11] = {TOP_CON_LOCK, 0x15,},
|
||||
._[CMD_12] = {TOP_DIG_WPK, 0x0,},
|
||||
._[CMD_13] = {TOP_CON_LOCK, 0x0,},
|
||||
._[CMD_14] = {TOP_CLK_CON0, 0x40,},
|
||||
._[CMD_15] = {TOP_CLK_CON0, 0x0,},
|
||||
.nr_idx = NR_IDX_ALL,
|
||||
},
|
||||
};
|
||||
|
||||
void _mt_spm_pmic_table_init(void)
|
||||
{
|
||||
struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
|
||||
{(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
|
||||
{(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
|
||||
{(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
|
||||
{(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
|
||||
{(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
|
||||
{(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
|
||||
{(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
|
||||
{(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
|
||||
{(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
|
||||
{(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
|
||||
{(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
|
||||
{(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
|
||||
{(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
|
||||
{(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
|
||||
{(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
|
||||
{(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
|
||||
};
|
||||
|
||||
memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
|
||||
}
|
||||
|
||||
void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
|
||||
{
|
||||
uint32_t idx, addr, data;
|
||||
|
||||
if (phase >= NR_PMIC_WRAP_PHASE) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (pw.phase == phase) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (pw.addr[0].cmd_addr == 0UL) {
|
||||
_mt_spm_pmic_table_init();
|
||||
}
|
||||
|
||||
pw.phase = phase;
|
||||
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
|
||||
|
||||
for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) {
|
||||
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
|
||||
data = pw.set[phase]._[idx].cmd_wdata;
|
||||
mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
|
||||
}
|
||||
}
|
||||
|
||||
void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
|
||||
uint32_t cmd_wdata)
|
||||
{
|
||||
uint32_t addr;
|
||||
|
||||
if (phase >= NR_PMIC_WRAP_PHASE) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (idx >= pw.set[phase].nr_idx) {
|
||||
return;
|
||||
}
|
||||
|
||||
pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
|
||||
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
|
||||
|
||||
if (pw.phase == phase) {
|
||||
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
|
||||
mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
|
||||
{
|
||||
if (phase >= NR_PMIC_WRAP_PHASE) {
|
||||
return 0UL;
|
||||
}
|
||||
|
||||
if (idx >= pw.set[phase].nr_idx) {
|
||||
return 0UL;
|
||||
}
|
||||
|
||||
return pw.set[phase]._[idx].cmd_wdata;
|
||||
}
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/****************************************************************
|
||||
* Auto generated by DE, please DO NOT modify this file directly.
|
||||
*****************************************************************/
|
||||
#ifndef MT_SPM_PMIC_WRAP_H
|
||||
#define MT_SPM_PMIC_WRAP_H
|
||||
|
||||
enum pmic_wrap_phase_id {
|
||||
PMIC_WRAP_PHASE_ALLINONE,
|
||||
NR_PMIC_WRAP_PHASE,
|
||||
};
|
||||
|
||||
/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
|
||||
enum {
|
||||
CMD_0, /* 0x0 */
|
||||
CMD_1, /* 0x1 */
|
||||
CMD_2, /* 0x2 */
|
||||
CMD_3, /* 0x3 */
|
||||
CMD_4, /* 0x4 */
|
||||
CMD_5, /* 0x5 */
|
||||
CMD_6, /* 0x6 */
|
||||
CMD_7, /* 0x7 */
|
||||
CMD_8, /* 0x8 */
|
||||
CMD_9, /* 0x9 */
|
||||
CMD_10, /* 0xA */
|
||||
CMD_11, /* 0xB */
|
||||
CMD_12, /* 0xC */
|
||||
CMD_13, /* 0xD */
|
||||
CMD_14, /* 0xE */
|
||||
CMD_15, /* 0xF */
|
||||
NR_IDX_ALL,
|
||||
};
|
||||
|
||||
/* APIs */
|
||||
extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
|
||||
extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
|
||||
uint32_t idx, uint32_t cmd_wdata);
|
||||
extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
|
||||
uint32_t idx);
|
||||
#endif /* MT_SPM_PMIC_WRAP_H */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_RESOURCE_REQ_H
|
||||
#define MT_SPM_RESOURCE_REQ_H
|
||||
|
||||
/* SPM resource request internal bit */
|
||||
#define MT_SPM_BIT_XO_FPM 0
|
||||
#define MT_SPM_BIT_26M 1
|
||||
#define MT_SPM_BIT_INFRA 2
|
||||
#define MT_SPM_BIT_SYSPLL 3
|
||||
#define MT_SPM_BIT_DRAM_S0 4
|
||||
#define MT_SPM_BIT_DRAM_S1 5
|
||||
|
||||
/* SPM resource request internal bit_mask */
|
||||
#define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM)
|
||||
#define MT_SPM_26M BIT(MT_SPM_BIT_26M)
|
||||
#define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA)
|
||||
#define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL)
|
||||
#define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0)
|
||||
#define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1)
|
||||
#endif /* MT_SPM_RESOURCE_REQ_H */
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_conservation.h>
|
||||
#include <mt_spm_internal.h>
|
||||
#include <mt_spm_rc_internal.h>
|
||||
#include <mt_spm_reg.h>
|
||||
#include <mt_spm_resource_req.h>
|
||||
#include <mt_spm_suspend.h>
|
||||
#include <plat_pm.h>
|
||||
#include <uart.h>
|
||||
|
||||
#define SPM_SUSPEND_SLEEP_PCM_FLAG \
|
||||
(SPM_FLAG_DISABLE_INFRA_PDN | \
|
||||
SPM_FLAG_DISABLE_VCORE_DVS | \
|
||||
SPM_FLAG_DISABLE_VCORE_DFS | \
|
||||
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
|
||||
SPM_FLAG_USE_SRCCLKENO2 | \
|
||||
SPM_FLAG_ENABLE_MD_MUMTAS | \
|
||||
SPM_FLAG_SRAM_SLEEP_CTRL)
|
||||
|
||||
#define SPM_SUSPEND_SLEEP_PCM_FLAG1 \
|
||||
(SPM_FLAG1_DISABLE_MD26M_CK_OFF)
|
||||
|
||||
#define SPM_SUSPEND_PCM_FLAG \
|
||||
(SPM_FLAG_DISABLE_VCORE_DVS | \
|
||||
SPM_FLAG_DISABLE_VCORE_DFS | \
|
||||
SPM_FLAG_ENABLE_TIA_WORKAROUND | \
|
||||
SPM_FLAG_ENABLE_MD_MUMTAS | \
|
||||
SPM_FLAG_SRAM_SLEEP_CTRL)
|
||||
|
||||
#define SPM_SUSPEND_PCM_FLAG1 \
|
||||
(SPM_FLAG1_DISABLE_MD26M_CK_OFF)
|
||||
|
||||
#define __WAKE_SRC_FOR_SUSPEND_COMMON__ \
|
||||
(R12_PCM_TIMER | \
|
||||
R12_KP_IRQ_B | \
|
||||
R12_APWDT_EVENT_B | \
|
||||
R12_APXGPT1_EVENT_B | \
|
||||
R12_CONN2AP_SPM_WAKEUP_B | \
|
||||
R12_EINT_EVENT_B | \
|
||||
R12_CONN_WDT_IRQ_B | \
|
||||
R12_CCIF0_EVENT_B | \
|
||||
R12_SSPM2SPM_WAKEUP_B | \
|
||||
R12_SCP2SPM_WAKEUP_B | \
|
||||
R12_ADSP2SPM_WAKEUP_B | \
|
||||
R12_USBX_CDSC_B | \
|
||||
R12_USBX_POWERDWN_B | \
|
||||
R12_SYS_TIMER_EVENT_B | \
|
||||
R12_EINT_EVENT_SECURE_B | \
|
||||
R12_CCIF1_EVENT_B | \
|
||||
R12_SYS_CIRQ_IRQ_B | \
|
||||
R12_MD2AP_PEER_EVENT_B | \
|
||||
R12_MD1_WDT_B | \
|
||||
R12_CLDMA_EVENT_B | \
|
||||
R12_REG_CPU_WAKEUP | \
|
||||
R12_APUSYS_WAKE_HOST_B | \
|
||||
R12_PCIE_BRIDGE_IRQ | \
|
||||
R12_PCIE_IRQ)
|
||||
|
||||
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
|
||||
#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
|
||||
#else
|
||||
#define WAKE_SRC_FOR_SUSPEND \
|
||||
(__WAKE_SRC_FOR_SUSPEND_COMMON__ | \
|
||||
R12_SEJ_EVENT_B)
|
||||
#endif
|
||||
|
||||
static struct pwr_ctrl suspend_ctrl = {
|
||||
.wake_src = WAKE_SRC_FOR_SUSPEND,
|
||||
.pcm_flags = SPM_SUSPEND_PCM_FLAG | SPM_FLAG_DISABLE_INFRA_PDN,
|
||||
.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
|
||||
|
||||
/* Auto-gen Start */
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
.reg_wfi_op = 0,
|
||||
.reg_wfi_type = 0,
|
||||
.reg_mp0_cputop_idle_mask = 0,
|
||||
.reg_mp1_cputop_idle_mask = 0,
|
||||
.reg_mcusys_idle_mask = 0,
|
||||
.reg_md_apsrc_1_sel = 0,
|
||||
.reg_md_apsrc_0_sel = 0,
|
||||
.reg_conn_apsrc_sel = 0,
|
||||
|
||||
/* SPM_SRC6_MASK */
|
||||
.reg_dpmaif_srcclkena_mask_b = 1,
|
||||
.reg_dpmaif_infra_req_mask_b = 1,
|
||||
.reg_dpmaif_apsrc_req_mask_b = 1,
|
||||
.reg_dpmaif_vrf18_req_mask_b = 1,
|
||||
.reg_dpmaif_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC_REQ */
|
||||
.reg_spm_apsrc_req = 0,
|
||||
.reg_spm_f26m_req = 0,
|
||||
.reg_spm_infra_req = 0,
|
||||
.reg_spm_vrf18_req = 0,
|
||||
.reg_spm_ddr_en_req = 0,
|
||||
.reg_spm_dvfs_req = 0,
|
||||
.reg_spm_sw_mailbox_req = 0,
|
||||
.reg_spm_sspm_mailbox_req = 0,
|
||||
.reg_spm_adsp_mailbox_req = 0,
|
||||
.reg_spm_scp_mailbox_req = 0,
|
||||
|
||||
/* SPM_SRC_MASK */
|
||||
.reg_md_srcclkena_0_mask_b = 1,
|
||||
.reg_md_srcclkena2infra_req_0_mask_b = 0,
|
||||
.reg_md_apsrc2infra_req_0_mask_b = 1,
|
||||
.reg_md_apsrc_req_0_mask_b = 1,
|
||||
.reg_md_vrf18_req_0_mask_b = 1,
|
||||
.reg_md_ddr_en_0_mask_b = 1,
|
||||
.reg_md_srcclkena_1_mask_b = 0,
|
||||
.reg_md_srcclkena2infra_req_1_mask_b = 0,
|
||||
.reg_md_apsrc2infra_req_1_mask_b = 0,
|
||||
.reg_md_apsrc_req_1_mask_b = 0,
|
||||
.reg_md_vrf18_req_1_mask_b = 0,
|
||||
.reg_md_ddr_en_1_mask_b = 0,
|
||||
.reg_conn_srcclkena_mask_b = 1,
|
||||
.reg_conn_srcclkenb_mask_b = 0,
|
||||
.reg_conn_infra_req_mask_b = 1,
|
||||
.reg_conn_apsrc_req_mask_b = 1,
|
||||
.reg_conn_vrf18_req_mask_b = 1,
|
||||
.reg_conn_ddr_en_mask_b = 1,
|
||||
.reg_conn_vfe28_mask_b = 0,
|
||||
.reg_srcclkeni0_srcclkena_mask_b = 1,
|
||||
.reg_srcclkeni0_infra_req_mask_b = 1,
|
||||
.reg_srcclkeni1_srcclkena_mask_b = 0,
|
||||
.reg_srcclkeni1_infra_req_mask_b = 0,
|
||||
.reg_srcclkeni2_srcclkena_mask_b = 0,
|
||||
.reg_srcclkeni2_infra_req_mask_b = 0,
|
||||
.reg_infrasys_apsrc_req_mask_b = 0,
|
||||
.reg_infrasys_ddr_en_mask_b = 1,
|
||||
.reg_md32_srcclkena_mask_b = 1,
|
||||
.reg_md32_infra_req_mask_b = 1,
|
||||
.reg_md32_apsrc_req_mask_b = 1,
|
||||
.reg_md32_vrf18_req_mask_b = 1,
|
||||
.reg_md32_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC2_MASK */
|
||||
.reg_scp_srcclkena_mask_b = 1,
|
||||
.reg_scp_infra_req_mask_b = 1,
|
||||
.reg_scp_apsrc_req_mask_b = 1,
|
||||
.reg_scp_vrf18_req_mask_b = 1,
|
||||
.reg_scp_ddr_en_mask_b = 1,
|
||||
.reg_audio_dsp_srcclkena_mask_b = 1,
|
||||
.reg_audio_dsp_infra_req_mask_b = 1,
|
||||
.reg_audio_dsp_apsrc_req_mask_b = 1,
|
||||
.reg_audio_dsp_vrf18_req_mask_b = 1,
|
||||
.reg_audio_dsp_ddr_en_mask_b = 1,
|
||||
.reg_ufs_srcclkena_mask_b = 1,
|
||||
.reg_ufs_infra_req_mask_b = 1,
|
||||
.reg_ufs_apsrc_req_mask_b = 1,
|
||||
.reg_ufs_vrf18_req_mask_b = 1,
|
||||
.reg_ufs_ddr_en_mask_b = 1,
|
||||
.reg_disp0_apsrc_req_mask_b = 1,
|
||||
.reg_disp0_ddr_en_mask_b = 1,
|
||||
.reg_disp1_apsrc_req_mask_b = 1,
|
||||
.reg_disp1_ddr_en_mask_b = 1,
|
||||
.reg_gce_infra_req_mask_b = 1,
|
||||
.reg_gce_apsrc_req_mask_b = 1,
|
||||
.reg_gce_vrf18_req_mask_b = 1,
|
||||
.reg_gce_ddr_en_mask_b = 1,
|
||||
.reg_apu_srcclkena_mask_b = 1,
|
||||
.reg_apu_infra_req_mask_b = 1,
|
||||
.reg_apu_apsrc_req_mask_b = 1,
|
||||
.reg_apu_vrf18_req_mask_b = 1,
|
||||
.reg_apu_ddr_en_mask_b = 1,
|
||||
.reg_cg_check_srcclkena_mask_b = 0,
|
||||
.reg_cg_check_apsrc_req_mask_b = 0,
|
||||
.reg_cg_check_vrf18_req_mask_b = 0,
|
||||
.reg_cg_check_ddr_en_mask_b = 0,
|
||||
|
||||
/* SPM_SRC3_MASK */
|
||||
.reg_dvfsrc_event_trigger_mask_b = 1,
|
||||
.reg_sw2spm_int0_mask_b = 0,
|
||||
.reg_sw2spm_int1_mask_b = 0,
|
||||
.reg_sw2spm_int2_mask_b = 0,
|
||||
.reg_sw2spm_int3_mask_b = 0,
|
||||
.reg_sc_adsp2spm_wakeup_mask_b = 0,
|
||||
.reg_sc_sspm2spm_wakeup_mask_b = 0,
|
||||
.reg_sc_scp2spm_wakeup_mask_b = 0,
|
||||
.reg_csyspwrreq_mask = 1,
|
||||
.reg_spm_srcclkena_reserved_mask_b = 0,
|
||||
.reg_spm_infra_req_reserved_mask_b = 0,
|
||||
.reg_spm_apsrc_req_reserved_mask_b = 0,
|
||||
.reg_spm_vrf18_req_reserved_mask_b = 0,
|
||||
.reg_spm_ddr_en_reserved_mask_b = 0,
|
||||
.reg_mcupm_srcclkena_mask_b = 1,
|
||||
.reg_mcupm_infra_req_mask_b = 1,
|
||||
.reg_mcupm_apsrc_req_mask_b = 1,
|
||||
.reg_mcupm_vrf18_req_mask_b = 1,
|
||||
.reg_mcupm_ddr_en_mask_b = 1,
|
||||
.reg_msdc0_srcclkena_mask_b = 1,
|
||||
.reg_msdc0_infra_req_mask_b = 1,
|
||||
.reg_msdc0_apsrc_req_mask_b = 1,
|
||||
.reg_msdc0_vrf18_req_mask_b = 1,
|
||||
.reg_msdc0_ddr_en_mask_b = 1,
|
||||
.reg_msdc1_srcclkena_mask_b = 1,
|
||||
.reg_msdc1_infra_req_mask_b = 1,
|
||||
.reg_msdc1_apsrc_req_mask_b = 1,
|
||||
.reg_msdc1_vrf18_req_mask_b = 1,
|
||||
.reg_msdc1_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC4_MASK */
|
||||
.ccif_event_mask_b = 0xFFF,
|
||||
.reg_bak_psri_srcclkena_mask_b = 0,
|
||||
.reg_bak_psri_infra_req_mask_b = 0,
|
||||
.reg_bak_psri_apsrc_req_mask_b = 0,
|
||||
.reg_bak_psri_vrf18_req_mask_b = 0,
|
||||
.reg_bak_psri_ddr_en_mask_b = 0,
|
||||
.reg_dramc0_md32_infra_req_mask_b = 1,
|
||||
.reg_dramc0_md32_vrf18_req_mask_b = 0,
|
||||
.reg_dramc1_md32_infra_req_mask_b = 1,
|
||||
.reg_dramc1_md32_vrf18_req_mask_b = 0,
|
||||
.reg_conn_srcclkenb2pwrap_mask_b = 0,
|
||||
.reg_dramc0_md32_wakeup_mask = 1,
|
||||
.reg_dramc1_md32_wakeup_mask = 1,
|
||||
|
||||
/* SPM_SRC5_MASK */
|
||||
.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
|
||||
.reg_mcusys_merge_ddr_en_mask_b = 0x11,
|
||||
.reg_msdc2_srcclkena_mask_b = 1,
|
||||
.reg_msdc2_infra_req_mask_b = 1,
|
||||
.reg_msdc2_apsrc_req_mask_b = 1,
|
||||
.reg_msdc2_vrf18_req_mask_b = 1,
|
||||
.reg_msdc2_ddr_en_mask_b = 1,
|
||||
.reg_pcie_srcclkena_mask_b = 1,
|
||||
.reg_pcie_infra_req_mask_b = 1,
|
||||
.reg_pcie_apsrc_req_mask_b = 1,
|
||||
.reg_pcie_vrf18_req_mask_b = 1,
|
||||
.reg_pcie_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
.reg_wakeup_event_mask = 0x01382202,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
|
||||
|
||||
/* Auto-gen End */
|
||||
};
|
||||
|
||||
struct spm_lp_scen __spm_suspend = {
|
||||
.pwrctrl = &suspend_ctrl,
|
||||
};
|
||||
|
||||
int mt_spm_suspend_mode_set(int mode)
|
||||
{
|
||||
if (mode == MT_SPM_SUSPEND_SLEEP) {
|
||||
suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
|
||||
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
|
||||
} else {
|
||||
suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
|
||||
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
|
||||
unsigned int resource_req)
|
||||
{
|
||||
/* If FMAudio / ADSP is active, change to sleep suspend mode */
|
||||
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
|
||||
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
|
||||
}
|
||||
|
||||
/* Notify MCUPM that device is going suspend flow */
|
||||
mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
|
||||
|
||||
/* Notify UART to sleep */
|
||||
mt_uart_save();
|
||||
|
||||
return spm_conservation(state_id, ext_opand,
|
||||
&__spm_suspend, resource_req);
|
||||
}
|
||||
|
||||
void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
|
||||
struct wake_status **status)
|
||||
{
|
||||
spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
|
||||
|
||||
/* Notify UART to wakeup */
|
||||
mt_uart_restore();
|
||||
|
||||
/* Notify MCUPM that device leave suspend */
|
||||
mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
|
||||
|
||||
/* If FMAudio / ADSP is active, change back to suspend mode */
|
||||
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
|
||||
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
|
||||
}
|
||||
}
|
||||
|
||||
void mt_spm_suspend_init(void)
|
||||
{
|
||||
spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
|
||||
}
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_SUSPEND_H
|
||||
#define MT_SPM_SUSPEND_H
|
||||
|
||||
#include <mt_spm_internal.h>
|
||||
|
||||
#define MCUPM_MBOX_OFFSET_PDN 0x0C55FDA8
|
||||
#define MCUPM_POWER_DOWN 0x4D50444E
|
||||
|
||||
enum MT_SPM_SUSPEND_MODE {
|
||||
MT_SPM_SUSPEND_SYSTEM_PDN,
|
||||
MT_SPM_SUSPEND_SLEEP,
|
||||
};
|
||||
|
||||
extern int mt_spm_suspend_mode_set(int mode);
|
||||
extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
|
||||
unsigned int reosuce_req);
|
||||
extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
|
||||
struct wake_status **status);
|
||||
extern void mt_spm_suspend_init(void);
|
||||
#endif /* MT_SPM_SUSPEND_H */
|
|
@ -0,0 +1,403 @@
|
|||
/*
|
||||
* Copyright(C)2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include <mtk_sip_svc.h>
|
||||
#include <plat_pm.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#include "mt_spm.h"
|
||||
#include "mt_spm_internal.h"
|
||||
#include "mt_spm_reg.h"
|
||||
#include "mt_spm_vcorefs.h"
|
||||
#include "mt_spm_pmic_wrap.h"
|
||||
|
||||
#define VCORE_CT_ENABLE (1U << 5)
|
||||
#define SW_REQ5_INIT_VAL (6U << 12)
|
||||
#define V_VMODE_SHIFT 0
|
||||
#define VCORE_HV 105
|
||||
#define VCORE_LV 95
|
||||
#define PMIC_STEP_UV 6250
|
||||
|
||||
static const struct reg_config dvfsrc_init_configs[] = {
|
||||
/* Setup opp table */
|
||||
{ DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
|
||||
{ DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
|
||||
{ DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
|
||||
{ DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
|
||||
{ DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
|
||||
{ DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
|
||||
{ DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
|
||||
{ DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
|
||||
{ DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
|
||||
{ DVFSRC_LEVEL_LABEL_18_19, 0x00110012 },
|
||||
{ DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
|
||||
|
||||
/* Setup hw emi qos policy */
|
||||
{ DVFSRC_DDR_REQUEST, 0x00004321 },
|
||||
{ DVFSRC_DDR_REQUEST3, 0x00000065 },
|
||||
|
||||
/* Setup up for PCIe */
|
||||
{ DVFSRC_PCIE_VCORE_REQ, 0x0A298001 },
|
||||
|
||||
/* Setup up HRT QOS policy */
|
||||
{ DVFSRC_HRT_BW_BASE, 0x00000004 },
|
||||
{ DVFSRC_HRT_REQ_UNIT, 0x0000001E },
|
||||
{ DVFSRC_HRT_HIGH_3, 0x18A618A6 },
|
||||
{ DVFSRC_HRT_HIGH_2, 0x18A61183 },
|
||||
{ DVFSRC_HRT_HIGH_1, 0x0D690B80 },
|
||||
{ DVFSRC_HRT_HIGH, 0x070804B0 },
|
||||
{ DVFSRC_HRT_LOW_3, 0x18A518A5 },
|
||||
{ DVFSRC_HRT_LOW_2, 0x18A51182 },
|
||||
{ DVFSRC_HRT_LOW_1, 0x0D680B7F },
|
||||
{ DVFSRC_HRT_LOW, 0x070704AF },
|
||||
{ DVFSRC_HRT_REQUEST, 0x66654321 },
|
||||
/* Setup up SRT QOS policy */
|
||||
{ DVFSRC_QOS_EN, 0x0011007C },
|
||||
{ DVFSRC_DDR_QOS0, 0x00000019 },
|
||||
{ DVFSRC_DDR_QOS1, 0x00000026 },
|
||||
{ DVFSRC_DDR_QOS2, 0x00000033 },
|
||||
{ DVFSRC_DDR_QOS3, 0x0000003B },
|
||||
{ DVFSRC_DDR_QOS4, 0x0000004C },
|
||||
{ DVFSRC_DDR_QOS5, 0x00000066 },
|
||||
{ DVFSRC_DDR_QOS6, 0x00000066 },
|
||||
{ DVFSRC_DDR_REQUEST5, 0x54321000 },
|
||||
{ DVFSRC_DDR_REQUEST7, 0x66000000 },
|
||||
/* Setup up hifi request policy */
|
||||
{ DVFSRC_DDR_REQUEST6, 0x66543210 },
|
||||
/* Setup up hw request vcore policy */
|
||||
{ DVFSRC_VCORE_USER_REQ, 0x00010A29 },
|
||||
|
||||
/* Setup misc*/
|
||||
{ DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
|
||||
{ DVFSRC_RSRV_5, 0x00000001 },
|
||||
{ DVFSRC_INT_EN, 0x00000002 },
|
||||
/* Init opp and enable dvfsrc*/
|
||||
{ DVFSRC_CURRENT_FORCE, 0x00000001 },
|
||||
{ DVFSRC_BASIC_CONTROL, 0x0298444B },
|
||||
{ DVFSRC_BASIC_CONTROL, 0x0298054B },
|
||||
{ DVFSRC_CURRENT_FORCE, 0x00000000 },
|
||||
};
|
||||
|
||||
static struct pwr_ctrl vcorefs_ctrl = {
|
||||
.wake_src = R12_REG_CPU_WAKEUP,
|
||||
|
||||
/* default VCORE DVFS is disabled */
|
||||
.pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
|
||||
SPM_FLAG_DISABLE_VCORE_DVS |
|
||||
SPM_FLAG_DISABLE_VCORE_DFS),
|
||||
|
||||
/* Auto-gen Start */
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
.reg_wfi_op = 0,
|
||||
.reg_wfi_type = 0,
|
||||
.reg_mp0_cputop_idle_mask = 0,
|
||||
.reg_mp1_cputop_idle_mask = 0,
|
||||
.reg_mcusys_idle_mask = 0,
|
||||
.reg_md_apsrc_1_sel = 0,
|
||||
.reg_md_apsrc_0_sel = 0,
|
||||
.reg_conn_apsrc_sel = 0,
|
||||
|
||||
/* SPM_SRC_REQ */
|
||||
.reg_spm_apsrc_req = 0,
|
||||
.reg_spm_f26m_req = 0,
|
||||
.reg_spm_infra_req = 0,
|
||||
.reg_spm_vrf18_req = 0,
|
||||
.reg_spm_ddr_en_req = 1,
|
||||
.reg_spm_dvfs_req = 0,
|
||||
.reg_spm_sw_mailbox_req = 0,
|
||||
.reg_spm_sspm_mailbox_req = 0,
|
||||
.reg_spm_adsp_mailbox_req = 0,
|
||||
.reg_spm_scp_mailbox_req = 0,
|
||||
|
||||
/* SPM_SRC6_MASK */
|
||||
.reg_dpmaif_srcclkena_mask_b = 1,
|
||||
.reg_dpmaif_infra_req_mask_b = 1,
|
||||
.reg_dpmaif_apsrc_req_mask_b = 1,
|
||||
.reg_dpmaif_vrf18_req_mask_b = 1,
|
||||
.reg_dpmaif_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC_MASK */
|
||||
.reg_md_srcclkena_0_mask_b = 1,
|
||||
.reg_md_srcclkena2infra_req_0_mask_b = 0,
|
||||
.reg_md_apsrc2infra_req_0_mask_b = 1,
|
||||
.reg_md_apsrc_req_0_mask_b = 1,
|
||||
.reg_md_vrf18_req_0_mask_b = 1,
|
||||
.reg_md_ddr_en_0_mask_b = 1,
|
||||
.reg_md_srcclkena_1_mask_b = 0,
|
||||
.reg_md_srcclkena2infra_req_1_mask_b = 0,
|
||||
.reg_md_apsrc2infra_req_1_mask_b = 0,
|
||||
.reg_md_apsrc_req_1_mask_b = 0,
|
||||
.reg_md_vrf18_req_1_mask_b = 0,
|
||||
.reg_md_ddr_en_1_mask_b = 0,
|
||||
.reg_conn_srcclkena_mask_b = 1,
|
||||
.reg_conn_srcclkenb_mask_b = 0,
|
||||
.reg_conn_infra_req_mask_b = 1,
|
||||
.reg_conn_apsrc_req_mask_b = 1,
|
||||
.reg_conn_vrf18_req_mask_b = 1,
|
||||
.reg_conn_ddr_en_mask_b = 1,
|
||||
.reg_conn_vfe28_mask_b = 0,
|
||||
.reg_srcclkeni0_srcclkena_mask_b = 1,
|
||||
.reg_srcclkeni0_infra_req_mask_b = 1,
|
||||
.reg_srcclkeni1_srcclkena_mask_b = 0,
|
||||
.reg_srcclkeni1_infra_req_mask_b = 0,
|
||||
.reg_srcclkeni2_srcclkena_mask_b = 0,
|
||||
.reg_srcclkeni2_infra_req_mask_b = 0,
|
||||
.reg_infrasys_apsrc_req_mask_b = 0,
|
||||
.reg_infrasys_ddr_en_mask_b = 1,
|
||||
.reg_md32_srcclkena_mask_b = 1,
|
||||
.reg_md32_infra_req_mask_b = 1,
|
||||
.reg_md32_apsrc_req_mask_b = 1,
|
||||
.reg_md32_vrf18_req_mask_b = 1,
|
||||
.reg_md32_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC2_MASK */
|
||||
.reg_scp_srcclkena_mask_b = 1,
|
||||
.reg_scp_infra_req_mask_b = 1,
|
||||
.reg_scp_apsrc_req_mask_b = 1,
|
||||
.reg_scp_vrf18_req_mask_b = 1,
|
||||
.reg_scp_ddr_en_mask_b = 1,
|
||||
.reg_audio_dsp_srcclkena_mask_b = 1,
|
||||
.reg_audio_dsp_infra_req_mask_b = 1,
|
||||
.reg_audio_dsp_apsrc_req_mask_b = 1,
|
||||
.reg_audio_dsp_vrf18_req_mask_b = 1,
|
||||
.reg_audio_dsp_ddr_en_mask_b = 1,
|
||||
.reg_ufs_srcclkena_mask_b = 1,
|
||||
.reg_ufs_infra_req_mask_b = 1,
|
||||
.reg_ufs_apsrc_req_mask_b = 1,
|
||||
.reg_ufs_vrf18_req_mask_b = 1,
|
||||
.reg_ufs_ddr_en_mask_b = 1,
|
||||
.reg_disp0_apsrc_req_mask_b = 1,
|
||||
.reg_disp0_ddr_en_mask_b = 1,
|
||||
.reg_disp1_apsrc_req_mask_b = 1,
|
||||
.reg_disp1_ddr_en_mask_b = 1,
|
||||
.reg_gce_infra_req_mask_b = 1,
|
||||
.reg_gce_apsrc_req_mask_b = 1,
|
||||
.reg_gce_vrf18_req_mask_b = 1,
|
||||
.reg_gce_ddr_en_mask_b = 1,
|
||||
.reg_apu_srcclkena_mask_b = 1,
|
||||
.reg_apu_infra_req_mask_b = 1,
|
||||
.reg_apu_apsrc_req_mask_b = 1,
|
||||
.reg_apu_vrf18_req_mask_b = 1,
|
||||
.reg_apu_ddr_en_mask_b = 1,
|
||||
.reg_cg_check_srcclkena_mask_b = 0,
|
||||
.reg_cg_check_apsrc_req_mask_b = 0,
|
||||
.reg_cg_check_vrf18_req_mask_b = 0,
|
||||
.reg_cg_check_ddr_en_mask_b = 0,
|
||||
|
||||
/* SPM_SRC3_MASK */
|
||||
.reg_dvfsrc_event_trigger_mask_b = 1,
|
||||
.reg_sw2spm_int0_mask_b = 0,
|
||||
.reg_sw2spm_int1_mask_b = 0,
|
||||
.reg_sw2spm_int2_mask_b = 0,
|
||||
.reg_sw2spm_int3_mask_b = 0,
|
||||
.reg_sc_adsp2spm_wakeup_mask_b = 0,
|
||||
.reg_sc_sspm2spm_wakeup_mask_b = 0,
|
||||
.reg_sc_scp2spm_wakeup_mask_b = 0,
|
||||
.reg_csyspwrreq_mask = 1,
|
||||
.reg_spm_srcclkena_reserved_mask_b = 0,
|
||||
.reg_spm_infra_req_reserved_mask_b = 0,
|
||||
.reg_spm_apsrc_req_reserved_mask_b = 0,
|
||||
.reg_spm_vrf18_req_reserved_mask_b = 0,
|
||||
.reg_spm_ddr_en_reserved_mask_b = 0,
|
||||
.reg_mcupm_srcclkena_mask_b = 1,
|
||||
.reg_mcupm_infra_req_mask_b = 1,
|
||||
.reg_mcupm_apsrc_req_mask_b = 1,
|
||||
.reg_mcupm_vrf18_req_mask_b = 1,
|
||||
.reg_mcupm_ddr_en_mask_b = 1,
|
||||
.reg_msdc0_srcclkena_mask_b = 1,
|
||||
.reg_msdc0_infra_req_mask_b = 1,
|
||||
.reg_msdc0_apsrc_req_mask_b = 1,
|
||||
.reg_msdc0_vrf18_req_mask_b = 1,
|
||||
.reg_msdc0_ddr_en_mask_b = 1,
|
||||
.reg_msdc1_srcclkena_mask_b = 1,
|
||||
.reg_msdc1_infra_req_mask_b = 1,
|
||||
.reg_msdc1_apsrc_req_mask_b = 1,
|
||||
.reg_msdc1_vrf18_req_mask_b = 1,
|
||||
.reg_msdc1_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC4_MASK */
|
||||
.ccif_event_mask_b = 0xFFF,
|
||||
.reg_bak_psri_srcclkena_mask_b = 0,
|
||||
.reg_bak_psri_infra_req_mask_b = 0,
|
||||
.reg_bak_psri_apsrc_req_mask_b = 0,
|
||||
.reg_bak_psri_vrf18_req_mask_b = 0,
|
||||
.reg_bak_psri_ddr_en_mask_b = 0,
|
||||
.reg_dramc0_md32_infra_req_mask_b = 1,
|
||||
.reg_dramc0_md32_vrf18_req_mask_b = 0,
|
||||
.reg_dramc1_md32_infra_req_mask_b = 1,
|
||||
.reg_dramc1_md32_vrf18_req_mask_b = 0,
|
||||
.reg_conn_srcclkenb2pwrap_mask_b = 0,
|
||||
.reg_dramc0_md32_wakeup_mask = 1,
|
||||
.reg_dramc1_md32_wakeup_mask = 1,
|
||||
|
||||
/* SPM_SRC5_MASK */
|
||||
.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
|
||||
.reg_mcusys_merge_ddr_en_mask_b = 0x11,
|
||||
.reg_msdc2_srcclkena_mask_b = 1,
|
||||
.reg_msdc2_infra_req_mask_b = 1,
|
||||
.reg_msdc2_apsrc_req_mask_b = 1,
|
||||
.reg_msdc2_vrf18_req_mask_b = 1,
|
||||
.reg_msdc2_ddr_en_mask_b = 1,
|
||||
.reg_pcie_srcclkena_mask_b = 1,
|
||||
.reg_pcie_infra_req_mask_b = 1,
|
||||
.reg_pcie_apsrc_req_mask_b = 1,
|
||||
.reg_pcie_vrf18_req_mask_b = 1,
|
||||
.reg_pcie_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
.reg_wakeup_event_mask = 0xEFFFFFFF,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
|
||||
|
||||
/* Auto-gen End */
|
||||
};
|
||||
|
||||
struct spm_lp_scen __spm_vcorefs = {
|
||||
.pwrctrl = &vcorefs_ctrl,
|
||||
};
|
||||
|
||||
static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
|
||||
{
|
||||
if (cmd < NR_IDX_ALL) {
|
||||
mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
|
||||
} else {
|
||||
INFO("cmd out of range!\n");
|
||||
}
|
||||
}
|
||||
|
||||
void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
|
||||
{
|
||||
mmio_clrsetbits_32(SPM_DVFS_MISC, SPM_DVFS_FORCE_ENABLE_LSB,
|
||||
SPM_DVFSRC_ENABLE_LSB);
|
||||
|
||||
mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
|
||||
mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
|
||||
}
|
||||
|
||||
void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
|
||||
const struct pwr_ctrl *src_pwr_ctrl)
|
||||
{
|
||||
uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
|
||||
SPM_FLAG_DISABLE_VCORE_DFS |
|
||||
SPM_FLAG_ENABLE_VOLTAGE_BIN;
|
||||
|
||||
dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
|
||||
(src_pwr_ctrl->pcm_flags & dvfs_mask);
|
||||
|
||||
if (dest_pwr_ctrl->pcm_flags_cust > 0U) {
|
||||
dest_pwr_ctrl->pcm_flags_cust =
|
||||
(dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) |
|
||||
(src_pwr_ctrl->pcm_flags & dvfs_mask);
|
||||
}
|
||||
}
|
||||
|
||||
static void spm_go_to_vcorefs(void)
|
||||
{
|
||||
__spm_set_power_control(__spm_vcorefs.pwrctrl);
|
||||
__spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
|
||||
__spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
|
||||
__spm_send_cpu_wakeup_event();
|
||||
}
|
||||
|
||||
static void dvfsrc_init(void)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(dvfsrc_init_configs); i++) {
|
||||
mmio_write_32(dvfsrc_init_configs[i].offset,
|
||||
dvfsrc_init_configs[i].val);
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t spm_vcorefs_get_efuse_data(void)
|
||||
{
|
||||
return mmio_read_32(VCORE_VB_EFUSE);
|
||||
}
|
||||
|
||||
static uint32_t is_rising_need(void)
|
||||
{
|
||||
return ((spm_vcorefs_get_efuse_data() & 0xF) == 11U) ? 1U : 0U;
|
||||
}
|
||||
|
||||
static void spm_vcorefs_vcore_setting(uint64_t flag)
|
||||
{
|
||||
uint32_t dvfs_v_mode, dvfsrc_rsrv, i;
|
||||
uint32_t opp_uv[] = {725000U, 650000U, 600000U, 575000U};
|
||||
|
||||
dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4);
|
||||
|
||||
dvfs_v_mode = (dvfsrc_rsrv >> V_VMODE_SHIFT) & 0x3;
|
||||
|
||||
if (is_rising_need() != 0U) {
|
||||
opp_uv[2] = 625000U;
|
||||
opp_uv[3] = 600000U;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(opp_uv); i++) {
|
||||
if (dvfs_v_mode == 3U) {
|
||||
/* LV */
|
||||
opp_uv[i] = round_down((opp_uv[i] * VCORE_LV) / 100U,
|
||||
PMIC_STEP_UV);
|
||||
} else if (dvfs_v_mode == 1U) {
|
||||
/* HV */
|
||||
opp_uv[i] = round_up((opp_uv[i] * VCORE_HV) / 100U,
|
||||
PMIC_STEP_UV);
|
||||
}
|
||||
spm_vcorefs_pwarp_cmd(i, __vcore_uv_to_pmic(opp_uv[i]));
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4)
|
||||
{
|
||||
uint64_t cmd = x1;
|
||||
uint64_t spm_flags;
|
||||
|
||||
switch (cmd) {
|
||||
case VCOREFS_SMC_CMD_INIT:
|
||||
/* vcore_dvfs init + kick */
|
||||
mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL);
|
||||
spm_dvfsfw_init(0ULL, 0ULL);
|
||||
spm_vcorefs_vcore_setting(x3 & 0xF);
|
||||
spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
|
||||
if ((x2 & 0x1) > 0U) {
|
||||
spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
|
||||
}
|
||||
|
||||
if ((x2 & 0x2) > 0U) {
|
||||
spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
|
||||
}
|
||||
|
||||
if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) {
|
||||
spm_flags |= SPM_FLAG_ENABLE_VOLTAGE_BIN;
|
||||
}
|
||||
|
||||
set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags);
|
||||
spm_go_to_vcorefs();
|
||||
dvfsrc_init();
|
||||
|
||||
*x4 = 0U;
|
||||
case VCOREFS_SMC_CMD_KICK:
|
||||
mmio_write_32(DVFSRC_SW_REQ5, 0U);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0ULL;
|
||||
}
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* Copyright(C)2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_VCOREFS_H
|
||||
#define MT_SPM_VCOREFS_H
|
||||
|
||||
uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4);
|
||||
|
||||
enum vcorefs_smc_cmd {
|
||||
VCOREFS_SMC_CMD_0,
|
||||
VCOREFS_SMC_CMD_1,
|
||||
VCOREFS_SMC_CMD_2,
|
||||
VCOREFS_SMC_CMD_3,
|
||||
VCOREFS_SMC_CMD_4,
|
||||
/* check spmfw status */
|
||||
VCOREFS_SMC_CMD_5,
|
||||
|
||||
/* get spmfw type */
|
||||
VCOREFS_SMC_CMD_6,
|
||||
|
||||
/* get spm reg status */
|
||||
VCOREFS_SMC_CMD_7,
|
||||
|
||||
NUM_VCOREFS_SMC_CMD,
|
||||
};
|
||||
|
||||
enum vcorefs_smc_cmd_new {
|
||||
VCOREFS_SMC_CMD_INIT = 0,
|
||||
VCOREFS_SMC_CMD_KICK = 1,
|
||||
};
|
||||
|
||||
#define _VCORE_BASE_UV 400000
|
||||
#define _VCORE_STEP_UV 6250
|
||||
|
||||
/* PMIC */
|
||||
#define __vcore_pmic_to_uv(pmic) \
|
||||
(((pmic) * _VCORE_STEP_UV) + _VCORE_BASE_UV)
|
||||
|
||||
#define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \
|
||||
((((uv) - _VCORE_BASE_UV) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV)
|
||||
|
||||
struct reg_config {
|
||||
uint32_t offset;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
|
||||
#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
|
||||
#define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8)
|
||||
#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC)
|
||||
#define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0)
|
||||
#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4)
|
||||
#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
|
||||
#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100)
|
||||
#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104)
|
||||
#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108)
|
||||
#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C)
|
||||
#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110)
|
||||
#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114)
|
||||
#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118)
|
||||
#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C)
|
||||
#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280)
|
||||
#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294)
|
||||
#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610)
|
||||
#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614)
|
||||
#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00)
|
||||
#define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04)
|
||||
#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08)
|
||||
#define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C)
|
||||
#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10)
|
||||
#define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14)
|
||||
#define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18)
|
||||
#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34)
|
||||
#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38)
|
||||
#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C)
|
||||
#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40)
|
||||
#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44)
|
||||
#define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60)
|
||||
#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4)
|
||||
#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8)
|
||||
#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC)
|
||||
#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0)
|
||||
#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4)
|
||||
#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8)
|
||||
#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC)
|
||||
#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0)
|
||||
#define DVFSRC_LAST (DVFSRC_BASE + 0xAE4)
|
||||
#define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8)
|
||||
#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC)
|
||||
#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0)
|
||||
#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4)
|
||||
#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8)
|
||||
#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC)
|
||||
#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00)
|
||||
#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04)
|
||||
#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08)
|
||||
#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C)
|
||||
#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0)
|
||||
#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4)
|
||||
#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8)
|
||||
#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC)
|
||||
#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00)
|
||||
#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04)
|
||||
#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08)
|
||||
#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C)
|
||||
#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0)
|
||||
#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4)
|
||||
#define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8)
|
||||
#define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC)
|
||||
#define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00)
|
||||
#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04)
|
||||
#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08)
|
||||
#define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C)
|
||||
#define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10)
|
||||
#define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14)
|
||||
#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18)
|
||||
#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C)
|
||||
#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38)
|
||||
#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C)
|
||||
#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C)
|
||||
#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50)
|
||||
#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54)
|
||||
#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58)
|
||||
#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C)
|
||||
#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60)
|
||||
#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64)
|
||||
#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68)
|
||||
#define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C)
|
||||
|
||||
#define VCORE_VB_EFUSE (0x11C105E8)
|
||||
|
||||
#endif /* MT_SPM_VCOREFS_H */
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_SSPM_NOTIFIER_H
|
||||
#define MT_SPM_SSPM_NOTIFIER_H
|
||||
|
||||
enum MT_SPM_SSPM_NOTIFY_ID {
|
||||
MT_SPM_NOTIFY_LP_ENTER,
|
||||
MT_SPM_NOTIFY_LP_LEAVE,
|
||||
};
|
||||
|
||||
int mt_spm_sspm_notify(int type, unsigned int lp_mode);
|
||||
|
||||
static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode)
|
||||
{
|
||||
return mt_spm_sspm_notify(type, lp_mode);
|
||||
}
|
||||
#endif /* MT_SPM_SSPM_NOTIFIER_H */
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MT_SPM_SSPM_INTC_H
|
||||
#define MT_SPM_SSPM_INTC_H
|
||||
|
||||
#include <mt_spm_reg.h>
|
||||
|
||||
#define MT_SPM_SSPM_INTC_SEL_0 0x10
|
||||
#define MT_SPM_SSPM_INTC_SEL_1 0x20
|
||||
#define MT_SPM_SSPM_INTC_SEL_2 0x40
|
||||
#define MT_SPM_SSPM_INTC_SEL_3 0x80
|
||||
|
||||
#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
|
||||
(((0x10 << id) | (sg << id)) & 0xff)
|
||||
|
||||
#define MT_SPM_SSPM_INTC0_HIGH MT_SPM_SSPM_INTC_TRIGGER(0, 1)
|
||||
#define MT_SPM_SSPM_INTC0_LOW MT_SPM_SSPM_INTC_TRIGGER(0, 0)
|
||||
#define MT_SPM_SSPM_INTC1_HIGH MT_SPM_SSPM_INTC_TRIGGER(1, 1)
|
||||
#define MT_SPM_SSPM_INTC1_LOW MT_SPM_SSPM_INTC_TRIGGER(1, 0)
|
||||
#define MT_SPM_SSPM_INTC2_HIGH MT_SPM_SSPM_INTC_TRIGGER(2, 1)
|
||||
#define MT_SPM_SSPM_INTC2_LOW MT_SPM_SSPM_INTC_TRIGGER(2, 0)
|
||||
#define MT_SPM_SSPM_INTC3_HIGH MT_SPM_SSPM_INTC_TRIGGER(3, 1)
|
||||
#define MT_SPM_SSPM_INTC3_LOW MT_SPM_SSPM_INTC_TRIGGER(3, 0)
|
||||
|
||||
#define DO_SPM_SSPM_LP_SUSPEND() \
|
||||
mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
|
||||
#define DO_SPM_SSPM_LP_RESUME() \
|
||||
mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
|
||||
#endif /* MT_SPM_SSPM_INTC_H */
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <mt_spm_notifier.h>
|
||||
#include <mt_spm_sspm_intc.h>
|
||||
|
||||
#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x)
|
||||
#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
|
||||
|
||||
#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)
|
||||
#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1)
|
||||
#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2)
|
||||
#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3)
|
||||
|
||||
#define MCUPM_MBOX_OFFSET_LP 0x0C55FDA4
|
||||
#define MCUPM_MBOX_ENTER_LP 0x454e0000
|
||||
#define MCUPM_MBOX_LEAVE_LP 0x4c450000
|
||||
#define MCUPM_MBOX_SLEEP_MASK 0x0000FFFF
|
||||
|
||||
int mt_spm_sspm_notify(int type, unsigned int lp_mode)
|
||||
{
|
||||
switch (type) {
|
||||
case MT_SPM_NOTIFY_LP_ENTER:
|
||||
mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
|
||||
mmio_write_32(MCUPM_MBOX_OFFSET_LP, MCUPM_MBOX_ENTER_LP |
|
||||
(lp_mode & MCUPM_MBOX_SLEEP_MASK));
|
||||
DO_SPM_SSPM_LP_SUSPEND();
|
||||
break;
|
||||
case MT_SPM_NOTIFY_LP_LEAVE:
|
||||
mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
|
||||
mmio_write_32(MCUPM_MBOX_OFFSET_LP, MCUPM_MBOX_LEAVE_LP |
|
||||
(lp_mode & MCUPM_MBOX_SLEEP_MASK));
|
||||
DO_SPM_SSPM_LP_RESUME();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PCM_DEF_H
|
||||
#define PCM_DEF_H
|
||||
|
||||
/*
|
||||
* Auto generated by DE, please DO NOT modify this file directly.
|
||||
*/
|
||||
|
||||
/* --- R0 Define --- */
|
||||
#define R0_SC_26M_CK_OFF (1U << 0)
|
||||
#define R0_SC_TX_TRACK_RETRY_EN (1U << 1)
|
||||
#define R0_SC_MEM_CK_OFF (1U << 2)
|
||||
#define R0_SC_AXI_CK_OFF (1U << 3)
|
||||
#define R0_SC_DR_SRAM_LOAD (1U << 4)
|
||||
#define R0_SC_MD26M_CK_OFF (1U << 5)
|
||||
#define R0_SC_DPY_MODE_SW (1U << 6)
|
||||
#define R0_SC_DMSUS_OFF (1U << 7)
|
||||
#define R0_SC_DPY_2ND_DLL_EN (1U << 8)
|
||||
#define R0_SC_DR_SRAM_RESTORE (1U << 9)
|
||||
#define R0_SC_MPLLOUT_OFF (1U << 10)
|
||||
#define R0_SC_TX_TRACKING_DIS (1U << 11)
|
||||
#define R0_SC_DPY_DLL_EN (1U << 12)
|
||||
#define R0_SC_DPY_DLL_CK_EN (1U << 13)
|
||||
#define R0_SC_DPY_VREF_EN (1U << 14)
|
||||
#define R0_SC_PHYPLL_EN (1U << 15)
|
||||
#define R0_SC_DDRPHY_FB_CK_EN (1U << 16)
|
||||
#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
|
||||
#define R0_SC_MPLL_OFF (1U << 18)
|
||||
#define R0_SC_SHU_RESTORE (1U << 19)
|
||||
#define R0_SC_CKSQ0_OFF (1U << 20)
|
||||
#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21)
|
||||
#define R0_SC_DR_SHU_EN (1U << 22)
|
||||
#define R0_SC_DPHY_PRECAL_UP (1U << 23)
|
||||
#define R0_SC_MPLL_S_OFF (1U << 24)
|
||||
#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25)
|
||||
#define R0_SC_PHYPLL_SHU_EN (1U << 26)
|
||||
#define R0_SC_PHYPLL2_SHU_EN (1U << 27)
|
||||
#define R0_SC_PHYPLL_MODE_SW (1U << 28)
|
||||
#define R0_SC_PHYPLL2_MODE_SW (1U << 29)
|
||||
#define R0_SC_DR_SHU_LEVEL0 (1U << 30)
|
||||
#define R0_SC_DR_SHU_LEVEL1 (1U << 31)
|
||||
/* --- R7 Define --- */
|
||||
#define R7_PWRAP_SLEEP_REQ (1U << 0)
|
||||
#define R7_EMI_CLK_OFF_REQ (1U << 1)
|
||||
#define R7_PCM_BUS_PROTECT_REQ (1U << 2)
|
||||
#define R7_SPM_CK_UPDATE (1U << 3)
|
||||
#define R7_SPM_CK_SEL0 (1U << 4)
|
||||
#define R7_SPM_CK_SEL1 (1U << 5)
|
||||
#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6)
|
||||
#define R7_SC_FHC_PAUSE_MPLL (1U << 7)
|
||||
#define R7_SC_26M_CK_SEL (1U << 8)
|
||||
#define R7_PCM_TIMER_SET (1U << 9)
|
||||
#define R7_PCM_TIMER_CLR (1U << 10)
|
||||
#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11)
|
||||
#define R7_CSYSPWRUPACK (1U << 12)
|
||||
#define R7_PCM_IM_SLP_EN (1U << 13)
|
||||
#define R7_SRCCLKENO0 (1U << 14)
|
||||
#define R7_FORCE_DDR_EN_WAKE (1U << 15)
|
||||
#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16)
|
||||
#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
|
||||
#define R7_SC_AXI_DCM_DIS (1U << 18)
|
||||
#define R7_SC_FHC_PAUSE_MEM (1U << 19)
|
||||
#define R7_SC_FHC_PAUSE_MAIN (1U << 20)
|
||||
#define R7_SRCCLKENO1 (1U << 21)
|
||||
#define R7_PCM_WDT_KICK_P (1U << 22)
|
||||
#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23)
|
||||
#define R7_SC_DDR_PST_REQ_PCM (1U << 24)
|
||||
#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25)
|
||||
#define R7_PMIC_IRQ_REQ_EN (1U << 26)
|
||||
#define R7_FORCE_F26M_WAKE (1U << 27)
|
||||
#define R7_FORCE_APSRC_WAKE (1U << 28)
|
||||
#define R7_FORCE_INFRA_WAKE (1U << 29)
|
||||
#define R7_FORCE_VRF18_WAKE (1U << 30)
|
||||
#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31)
|
||||
/* --- R12 Define --- */
|
||||
#define R12_PCM_TIMER (1U << 0)
|
||||
#define R12_TWAM_IRQ_B (1U << 1)
|
||||
#define R12_KP_IRQ_B (1U << 2)
|
||||
#define R12_APWDT_EVENT_B (1U << 3)
|
||||
#define R12_APXGPT1_EVENT_B (1U << 4)
|
||||
#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5)
|
||||
#define R12_EINT_EVENT_B (1U << 6)
|
||||
#define R12_CONN_WDT_IRQ_B (1U << 7)
|
||||
#define R12_CCIF0_EVENT_B (1U << 8)
|
||||
#define R12_LOWBATTERY_IRQ_B (1U << 9)
|
||||
#define R12_SSPM2SPM_WAKEUP_B (1U << 10)
|
||||
#define R12_SCP2SPM_WAKEUP_B (1U << 11)
|
||||
#define R12_ADSP2SPM_WAKEUP_B (1U << 12)
|
||||
#define R12_PCM_WDT_WAKEUP_B (1U << 13)
|
||||
#define R12_USBX_CDSC_B (1U << 14)
|
||||
#define R12_USBX_POWERDWN_B (1U << 15)
|
||||
#define R12_SYS_TIMER_EVENT_B (1U << 16)
|
||||
#define R12_EINT_EVENT_SECURE_B (1U << 17)
|
||||
#define R12_CCIF1_EVENT_B (1U << 18)
|
||||
#define R12_UART0_IRQ_B (1U << 19)
|
||||
#define R12_AFE_IRQ_MCU_B (1U << 20)
|
||||
#define R12_THERM_CTRL_EVENT_B (1U << 21)
|
||||
#define R12_SYS_CIRQ_IRQ_B (1U << 22)
|
||||
#define R12_MD2AP_PEER_EVENT_B (1U << 23)
|
||||
#define R12_CSYSPWREQ_B (1U << 24)
|
||||
#define R12_MD1_WDT_B (1U << 25)
|
||||
#define R12_CLDMA_EVENT_B (1U << 26)
|
||||
#define R12_SEJ_EVENT_B (1U << 27)
|
||||
#define R12_REG_CPU_WAKEUP (1U << 28)
|
||||
#define R12_APUSYS_WAKE_HOST_B (1U << 29)
|
||||
#define R12_PCIE_BRIDGE_IRQ (1U << 30)
|
||||
#define R12_PCIE_IRQ (1U << 31)
|
||||
/* --- R12ext Define --- */
|
||||
#define R12EXT_26M_WAKE (1U << 0)
|
||||
#define R12EXT_26M_SLEEP (1U << 1)
|
||||
#define R12EXT_INFRA_WAKE (1U << 2)
|
||||
#define R12EXT_INFRA_SLEEP (1U << 3)
|
||||
#define R12EXT_APSRC_WAKE (1U << 4)
|
||||
#define R12EXT_APSRC_SLEEP (1U << 5)
|
||||
#define R12EXT_VRF18_WAKE (1U << 6)
|
||||
#define R12EXT_VRF18_SLEEP (1U << 7)
|
||||
#define R12EXT_DVFS_WAKE (1U << 8)
|
||||
#define R12EXT_DDREN_WAKE (1U << 9)
|
||||
#define R12EXT_DDREN_SLEEP (1U << 10)
|
||||
#define R12EXT_MCU_PM_WFI (1U << 11)
|
||||
#define R12EXT_SSPM_IDLE (1U << 12)
|
||||
#define R12EXT_CONN_SRCCLKENB (1U << 13)
|
||||
#define R12EXT_DRAMC_SSPM_WFI_MERGE (1U << 14)
|
||||
#define R12EXT_SW_MAILBOX_WAKE (1U << 15)
|
||||
#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16)
|
||||
#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17)
|
||||
#define R12EXT_SCP_MAILBOX_WAKE (1U << 18)
|
||||
#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19)
|
||||
#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20)
|
||||
#define R12EXT_VS1_TRIGGER (1U << 21)
|
||||
#define R12EXT_VS2_TRIGGER (1U << 22)
|
||||
#define R12EXT_COROSS_REQ_APU (1U << 23)
|
||||
#define R12EXT_CROSS_REQ_L3 (1U << 24)
|
||||
#define R12EXT_DDR_PST_ACK (1U << 25)
|
||||
#define R12EXT_BIT26 (1U << 26)
|
||||
#define R12EXT_BIT27 (1U << 27)
|
||||
#define R12EXT_BIT28 (1U << 28)
|
||||
#define R12EXT_BIT29 (1U << 29)
|
||||
#define R12EXT_BIT30 (1U << 30)
|
||||
#define R12EXT_BIT31 (1U << 31)
|
||||
/* --- R13 Define --- */
|
||||
#define R13_SRCCLKENI0 (1U << 0)
|
||||
#define R13_SRCCLKENI1 (1U << 1)
|
||||
#define R13_MD_SRCCLKENA_0 (1U << 2)
|
||||
#define R13_MD_APSRC_REQ_0 (1U << 3)
|
||||
#define R13_CONN_DDR_EN (1U << 4)
|
||||
#define R13_MD_SRCCLKENA_1 (1U << 5)
|
||||
#define R13_SSPM_SRCCLKENA (1U << 6)
|
||||
#define R13_SSPM_APSRC_REQ (1U << 7)
|
||||
#define R13_MD1_STATE (1U << 8)
|
||||
#define R13_BIT9 (1U << 9)
|
||||
#define R13_MM_STATE (1U << 10)
|
||||
#define R13_SSPM_STATE (1U << 11)
|
||||
#define R13_MD_DDR_EN_0 (1U << 12)
|
||||
#define R13_CONN_STATE (1U << 13)
|
||||
#define R13_CONN_SRCCLKENA (1U << 14)
|
||||
#define R13_CONN_APSRC_REQ (1U << 15)
|
||||
#define R13_SC_DDR_PST_ACK_ALL (1U << 16)
|
||||
#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17)
|
||||
#define R13_SCP_STATE (1U << 18)
|
||||
#define R13_CSYSPWRUPREQ (1U << 19)
|
||||
#define R13_PWRAP_SLEEP_ACK (1U << 20)
|
||||
#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21)
|
||||
#define R13_AUDIO_DSP_STATE (1U << 22)
|
||||
#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23)
|
||||
#define R13_CONN_SRCCLKENB (1U << 24)
|
||||
#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25)
|
||||
#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26)
|
||||
#define R13_DVFS_STATE (1U << 27)
|
||||
#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28)
|
||||
#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29)
|
||||
#define R13_MD_VRF18_REQ_0 (1U << 30)
|
||||
#define R13_DDR_EN_STATE (1U << 31)
|
||||
#endif /* PCM_DEF_H */
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SLEEP_DEF_H
|
||||
#define SLEEP_DEF_H
|
||||
|
||||
/*
|
||||
* Auto generated by DE, please DO NOT modify this file directly.
|
||||
*/
|
||||
|
||||
/* --- SPM Flag Define --- */
|
||||
#define SPM_FLAG_DISABLE_CPU_PDN (1U << 0)
|
||||
#define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1)
|
||||
#define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2)
|
||||
#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
|
||||
#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
|
||||
#define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5)
|
||||
#define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6)
|
||||
#define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7)
|
||||
#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8)
|
||||
#define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9)
|
||||
#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
|
||||
#define SPM_FLAG_RESERVED_BIT11 (1U << 11)
|
||||
#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12)
|
||||
#define SPM_FLAG_USE_SRCCLKENO2 (1U << 13)
|
||||
#define SPM_FLAG_ENABLE_6315_CTRL (1U << 14)
|
||||
#define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15)
|
||||
#define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16)
|
||||
#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17)
|
||||
#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18)
|
||||
#define SPM_FLAG_ENABLE_MD_MUMTAS (1U << 19)
|
||||
#define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20)
|
||||
#define SPM_FLAG_RESERVED_BIT21 (1U << 21)
|
||||
#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
|
||||
#define SPM_FLAG_DISABLE_SRAM_EVENT (1U << 23)
|
||||
#define SPM_FLAG_RESERVED_BIT24 (1U << 24)
|
||||
#define SPM_FLAG_RESERVED_BIT25 (1U << 25)
|
||||
#define SPM_FLAG_RESERVED_BIT26 (1U << 26)
|
||||
#define SPM_FLAG_VTCXO_STATE (1U << 27)
|
||||
#define SPM_FLAG_INFRA_STATE (1U << 28)
|
||||
#define SPM_FLAG_APSRC_STATE (1U << 29)
|
||||
#define SPM_FLAG_VRF18_STATE (1U << 30)
|
||||
#define SPM_FLAG_DDREN_STATE (1U << 31)
|
||||
/* --- SPM Flag1 Define --- */
|
||||
#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0)
|
||||
#define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1)
|
||||
#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2)
|
||||
#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3)
|
||||
#define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4)
|
||||
#define SPM_FLAG1_RESERVED_BIT5 (1U << 5)
|
||||
#define SPM_FLAG1_ENABLE_REKICK (1U << 6)
|
||||
#define SPM_FLAG1_DISABLE_MD26M_CK_OFF (1U << 7)
|
||||
#define SPM_FLAG1_RESERVED_BIT8 (1U << 8)
|
||||
#define SPM_FLAG1_RESERVED_BIT9 (1U << 9)
|
||||
#define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10)
|
||||
#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11)
|
||||
#define SPM_FLAG1_RESERVED_BIT12 (1U << 12)
|
||||
#define SPM_FLAG1_RESERVED_BIT13 (1U << 13)
|
||||
#define SPM_FLAG1_RESERVED_BIT14 (1U << 14)
|
||||
#define SPM_FLAG1_RESERVED_BIT15 (1U << 15)
|
||||
#define SPM_FLAG1_RESERVED_BIT16 (1U << 16)
|
||||
#define SPM_FLAG1_RESERVED_BIT17 (1U << 17)
|
||||
#define SPM_FLAG1_RESERVED_BIT18 (1U << 18)
|
||||
#define SPM_FLAG1_RESERVED_BIT19 (1U << 19)
|
||||
#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20)
|
||||
#define SPM_FLAG1_RESERVED_BIT21 (1U << 21)
|
||||
#define SPM_FLAG1_ENABLE_VS1_VOTER (1U << 22)
|
||||
#define SPM_FLAG1_ENABLE_VS2_VOTER (1U << 23)
|
||||
#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24)
|
||||
#define SPM_FLAG1_RESERVED_BIT25 (1U << 25)
|
||||
#define SPM_FLAG1_RESERVED_BIT26 (1U << 26)
|
||||
#define SPM_FLAG1_RESERVED_BIT27 (1U << 27)
|
||||
#define SPM_FLAG1_RESERVED_BIT28 (1U << 28)
|
||||
#define SPM_FLAG1_RESERVED_BIT29 (1U << 29)
|
||||
#define SPM_FLAG1_RESERVED_BIT30 (1U << 30)
|
||||
#define SPM_FLAG1_DISABLE_CPUEB_OFF (1U << 31)
|
||||
/* --- SPM DEBUG Define --- */
|
||||
#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0)
|
||||
#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1)
|
||||
#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2)
|
||||
#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3)
|
||||
#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4)
|
||||
#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5)
|
||||
#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6)
|
||||
#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7)
|
||||
#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8)
|
||||
#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9)
|
||||
#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10)
|
||||
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11)
|
||||
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12)
|
||||
#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13)
|
||||
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14)
|
||||
#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15)
|
||||
#define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16)
|
||||
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17)
|
||||
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18)
|
||||
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19)
|
||||
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20)
|
||||
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21)
|
||||
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22)
|
||||
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V (1U << 23)
|
||||
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V (1U << 24)
|
||||
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V (1U << 25)
|
||||
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V (1U << 26)
|
||||
#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27)
|
||||
#define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28)
|
||||
#define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29)
|
||||
#define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30)
|
||||
#define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31)
|
||||
/* --- SPM DEBUG1 Define --- */
|
||||
#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0)
|
||||
#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1)
|
||||
#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2)
|
||||
#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3)
|
||||
#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4)
|
||||
#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5)
|
||||
#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6)
|
||||
#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7)
|
||||
#define SPM_DBG1_RESERVED_BIT8 (1U << 8)
|
||||
#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF (1U << 9)
|
||||
#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON (1U << 10)
|
||||
#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11)
|
||||
#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12)
|
||||
#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13)
|
||||
#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14)
|
||||
#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15)
|
||||
#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16)
|
||||
#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17)
|
||||
#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18)
|
||||
#define SPM_DBG1_RESERVED_BIT19 (1U << 19)
|
||||
#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20)
|
||||
#define SPM_DBG1_DEBUG_IDX_6315_LOW (1U << 21)
|
||||
#define SPM_DBG1_DEBUG_IDX_6315_HIGH (1U << 22)
|
||||
#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23)
|
||||
#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24)
|
||||
#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25)
|
||||
#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26)
|
||||
#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27)
|
||||
#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28)
|
||||
#define SPM_DBG1_RESERVED_BIT29 (1U << 29)
|
||||
#define SPM_DBG1_RESERVED_BIT30 (1U << 30)
|
||||
#define SPM_DBG1_DEBUG_DISABLE_CPUEB_OFF (1U << 31)
|
||||
|
||||
/* Macro and Inline */
|
||||
#define is_cpu_pdn(flags) (((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
|
||||
#define is_infra_pdn(flags) (((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
|
||||
#define is_ddrphy_pdn(flags) (((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
|
||||
#endif /* SLEEP_DEF_H */
|
|
@ -10,7 +10,7 @@
|
|||
#include <lib/psci/psci.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define MT_IRQ_REMAIN_MAX U(8)
|
||||
#define MT_IRQ_REMAIN_MAX U(32)
|
||||
#define MT_IRQ_REMAIN_CAT_LOG BIT(31)
|
||||
|
||||
struct mt_irqremain {
|
||||
|
|
|
@ -26,12 +26,16 @@
|
|||
#define MTK_MCDI_SRAM_BASE 0x11B000
|
||||
#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
|
||||
|
||||
#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
|
||||
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
|
||||
#define GPIO_BASE (IO_PHYS + 0x00005000)
|
||||
#define SPM_BASE (IO_PHYS + 0x00006000)
|
||||
#define APMIXEDSYS (IO_PHYS + 0x0000C000)
|
||||
#define DVFSRC_BASE (IO_PHYS + 0x00012000)
|
||||
#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
|
||||
#define EMI_BASE (IO_PHYS + 0x00219000)
|
||||
#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
|
||||
#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
|
||||
#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
|
||||
#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
|
||||
#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
|
||||
|
@ -41,6 +45,7 @@
|
|||
#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
|
||||
#define IOCFG_LT_BASE (IO_PHYS + 0x01F20000)
|
||||
#define IOCFG_TL_BASE (IO_PHYS + 0x01F30000)
|
||||
#define MMSYS_BASE (IO_PHYS + 0x04000000)
|
||||
/*******************************************************************************
|
||||
* UART related constants
|
||||
******************************************************************************/
|
||||
|
|
|
@ -87,11 +87,6 @@ static void plat_cpu_pwron_common(unsigned int cpu,
|
|||
|
||||
coordinate_cluster_pwron();
|
||||
|
||||
/* Enable the GIC CPU interface */
|
||||
gicv3_rdistif_on(cpu);
|
||||
gicv3_cpuif_enable(cpu);
|
||||
mt_gic_rdistif_init();
|
||||
|
||||
/*
|
||||
* If mcusys does power down before then restore
|
||||
* all CPUs' GIC Redistributors
|
||||
|
@ -99,6 +94,9 @@ static void plat_cpu_pwron_common(unsigned int cpu,
|
|||
if (IS_MCUSYS_OFF_STATE(state)) {
|
||||
mt_gic_rdistif_restore_all();
|
||||
} else {
|
||||
gicv3_rdistif_on(cpu);
|
||||
gicv3_cpuif_enable(cpu);
|
||||
mt_gic_rdistif_init();
|
||||
mt_gic_rdistif_restore();
|
||||
}
|
||||
|
||||
|
|
|
@ -6,6 +6,9 @@
|
|||
|
||||
#include <common/debug.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <mtk_sip_svc.h>
|
||||
#include <mt_spm_vcorefs.h>
|
||||
#include "plat_sip_calls.h"
|
||||
|
||||
uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
|
@ -16,8 +19,14 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
|
|||
void *handle,
|
||||
u_register_t flags)
|
||||
{
|
||||
uint64_t ret;
|
||||
|
||||
switch (smc_fid) {
|
||||
case MTK_SIP_VCORE_CONTROL_ARCH32:
|
||||
case MTK_SIP_VCORE_CONTROL_ARCH64:
|
||||
ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
|
||||
SMC_RET2(handle, ret, x4);
|
||||
break;
|
||||
default:
|
||||
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
|
||||
break;
|
||||
|
|
|
@ -8,6 +8,7 @@ MTK_PLAT := plat/mediatek
|
|||
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
|
||||
|
||||
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
|
||||
-I${MTK_PLAT}/common/lpm/ \
|
||||
-I${MTK_PLAT_SOC}/include/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/dcm \
|
||||
|
@ -42,6 +43,7 @@ BL31_SOURCES += common/desc_image_load.c \
|
|||
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
|
||||
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
|
||||
${MTK_PLAT}/common/drivers/uart/uart.c \
|
||||
${MTK_PLAT}/common/lpm/mt_lp_rm.c \
|
||||
${MTK_PLAT}/common/mtk_plat_common.c \
|
||||
${MTK_PLAT}/common/mtk_sip_svc.c \
|
||||
${MTK_PLAT}/common/params_setup.c \
|
||||
|
@ -61,11 +63,15 @@ BL31_SOURCES += common/desc_image_load.c \
|
|||
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
|
||||
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
|
||||
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
|
||||
${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \
|
||||
${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
|
||||
${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \
|
||||
${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
|
||||
${MTK_PLAT_SOC}/drivers/timer/mt_timer.c
|
||||
|
||||
# Build SPM drivers
|
||||
include ${MTK_PLAT_SOC}/drivers/spm/build.mk
|
||||
|
||||
# Configs for A76 and A55
|
||||
HW_ASSISTED_COHERENCY := 1
|
||||
USE_COHERENT_MEM := 0
|
||||
|
|
Loading…
Reference in New Issue