From 10007118a2a0a99e6630001455df8757eb9bc8f9 Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Thu, 28 Jul 2016 13:54:29 -0700 Subject: [PATCH 01/14] Tegra186: mce: clear reserved fields for ARI calls This patch clears the unused or reserved ARI input registers before issuing the actual ARI command. Change-Id: I454b86566bfe088049a5c63527c1323d7b25248a Signed-off-by: Krishna Sitaraman Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t186/drivers/mce/ari.c | 48 ++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c index e11d16000..116864536 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c @@ -129,6 +129,9 @@ int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) return EINVAL; } + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* Enter the cstate, to be woken up after wake_time (TSC ticks) */ return ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT, TEGRA_ARI_ENTER_CSTATE, state, wake_time); @@ -140,6 +143,9 @@ int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, { uint32_t val = 0; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* update CLUSTER_CSTATE? */ if (cluster) val |= (cluster & CLUSTER_CSTATE_MASK) | @@ -172,6 +178,9 @@ int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) (type > TEGRA_ARI_CROSSOVER_CCP3_SC1)) return EINVAL; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* update crossover threshold time */ return ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CROSSOVER, type, time); @@ -185,6 +194,9 @@ uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state) if (state == 0) return EINVAL; + /* clean the previous response state */ + ari_clobber_response(ari_base); + ret = ari_request_wait(ari_base, 0, TEGRA_ARI_CSTATE_STATS, state, 0); if (ret != 0) return EINVAL; @@ -194,6 +206,9 @@ uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state) int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* write the cstate stats */ return ari_request_wait(ari_base, 0, TEGRA_ARI_WRITE_CSTATE_STATS, state, stats); @@ -226,6 +241,9 @@ int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) { int ret; + /* clean the previous response state */ + ari_clobber_response(ari_base); + ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7, wake_time); if (ret) { @@ -248,6 +266,9 @@ int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) return EINVAL; } + /* clean the previous response state */ + ari_clobber_response(ari_base); + ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_SC7_ALLOWED, state, wake_time); if (ret) { @@ -283,6 +304,9 @@ int ari_online_core(uint32_t ari_base, uint32_t core) return EINVAL; } + /* clean the previous response state */ + ari_clobber_response(ari_base); + return ari_request_wait(ari_base, 0, TEGRA_ARI_ONLINE_CORE, core, 0); } @@ -290,6 +314,9 @@ int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable { int val; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* * If the enable bit is cleared, Auto-CC3 will be disabled by setting * the SW visible voltage/frequency request registers for all non @@ -309,6 +336,9 @@ int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* * Need to program the CPU reset vector one time during cold boot * and SC7 exit @@ -320,18 +350,27 @@ int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi) int ari_roc_flush_cache_trbits(uint32_t ari_base) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS, 0, 0); } int ari_roc_flush_cache(uint32_t ari_base) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY, 0, 0); } int ari_roc_clean_cache(uint32_t ari_base) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY, 0, 0); } @@ -372,6 +411,9 @@ int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx) if (gsc_idx > TEGRA_ARI_GSC_VPR_IDX) return EINVAL; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* * The MCE code will read the GSC carveout value, corrseponding to * the ID, from the MC registers and update the internal GSC registers @@ -384,6 +426,9 @@ int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx) void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx) { + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* * The MCE will shutdown or restart the entire system */ @@ -396,6 +441,9 @@ int ari_read_write_uncore_perfmon(uint32_t ari_base, int ret; uint32_t val; + /* clean the previous response state */ + ari_clobber_response(ari_base); + /* sanity check input parameters */ if (req.perfmon_command.cmd == UNCORE_PERFMON_CMD_READ && !data) { ERROR("invalid parameters\n"); From 6ef90b96383e5aaa31fe64353d1d557c8425f99f Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Wed, 27 Jul 2016 16:26:45 -0700 Subject: [PATCH 02/14] Tegra186: mce: fix return value for enum features ari This patch fixes the incorrect return value that was being passed back for the ENUM_FEATURES ARI call. Change-Id: I3842c6ce27ea24698608830cf4c12cfa7ff64421 Signed-off-by: Krishna Sitaraman Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t186/drivers/mce/mce.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c index f87dfa4d3..afd45278b 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c @@ -307,14 +307,12 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, break; case MCE_CMD_ENUM_FEATURES: - ret = ops->call_enum_misc(cpu_ari_base, + ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0); /* update context to return features value */ write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); - ret = 0; - break; case MCE_CMD_ROC_FLUSH_CACHE_TRBITS: From 719f3ec242e671cf012b2e88f7a9ab3cfa063c91 Mon Sep 17 00:00:00 2001 From: Harvey Hsieh Date: Fri, 29 Jul 2016 20:10:59 +0800 Subject: [PATCH 03/14] Tegra: memctrl_v2: save TZDRAM settings to secure scratch registers Save TZDRAM settings for SC7 resume firmware to restore. SECURITY_BOM: MC_SECURITY_CFG0_0 = SECURE_RSV55_SCRATCH_0 SECURITY_BOM_HI: MC_SECURITY_CFG3_0 = SECURE_RSV55_SCRATCH_1 SECURITY_SIZE_MB: MC_SECURITY_CFG1_0 = SECURE_RSV54_SCRATCH_1 Change-Id: I78e891d9ebf576ff2a17ff87cf3aff4030ee11b8 Signed-off-by: Harvey Hsieh Signed-off-by: Varun Wadekar --- .../tegra/common/drivers/memctrl/memctrl_v2.c | 14 ++++++++++++++ plat/nvidia/tegra/include/t186/tegra_def.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index bd16b9916..3b662a699 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -622,6 +622,20 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); + /* + * When TZ encryption enabled, + * We need setup TZDRAM before CPU to access TZ Carveout, + * otherwise CPU will fetch non-decrypted data. + * So save TZDRAM setting for retore by SC7 resume FW. + */ + + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, + tegra_mc_read_32(MC_SECURITY_CFG0_0)); + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, + tegra_mc_read_32(MC_SECURITY_CFG3_0)); + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI, + tegra_mc_read_32(MC_SECURITY_CFG1_0)); + /* * MCE propogates the security configuration values across the * CCPLEX. diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index e0eddfd34..a394a7239 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -148,6 +148,9 @@ #define SECURE_SCRATCH_RSV11_HI 0x6AC #define SECURE_SCRATCH_RSV53_LO 0x7F8 #define SECURE_SCRATCH_RSV53_HI 0x7FC +#define SECURE_SCRATCH_RSV54_HI 0x804 +#define SECURE_SCRATCH_RSV55_LO 0x808 +#define SECURE_SCRATCH_RSV55_HI 0x80C /******************************************************************************* * Tegra Memory Mapped Control Register Access Bus constants From 53451898a1f5f5f64b6c397b2b0dad0b2e7a091c Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Tue, 19 Jul 2016 16:36:13 -0700 Subject: [PATCH 04/14] Tegra186: Add smc handler for coresight clock gating This change adds function to invoke for MISC_CCPLEX ARI calls and the corresponding smc handler. This can be used to enable/disable Coresight clock gating. Change-Id: I4bc17aa478a46c29bfe17fd74f839a383ee2b644 Signed-off-by: Krishna Sitaraman Signed-off-by: Varun Wadekar --- .../tegra/soc/t186/drivers/include/mce.h | 42 +++++++++++-------- plat/nvidia/tegra/soc/t186/drivers/mce/ari.c | 19 +++++++++ plat/nvidia/tegra/soc/t186/drivers/mce/mce.c | 11 ++++- plat/nvidia/tegra/soc/t186/plat_sip_calls.c | 2 + 4 files changed, 55 insertions(+), 19 deletions(-) diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h index 66e212bff..56e8afb89 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h @@ -79,23 +79,24 @@ typedef enum mce_core_id { ******************************************************************************/ typedef enum mce_cmd { MCE_CMD_ENTER_CSTATE = 0, - MCE_CMD_UPDATE_CSTATE_INFO, - MCE_CMD_UPDATE_CROSSOVER_TIME, - MCE_CMD_READ_CSTATE_STATS, - MCE_CMD_WRITE_CSTATE_STATS, - MCE_CMD_IS_SC7_ALLOWED, - MCE_CMD_ONLINE_CORE, - MCE_CMD_CC3_CTRL, - MCE_CMD_ECHO_DATA, - MCE_CMD_READ_VERSIONS, - MCE_CMD_ENUM_FEATURES, - MCE_CMD_ROC_FLUSH_CACHE_TRBITS, - MCE_CMD_ENUM_READ_MCA, - MCE_CMD_ENUM_WRITE_MCA, - MCE_CMD_ROC_FLUSH_CACHE, - MCE_CMD_ROC_CLEAN_CACHE, - MCE_CMD_ENABLE_LATIC, - MCE_CMD_UNCORE_PERFMON_REQ, + MCE_CMD_UPDATE_CSTATE_INFO = 1, + MCE_CMD_UPDATE_CROSSOVER_TIME = 2, + MCE_CMD_READ_CSTATE_STATS = 3, + MCE_CMD_WRITE_CSTATE_STATS = 4, + MCE_CMD_IS_SC7_ALLOWED = 5, + MCE_CMD_ONLINE_CORE = 6, + MCE_CMD_CC3_CTRL = 7, + MCE_CMD_ECHO_DATA = 8, + MCE_CMD_READ_VERSIONS = 9, + MCE_CMD_ENUM_FEATURES = 10, + MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11, + MCE_CMD_ENUM_READ_MCA = 12, + MCE_CMD_ENUM_WRITE_MCA = 13, + MCE_CMD_ROC_FLUSH_CACHE = 14, + MCE_CMD_ROC_CLEAN_CACHE = 15, + MCE_CMD_ENABLE_LATIC = 16, + MCE_CMD_UNCORE_PERFMON_REQ = 17, + MCE_CMD_MISC_CCPLEX = 18, MCE_CMD_IS_CCX_ALLOWED = 0xFE, MCE_CMD_MAX = 0xFF, } mce_cmd_t; @@ -386,6 +387,12 @@ typedef struct arch_mce_ops { */ int (*read_write_uncore_perfmon)(uint32_t ari_base, uncore_perfmon_req_t req, uint64_t *data); + /* + * This ARI implements ARI_MISC_CCPLEX commands. This can be + * used to enable/disable coresight clock gating. + */ + void (*misc_ccplex)(uint32_t ari_base, uint32_t index, + uint32_t value); } arch_mce_ops_t; int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, @@ -420,6 +427,7 @@ int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); int ari_read_write_uncore_perfmon(uint32_t ari_base, uncore_perfmon_req_t req, uint64_t *data); +void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c index 116864536..8d2a2b262 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c @@ -475,3 +475,22 @@ int ari_read_write_uncore_perfmon(uint32_t ari_base, return (int)req.perfmon_status.val; } + +void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value) +{ + /* + * This invokes the ARI_MISC_CCPLEX commands. This can be + * used to enable/disable coresight clock gating. + */ + + if ((index > TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) || + ((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) && + (value > 1))) { + ERROR("%s: invalid parameters \n", __func__); + return; + } + + /* clean the previous response state */ + ari_clobber_response(ari_base); + (void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, index, value); +} diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c index afd45278b..f953b2efa 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c @@ -63,7 +63,8 @@ static arch_mce_ops_t nvg_mce_ops = { .read_write_mca = ari_read_write_mca, .update_ccplex_gsc = ari_update_ccplex_gsc, .enter_ccplex_state = ari_enter_ccplex_state, - .read_write_uncore_perfmon = ari_read_write_uncore_perfmon + .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, + .misc_ccplex = ari_misc_ccplex }; /* ARI functions handlers */ @@ -85,7 +86,8 @@ static arch_mce_ops_t ari_mce_ops = { .read_write_mca = ari_read_write_mca, .update_ccplex_gsc = ari_update_ccplex_gsc, .enter_ccplex_state = ari_enter_ccplex_state, - .read_write_uncore_perfmon = ari_read_write_uncore_perfmon + .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, + .misc_ccplex = ari_misc_ccplex }; typedef struct mce_config { @@ -385,6 +387,11 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, write_ctx_reg(gp_regs, CTX_GPREG_X1, arg1); break; + case MCE_CMD_MISC_CCPLEX: + ops->misc_ccplex(cpu_ari_base, arg0, arg1); + + break; + default: ERROR("unknown MCE command (%d)\n", cmd); return EINVAL; diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c index 8e3371845..31e903eba 100644 --- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c @@ -66,6 +66,7 @@ extern uint32_t tegra186_system_powerdn_state; #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10 #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11 +#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12 /******************************************************************************* * This function is responsible for handling all T186 SiP calls @@ -104,6 +105,7 @@ int plat_sip_handler(uint32_t smc_fid, case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: + case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: /* clean up the high bits */ smc_fid &= MCE_CMD_MASK; From 25621454d53a18bd516c7f35b94266fa7aeca7bb Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 8 Aug 2016 11:53:14 -0700 Subject: [PATCH 05/14] Tegra186: trampoline: update "System Suspend" exit criteria The TZRAM memory loses its state during "System Suspend". This patch check if TZRAM base address contains valid data, to decide if the system is exiting from "System Suspend". To enable TZDRAM encryption, the Memory Controller's TZDRAM base/size registers would be populated by the BPMP when the system "wakes up". Change-Id: I5fc8ba1ae3bce12f0ece493f6f9f5f4d92a46344 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t186/plat_trampoline.S | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S index 7619ed0c9..21393d9b9 100644 --- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S @@ -42,18 +42,14 @@ /* CPU reset handler routine */ func tegra186_cpu_reset_handler /* - * The Memory Controller loses state during System Suspend. We - * use this information to decide if the reset handler is running - * after a System Suspend. Resume from system suspend requires - * restoring the entire state from TZDRAM to TZRAM. + * The TZRAM loses state during System Suspend. We use this + * information to decide if the reset handler is running after a + * System Suspend. Resume from system suspend requires restoring + * the entire state from TZDRAM to TZRAM. */ - mov x1, #TEGRA_MC_BASE - ldr w0, [x1, #MC_SECURITY_CFG3_0] - lsl x0, x0, #32 - ldr w0, [x1, #MC_SECURITY_CFG0_0] - adr x1, tegra186_cpu_reset_handler - cmp x0, x1 - beq boot_cpu + mov x0, #BL31_BASE + ldr x0, [x0] + cbnz x0, boot_cpu /* resume from system suspend */ mov x0, #BL31_BASE From ac26b96b40c4cda751f1923b4906d7027e529327 Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Thu, 28 Jul 2016 13:56:36 -0700 Subject: [PATCH 06/14] Tegra186: update t18x_ari.h to v3.0 This patch updates the ARI header to version 3.0 Change-Id: I7cfe0c61c80a6b78625232135dd63393602d32fe Signed-off-by: Krishna Sitaraman Signed-off-by: Varun Wadekar --- .../tegra/soc/t186/drivers/include/t18x_ari.h | 62 +++++++++---------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h index 3e6054bd0..cb48de62f 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h @@ -40,8 +40,8 @@ */ enum { - TEGRA_ARI_VERSION_MAJOR = 2, - TEGRA_ARI_VERSION_MINOR = 19, + TEGRA_ARI_VERSION_MAJOR = 3, + TEGRA_ARI_VERSION_MINOR = 0, }; typedef enum { @@ -107,15 +107,15 @@ typedef enum { typedef enum { TEGRA_ARI_CCPLEX_CCP0 = 0, TEGRA_ARI_CCPLEX_CCP1 = 1, - TEGRA_ARI_CCPLEX_CCP3 = 3, + TEGRA_ARI_CCPLEX_CCP3 = 3, /* obsoleted */ } tegra_ari_ccplex_sleep_state_t; typedef enum { TEGRA_ARI_SYSTEM_SC0 = 0, - TEGRA_ARI_SYSTEM_SC1 = 1, - TEGRA_ARI_SYSTEM_SC2 = 2, - TEGRA_ARI_SYSTEM_SC3 = 3, - TEGRA_ARI_SYSTEM_SC4 = 4, + TEGRA_ARI_SYSTEM_SC1 = 1, /* obsoleted */ + TEGRA_ARI_SYSTEM_SC2 = 2, /* obsoleted */ + TEGRA_ARI_SYSTEM_SC3 = 3, /* obsoleted */ + TEGRA_ARI_SYSTEM_SC4 = 4, /* obsoleted */ TEGRA_ARI_SYSTEM_SC7 = 7, TEGRA_ARI_SYSTEM_SC8 = 8, } tegra_ari_system_sleep_state_t; @@ -124,21 +124,22 @@ typedef enum { TEGRA_ARI_CROSSOVER_C1_C6 = 0, TEGRA_ARI_CROSSOVER_CC1_CC6 = 1, TEGRA_ARI_CROSSOVER_CC1_CC7 = 2, - TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3, - TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4, - TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5, - TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6, - TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7, - TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8, + TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7, /* obsoleted */ + TEGRA_ARI_CROSSOVER_SC0_SC7 = 7, + TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8, /* obsoleted */ } tegra_ari_crossover_index_t; typedef enum { TEGRA_ARI_CSTATE_STATS_CLEAR = 0, - TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES = 1, - TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, - TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, - TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, - TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, + TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES, + TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, /* obsoleted */ + TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, /* obsoleted */ + TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, /* obsoleted */ + TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, /* obsoleted */ TEGRA_ARI_CSTATE_STATS_A57_CC6_ENTRIES, TEGRA_ARI_CSTATE_STATS_A57_CC7_ENTRIES, TEGRA_ARI_CSTATE_STATS_D15_CC6_ENTRIES, @@ -403,17 +404,18 @@ typedef enum { TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5, TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6, TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12, + TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_SC0_SC7 = 12, TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13, TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14, - TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15, - TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16, - TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17, - TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18, + TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15, /* obsoleted */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16, /* obsoleted */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17, /* obsoleted */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18, /* obsoleted */ TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19, TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20, TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21, @@ -432,7 +434,7 @@ typedef enum { TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34, TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35, TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36, - TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /* Reserved (for Denver15 core 2) */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /* Reserved (for Denver15 core 2) */ TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38, /* Reserved (for Denver15 core 3) */ TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39, TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40, @@ -441,10 +443,8 @@ typedef enum { TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, TEGRA_NVG_CHANNEL_CC3_CTRL = 45, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46, + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46, /* obsoleted */ TEGRA_NVG_CHANNEL_LAST_INDEX, } tegra_nvg_channel_id_t; #endif /* T18X_TEGRA_ARI_H */ - - From 322b00fcfb6e8b1b5aa533c9503955c0bfdf826b Mon Sep 17 00:00:00 2001 From: Mustafa Yigit Bilgen Date: Fri, 2 Sep 2016 19:30:22 -0700 Subject: [PATCH 07/14] Tegra186: clean CPU wake times from L2 cache When entering C7, ATF disables caches and flushes the L1 cache. However, wake_time[cpu] can still remain in the L2 cache, causing later reads to it to fetch from DRAM. This will read stale values. Fix this by aligning wake_time[cpu] to cache lines, and explicitly cleaning it before disabling caches. Change-Id: Id73d095b479677595a6b3dd0abb240a1fef5f311 Signed-off-by: Mustafa Yigit Bilgen Signed-off-by: Varun Wadekar --- .../tegra/soc/t186/plat_psci_handlers.c | 21 +++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 358287870..8485e0445 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -63,7 +63,9 @@ extern uint32_t __tegra186_cpu_reset_handler_data, #define TEGRA186_SE_CONTEXT_SIZE 3 static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; -static unsigned int wake_time[PLATFORM_CORE_COUNT]; +static struct t18x_psci_percpu_data { + unsigned int wake_time; +} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; /* System power down state */ uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; @@ -75,9 +77,19 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, int cpu = plat_my_core_pos(); /* save the core wake time (us) */ - wake_time[cpu] = (power_state >> TEGRA186_WAKE_TIME_SHIFT) & + percpu_data[cpu].wake_time = (power_state >> TEGRA186_WAKE_TIME_SHIFT) & TEGRA186_WAKE_TIME_MASK; + /* + * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that + * the correct value is read in tegra_soc_pwr_domain_suspend(), which + * is called with caches disabled. It is possible to read a stale value + * from DRAM in that function, because the L2 cache is not flushed + * unless the cluster is entering CC6/CC7. + */ + clean_dcache_range((uint64_t)&percpu_data[cpu], + sizeof(percpu_data[cpu])); + /* Sanity check the requested state id */ switch (state_id) { case PSTATE_ID_CORE_IDLE: @@ -121,7 +133,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7; (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, - wake_time[cpu], 0); + percpu_data[cpu].wake_time, 0); } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { @@ -193,7 +205,8 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, /* Check if CCx state is allowed. */ ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, - TEGRA_ARI_CORE_C7, wake_time[cpu], 0); + TEGRA_ARI_CORE_C7, percpu_data[cpu].wake_time, + 0); if (ret) return PSTATE_ID_CORE_POWERDN; } From a259293ebee927cd661746c2dd890c8c283091a8 Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Fri, 2 Sep 2016 16:53:04 -0700 Subject: [PATCH 08/14] Tegra186: Update API for reset vector ARI The TEGRA_ARI_COPY_MISCREG_AA64_RST ARI should be called with request_lo/hi set to zero. MTS automatically takes the reset vector from MISCREG_AA64_RST register and does not need it to be passed as parameters. This patch updates the API and the caller function accordingly. Change-Id: Ie3e3402d93951102239d988ca9f0cdf94f290d2f Signed-off-by: Krishna Sitaraman Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t186/drivers/include/mce.h | 8 +++----- plat/nvidia/tegra/soc/t186/drivers/mce/ari.c | 4 ++-- plat/nvidia/tegra/soc/t186/drivers/mce/mce.c | 4 ++-- plat/nvidia/tegra/soc/t186/plat_secondary.c | 2 +- 4 files changed, 8 insertions(+), 10 deletions(-) diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h index 56e8afb89..61ca5ebe8 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h @@ -338,9 +338,7 @@ typedef struct arch_mce_ops { * This ARI request allows updating the reset vector register for * D15 and A57 CPUs. */ - int (*update_reset_vector)(uint32_t ari_base, - uint32_t addr_low, - uint32_t addr_high); + int (*update_reset_vector)(uint32_t ari_base); /* * This ARI request instructs the ROC to flush A57 data caches in * order to maintain coherency with the Denver cluster. @@ -397,7 +395,7 @@ typedef struct arch_mce_ops { int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, uint64_t arg2); -int mce_update_reset_vector(uint32_t addr_lo, uint32_t addr_hi); +int mce_update_reset_vector(void); int mce_update_gsc_videomem(void); int mce_update_gsc_tzdram(void); int mce_update_gsc_tzram(void); @@ -418,7 +416,7 @@ int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); int ari_online_core(uint32_t ari_base, uint32_t core); int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); -int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi); +int ari_reset_vector_update(uint32_t ari_base); int ari_roc_flush_cache_trbits(uint32_t ari_base); int ari_roc_flush_cache(uint32_t ari_base); int ari_roc_clean_cache(uint32_t ari_base); diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c index 8d2a2b262..7597c12b6 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c @@ -334,7 +334,7 @@ int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable return ari_request_wait(ari_base, 0, TEGRA_ARI_CC3_CTRL, val, 0); } -int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi) +int ari_reset_vector_update(uint32_t ari_base) { /* clean the previous response state */ ari_clobber_response(ari_base); @@ -343,7 +343,7 @@ int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi) * Need to program the CPU reset vector one time during cold boot * and SC7 exit */ - ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, lo, hi); + ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0, 0); return 0; } diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c index f953b2efa..3a0edfb9e 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c @@ -403,11 +403,11 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, /******************************************************************************* * Handler to update the reset vector for CPUs ******************************************************************************/ -int mce_update_reset_vector(uint32_t addr_lo, uint32_t addr_hi) +int mce_update_reset_vector(void) { arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); - ops->update_reset_vector(mce_get_curr_cpu_ari_base(), addr_lo, addr_hi); + ops->update_reset_vector(mce_get_curr_cpu_ari_base()); return 0; } diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c index 406c1e08d..6576db110 100644 --- a/plat/nvidia/tegra/soc/t186/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c @@ -91,5 +91,5 @@ void plat_secondary_setup(void) addr_high); /* update reset vector address to the CCPLEX */ - mce_update_reset_vector(addr_low, addr_high); + mce_update_reset_vector(); } From 5ea1fe569df5c4d8ca4a2ab9ea9b572e2fd3959b Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Thu, 18 Aug 2016 15:41:21 -0700 Subject: [PATCH 09/14] Tegra186: use MSB of wake_time This patch updates wake time of the cpu to use the MSBs and zero out the LSB's. Only 24 out of 32 bits are currently passed through the PSCI interface. Previously all the LSB's were used. Change-Id: Ie2d9d1bf6e3003dd47526a124f64e6ad555d2371 Signed-off-by: Krishna Sitaraman Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t186/plat_psci_handlers.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 8485e0445..a170b9947 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -55,7 +55,7 @@ extern uint32_t __tegra186_cpu_reset_handler_data, /* state id mask */ #define TEGRA186_STATE_ID_MASK 0xF /* constants to get power state's wake time */ -#define TEGRA186_WAKE_TIME_MASK 0xFFFFFF +#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 #define TEGRA186_WAKE_TIME_SHIFT 4 /* default core wake mask for CPU_SUSPEND */ #define TEGRA186_CORE_WAKE_MASK 0x180c @@ -76,9 +76,9 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; int cpu = plat_my_core_pos(); - /* save the core wake time (us) */ - percpu_data[cpu].wake_time = (power_state >> TEGRA186_WAKE_TIME_SHIFT) & - TEGRA186_WAKE_TIME_MASK; + /* save the core wake time (in TSC ticks)*/ + percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) + << TEGRA186_WAKE_TIME_SHIFT; /* * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that From 396a9b8feec656308b7c3a9a3e6cefaa846497a5 Mon Sep 17 00:00:00 2001 From: Vivek Aseeja Date: Mon, 22 Aug 2016 13:44:08 -0700 Subject: [PATCH 10/14] Tegra186: memctrl_v2: remove APE overrides for chip verification This patch reverts the APE overrides added for chip verification. Change-Id: Ib85560934d63f6e41e95ef6898a341f24761a517 Signed-off-by: Vivek Aseeja Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index 3b662a699..a2474a03b 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -195,17 +195,10 @@ const static mc_streamid_security_cfg_t sec_cfgs[] = { mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE), -#if ENABLE_CHIP_VERIFICATION_HARNESS - mc_make_sec_cfg(APEDMAW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(APER, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(APEW, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(APEDMAR, NON_SECURE, OVERRIDE, ENABLE), -#else mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), -#endif }; const static mc_txn_override_cfg_t mc_override_cfgs[] = { From d81938ab3a56d5e75ab9c43f9f496f438700854f Mon Sep 17 00:00:00 2001 From: Mustafa Yigit Bilgen Date: Thu, 17 Nov 2016 15:08:39 -0800 Subject: [PATCH 11/14] Tegra: memctrl_v2: no SID override for AON Remove stream ID overrides for AON. AON drives its own stream ID when accesing IOVA memory. However, it needs to use a physical stream ID when accesing GSC memory. Overriding stream ids prevents AON from accessing GSC memory, so remove them to allow AON to access GSCs. Change-Id: Ia2b11014d9780c4546b5e781621ae4cd413735cc Signed-off-by: Mustafa Yigit Bilgen Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index a2474a03b..fb57b2b74 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -136,7 +136,7 @@ const static mc_streamid_security_cfg_t sec_cfgs[] = { mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(AONDMAW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), @@ -178,8 +178,8 @@ const static mc_streamid_security_cfg_t sec_cfgs[] = { mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), - mc_make_sec_cfg(AONDMAR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(AONW, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), @@ -188,7 +188,7 @@ const static mc_streamid_security_cfg_t sec_cfgs[] = { mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), - mc_make_sec_cfg(AONR, NON_SECURE, OVERRIDE, ENABLE), + mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE), From dec349c87d99ec91ef3b00aa14a937a1fe237703 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 12 Dec 2016 14:24:17 -0800 Subject: [PATCH 12/14] Tegra186: move platform specific MCE defines to tegra_def.h This patch moves the MCE's configurable parameters to tegra_def.h for the Tegra186 SoC, to allow forward compatiblity. Change-Id: If8660c1c09908a4064dbb67d5ca4fb78389cab13 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/t186/tegra_def.h | 30 ++++++++++++++ .../tegra/soc/t186/drivers/include/mce.h | 40 ------------------- 2 files changed, 30 insertions(+), 40 deletions(-) diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index a394a7239..b5a8ab38d 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -31,6 +31,36 @@ #ifndef __TEGRA_DEF_H__ #define __TEGRA_DEF_H__ +/******************************************************************************* + * MCE apertures used by the ARI interface + * + * Aperture 0 - Cpu0 (ARM Cortex A-57) + * Aperture 1 - Cpu1 (ARM Cortex A-57) + * Aperture 2 - Cpu2 (ARM Cortex A-57) + * Aperture 3 - Cpu3 (ARM Cortex A-57) + * Aperture 4 - Cpu4 (Denver15) + * Aperture 5 - Cpu5 (Denver15) + ******************************************************************************/ +#define MCE_ARI_APERTURE_0_OFFSET 0x0 +#define MCE_ARI_APERTURE_1_OFFSET 0x10000 +#define MCE_ARI_APERTURE_2_OFFSET 0x20000 +#define MCE_ARI_APERTURE_3_OFFSET 0x30000 +#define MCE_ARI_APERTURE_4_OFFSET 0x40000 +#define MCE_ARI_APERTURE_5_OFFSET 0x50000 +#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET + +/* number of apertures */ +#define MCE_ARI_APERTURES_MAX 6 + +/* each ARI aperture is 64KB */ +#define MCE_ARI_APERTURE_SIZE 0x10000 + +/******************************************************************************* + * CPU core id macros for the MCE_ONLINE_CORE ARI + ******************************************************************************/ +#define MCE_CORE_ID_MAX 8 +#define MCE_CORE_ID_MASK 0x7 + /******************************************************************************* * These values are used by the PSCI implementation during the `CPU_SUSPEND` * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h index 61ca5ebe8..441a2c1b7 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h @@ -34,46 +34,6 @@ #include #include -/******************************************************************************* - * MCE apertures used by the ARI interface - * - * Aperture 0 - Cpu0 (ARM Cortex A-57) - * Aperture 1 - Cpu1 (ARM Cortex A-57) - * Aperture 2 - Cpu2 (ARM Cortex A-57) - * Aperture 3 - Cpu3 (ARM Cortex A-57) - * Aperture 4 - Cpu4 (Denver15) - * Aperture 5 - Cpu5 (Denver15) - ******************************************************************************/ -#define MCE_ARI_APERTURE_0_OFFSET 0x0 -#define MCE_ARI_APERTURE_1_OFFSET 0x10000 -#define MCE_ARI_APERTURE_2_OFFSET 0x20000 -#define MCE_ARI_APERTURE_3_OFFSET 0x30000 -#define MCE_ARI_APERTURE_4_OFFSET 0x40000 -#define MCE_ARI_APERTURE_5_OFFSET 0x50000 -#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET - -/* number of apertures */ -#define MCE_ARI_APERTURES_MAX 6 - -/* each ARI aperture is 64KB */ -#define MCE_ARI_APERTURE_SIZE 0x10000 - -/******************************************************************************* - * CPU core ids - used by the MCE_ONLINE_CORE ARI - ******************************************************************************/ -typedef enum mce_core_id { - MCE_CORE_ID_DENVER_15_0, - MCE_CORE_ID_DENVER_15_1, - /* 2 and 3 are reserved */ - MCE_CORE_ID_A57_0 = 4, - MCE_CORE_ID_A57_1, - MCE_CORE_ID_A57_2, - MCE_CORE_ID_A57_3, - MCE_CORE_ID_MAX -} mce_core_id_t; - -#define MCE_CORE_ID_MASK 0x7 - /******************************************************************************* * MCE commands ******************************************************************************/ From 0258840e42d0d842e989835aca5b85f417d330ef Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 12 Dec 2016 16:14:57 -0800 Subject: [PATCH 13/14] Tegra: drivers: memctrl: move chip specific defines to tegra_def.h This patch moves the chip specific memory controller driver defines to the appropriate tegra_def.h files, for future compatibility. Change-Id: I3179fb771d8b32e913ca29bd94af95f4b2fc1961 Signed-off-by: Varun Wadekar --- .../tegra/common/drivers/memctrl/memctrl_v1.c | 9 ++-- .../nvidia/tegra/include/drivers/memctrl_v1.h | 8 ---- .../nvidia/tegra/include/drivers/memctrl_v2.h | 45 ------------------- plat/nvidia/tegra/include/t132/tegra_def.h | 10 +++++ plat/nvidia/tegra/include/t186/tegra_def.h | 39 ++++++++++++++++ plat/nvidia/tegra/include/t210/tegra_def.h | 10 +++++ 6 files changed, 65 insertions(+), 56 deletions(-) diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c index c4170504c..859ecd53e 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c @@ -43,7 +43,7 @@ #define GPU_RESET_BIT (1 << 24) /* Video Memory base and size (live values) */ -static uintptr_t video_mem_base; +static uint64_t video_mem_base; static uint64_t video_mem_size; /* @@ -85,7 +85,9 @@ void tegra_memctrl_setup(void) (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ /* video memory carveout */ - tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, + (uint32_t)(video_mem_base >> 32)); + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base); tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); } @@ -208,7 +210,8 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) enable_mmu_el3(0); done: - tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32)); + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); /* store new values */ diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v1.h b/plat/nvidia/tegra/include/drivers/memctrl_v1.h index e44a9ea92..b504594bf 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v1.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v1.h @@ -60,14 +60,6 @@ #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 #define MC_SMMU_TRANSLATION_ENABLE (~0) -/* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 - -/* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c - static inline uint32_t tegra_mc_read_32(uint32_t off) { return mmio_read_32(TEGRA_MC_BASE + off); diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h index e1abe1434..8b12dcd03 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h @@ -352,51 +352,6 @@ typedef struct mc_streamid_security_cfg { #endif /* __ASSEMBLY__ */ -/******************************************************************************* - * TZDRAM carveout configuration registers - ******************************************************************************/ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 -#define MC_SECURITY_CFG3_0 0x9BC - -/******************************************************************************* - * Video Memory carveout configuration registers - ******************************************************************************/ -#define MC_VIDEO_PROTECT_BASE_HI 0x978 -#define MC_VIDEO_PROTECT_BASE_LO 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c - -/******************************************************************************* - * TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers - ******************************************************************************/ -#define MC_TZRAM_BASE_LO 0x2194 -#define TZRAM_BASE_LO_SHIFT 12 -#define TZRAM_BASE_LO_MASK 0xFFFFF -#define MC_TZRAM_BASE_HI 0x2198 -#define TZRAM_BASE_HI_SHIFT 0 -#define TZRAM_BASE_HI_MASK 3 -#define MC_TZRAM_SIZE 0x219C -#define TZRAM_SIZE_RANGE_4KB_SHIFT 27 - -#define MC_TZRAM_CARVEOUT_CFG 0x2190 -#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) -#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 -#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) -#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 - -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC - /******************************************************************************* * Memory Controller Reset Control registers ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index 314b70071..4ba4f12c5 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -104,6 +104,16 @@ ******************************************************************************/ #define TEGRA_MC_BASE 0x70019000 +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 +#define MC_SECURITY_CFG3_0 0x9BC + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE_HI 0x978 +#define MC_VIDEO_PROTECT_BASE_LO 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index b5a8ab38d..01da884f7 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -120,6 +120,45 @@ #define TEGRA_MC_STREAMID_BASE 0x02C00000 #define TEGRA_MC_BASE 0x02C10000 +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 +#define MC_SECURITY_CFG3_0 0x9BC + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE_HI 0x978 +#define MC_VIDEO_PROTECT_BASE_LO 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + +/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ +#define MC_TZRAM_BASE_LO 0x2194 +#define TZRAM_BASE_LO_SHIFT 12 +#define TZRAM_BASE_LO_MASK 0xFFFFF +#define MC_TZRAM_BASE_HI 0x2198 +#define TZRAM_BASE_HI_SHIFT 0 +#define TZRAM_BASE_HI_MASK 3 +#define MC_TZRAM_SIZE 0x219C +#define TZRAM_SIZE_RANGE_4KB_SHIFT 27 + +#define MC_TZRAM_CARVEOUT_CFG 0x2190 +#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) +#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 +#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) +#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 +#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 + +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8 +#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC + /******************************************************************************* * Tegra UART Controller constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index d24377da3..096135514 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -129,6 +129,16 @@ ******************************************************************************/ #define TEGRA_MC_BASE 0x70019000 +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 +#define MC_SECURITY_CFG3_0 0x9BC + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE_HI 0x978 +#define MC_VIDEO_PROTECT_BASE_LO 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ From 2dd7d41a2b62a655fe0126e8408baf9e99a62e69 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 15 Dec 2016 11:54:51 -0800 Subject: [PATCH 14/14] Tegra186: move TSA macros to tegra_def.h This patch moves the TSA block's macros from memctrl_v2.h to tegra_def.h in the Tegra186 tree. Change-Id: I8b45dd3905c5d1f33ffb36d8b2de72aeb06674aa Signed-off-by: Varun Wadekar --- .../nvidia/tegra/include/drivers/memctrl_v2.h | 37 ------------------- plat/nvidia/tegra/include/t186/tegra_def.h | 37 +++++++++++++++++++ 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h index 8b12dcd03..559ea2c59 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h @@ -392,43 +392,6 @@ typedef struct mc_streamid_security_cfg { #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1 << 24) #define MC_CLIENT_HOTRESET_STATUS1 0x974 -/******************************************************************************* - * TSA configuration registers - ******************************************************************************/ -#define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 -#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 -#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 -#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 -#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 -#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 -#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 -#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 -#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 -#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 -#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 -#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 -#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 -#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 -#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 -#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 -#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 - -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) - /******************************************************************************* * Memory Controller's PCFIFO client configuration registers ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index 01da884f7..6bac0d714 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -114,6 +114,43 @@ ******************************************************************************/ #define TEGRA_TSA_BASE 0x02400000 +/******************************************************************************* + * TSA configuration registers + ******************************************************************************/ +#define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 +#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 +#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 +#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 +#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 +#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 +#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 +#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 +#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 +#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 +#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 +#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 + +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) + /******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/