Tegra: organize memory/mmio apertures to decrease memmap latency
This patch organizes the memory and mmio maps linearly, to make the mmap_add_region process faster. The microsecond timer has been moved to individual platforms instead of making it a common step, as it further speeds up the memory map creation process. Change-Id: I6fdaee392f7ac5d99daa182380ca9116a001f5d6 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -404,6 +404,14 @@ void bl31_plat_arch_setup(void)
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*/
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*/
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boot_profiler_add_record("[TF] arch setup entry");
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boot_profiler_add_record("[TF] arch setup entry");
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/* add MMIO space */
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plat_mmio_map = plat_get_mmio_map();
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if (plat_mmio_map != NULL) {
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mmap_add(plat_mmio_map);
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} else {
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WARN("MMIO map not available\n");
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}
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/* add memory regions */
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/* add memory regions */
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mmap_add_region(rw_start, rw_start,
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mmap_add_region(rw_start, rw_start,
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rw_size,
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rw_size,
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@ -415,14 +423,6 @@ void bl31_plat_arch_setup(void)
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code_size,
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code_size,
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MT_CODE | MT_SECURE);
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MT_CODE | MT_SECURE);
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/* map TZDRAM used by BL31 as coherent memory */
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if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
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mmap_add_region(params_from_bl2->tzdram_base,
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params_from_bl2->tzdram_base,
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BL31_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE);
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}
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#if USE_COHERENT_MEM
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#if USE_COHERENT_MEM
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coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
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coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
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coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
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coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
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@ -432,18 +432,12 @@ void bl31_plat_arch_setup(void)
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
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#endif
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#endif
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/* map on-chip free running uS timer */
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/* map TZDRAM used by BL31 as coherent memory */
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mmap_add_region(page_align(TEGRA_TMRUS_BASE, 0),
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if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
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page_align(TEGRA_TMRUS_BASE, 0),
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mmap_add_region(params_from_bl2->tzdram_base,
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TEGRA_TMRUS_SIZE,
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params_from_bl2->tzdram_base,
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(uint8_t)MT_DEVICE | (uint8_t)MT_RO | (uint8_t)MT_SECURE);
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BL31_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE);
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/* add MMIO space */
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plat_mmio_map = plat_get_mmio_map();
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if (plat_mmio_map != NULL) {
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mmap_add(plat_mmio_map);
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} else {
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WARN("MMIO map not available\n");
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}
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}
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/* set up translation tables */
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/* set up translation tables */
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@ -91,6 +91,8 @@ static const mmap_region_t tegra_mmap[] = {
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MT_DEVICE | MT_RW | MT_SECURE),
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
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MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
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MT_DEVICE | MT_RO | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
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MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
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MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
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