Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware
This patch adds the driver to communicate with the BPMP firmware on Tegra SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/ disable requests, module resets among other things. MRQ is short for Message ReQuest. This is the general purpose, multi channel messaging protocol that is widely used to communicate with BPMP. This is further divided into a common high level protocol and a peer-specific low level protocol. The higher level protocol specifies the peer identification, channel definition and allocation, message structure, message semantics and message dispatch process whereas the lower level protocol defines actual message transfer implementation details. Currently, BPMP supports two lower level protocols - Token Mail Operations (TMO), IVC Mail Operations (IMO). This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM Communication) protocol which is a lockless, shared memory messaging queue management protocol. The IVC peer is expected to perform the following as part of establishing a connection with BPMP. 1. Initialize the channels with tegra_ivc_init() or its equivalent. 2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that BPMP is notified via the doorbell. 3. Poll until the channel connection is established [tegra_ivc_channel_notified() return 0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return non zero. The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In future, more hardware blocks would be supported. Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
01da3bd2db
commit
26e2b93a85
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <bpmp_ipc.h>
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#include <debug.h>
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#include <delay_timer.h>
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#include <errno.h>
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#include <mmio.h>
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#include <stdbool.h>
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#include <string.h>
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#include <tegra_def.h>
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#include <utils_def.h>
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#include "intf.h"
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#include "ivc.h"
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/**
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* Holds IVC channel data
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*/
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struct ccplex_bpmp_channel_data {
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/* Buffer for incoming data */
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struct frame_data *ib;
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/* Buffer for outgoing data */
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struct frame_data *ob;
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};
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static struct ccplex_bpmp_channel_data s_channel;
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static struct ivc ivc_ccplex_bpmp_channel;
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/*
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* Helper functions to access the HSP doorbell registers
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*/
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static inline uint32_t hsp_db_read(uint32_t reg)
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{
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return mmio_read_32((uint32_t)(TEGRA_HSP_DBELL_BASE + reg));
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}
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static inline void hsp_db_write(uint32_t reg, uint32_t val)
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{
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mmio_write_32((uint32_t)(TEGRA_HSP_DBELL_BASE + reg), val);
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}
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/*******************************************************************************
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* IVC wrappers for CCPLEX <-> BPMP communication.
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******************************************************************************/
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static void tegra_bpmp_ring_bpmp_doorbell(void);
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/*
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* Get the next frame where data can be written.
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*/
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static struct frame_data *tegra_bpmp_get_next_out_frame(void)
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{
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struct frame_data *frame;
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const struct ivc *ch = &ivc_ccplex_bpmp_channel;
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frame = (struct frame_data *)tegra_ivc_write_get_next_frame(ch);
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if (frame == NULL) {
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ERROR("%s: Error in getting next frame, exiting\n", __func__);
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} else {
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s_channel.ob = frame;
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}
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return frame;
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}
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static void tegra_bpmp_signal_slave(void)
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{
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(void)tegra_ivc_write_advance(&ivc_ccplex_bpmp_channel);
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tegra_bpmp_ring_bpmp_doorbell();
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}
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static int32_t tegra_bpmp_free_master(void)
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{
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return tegra_ivc_read_advance(&ivc_ccplex_bpmp_channel);
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}
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static bool tegra_bpmp_slave_acked(void)
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{
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struct frame_data *frame;
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bool ret = true;
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frame = (struct frame_data *)tegra_ivc_read_get_next_frame(&ivc_ccplex_bpmp_channel);
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if (frame == NULL) {
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ret = false;
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} else {
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s_channel.ib = frame;
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}
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return ret;
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}
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static struct frame_data *tegra_bpmp_get_cur_in_frame(void)
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{
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return s_channel.ib;
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}
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/*
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* Enables BPMP to ring CCPlex doorbell
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*/
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static void tegra_bpmp_enable_ccplex_doorbell(void)
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{
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uint32_t reg;
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reg = hsp_db_read(HSP_DBELL_1_ENABLE);
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reg |= HSP_MASTER_BPMP_BIT;
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hsp_db_write(HSP_DBELL_1_ENABLE, reg);
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}
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/*
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* CCPlex rings the BPMP doorbell
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*/
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static void tegra_bpmp_ring_bpmp_doorbell(void)
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{
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/*
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* Any writes to this register has the same effect,
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* uses master ID of the write transaction and set
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* corresponding flag.
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*/
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hsp_db_write(HSP_DBELL_3_TRIGGER, HSP_MASTER_CCPLEX_BIT);
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}
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/*
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* Returns true if CCPLex can ring BPMP doorbell, otherwise false.
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* This also signals that BPMP is up and ready.
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*/
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static bool tegra_bpmp_can_ccplex_ring_doorbell(void)
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{
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uint32_t reg;
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/* check if ccplex can communicate with bpmp */
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reg = hsp_db_read(HSP_DBELL_3_ENABLE);
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return ((reg & HSP_MASTER_CCPLEX_BIT) != 0U);
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}
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static int32_t tegra_bpmp_wait_for_slave_ack(void)
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{
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uint32_t timeout = TIMEOUT_RESPONSE_FROM_BPMP_US;
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while (!tegra_bpmp_slave_acked() && (timeout != 0U)) {
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udelay(1);
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timeout--;
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};
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return ((timeout == 0U) ? -ETIMEDOUT : 0);
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}
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/*
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* Notification from the ivc layer
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*/
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static void tegra_bpmp_ivc_notify(const struct ivc *ivc)
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{
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(void)(ivc);
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tegra_bpmp_ring_bpmp_doorbell();
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}
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/*
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* Atomic send/receive API, which means it waits until slave acks
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*/
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static int32_t tegra_bpmp_ipc_send_req_atomic(uint32_t mrq, void *p_out,
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uint32_t size_out, void *p_in, uint32_t size_in)
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{
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struct frame_data *frame = tegra_bpmp_get_next_out_frame();
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const struct frame_data *f_in = NULL;
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int32_t ret = 0;
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void *p_fdata;
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if ((p_out == NULL) || (size_out > IVC_DATA_SZ_BYTES) ||
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(frame == NULL)) {
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ERROR("%s: invalid parameters, exiting\n", __func__);
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ret = -EINVAL;
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}
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if (ret == 0) {
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/* prepare the command frame */
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frame->mrq = mrq;
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frame->flags = FLAG_DO_ACK;
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p_fdata = frame->data;
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(void)memcpy(p_fdata, p_out, (size_t)size_out);
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/* signal the slave */
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tegra_bpmp_signal_slave();
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/* wait for slave to ack */
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ret = tegra_bpmp_wait_for_slave_ack();
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if (ret != 0) {
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ERROR("failed waiting for the slave to ack\n");
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}
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/* retrieve the response frame */
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if ((size_in <= IVC_DATA_SZ_BYTES) && (p_in != NULL) &&
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(ret == 0)) {
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f_in = tegra_bpmp_get_cur_in_frame();
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if (f_in != NULL) {
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ERROR("Failed to get next input frame!\n");
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} else {
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(void)memcpy(p_in, p_fdata, (size_t)size_in);
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}
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}
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if (ret == 0) {
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ret = tegra_bpmp_free_master();
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if (ret != 0) {
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ERROR("Failed to free master\n");
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}
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}
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}
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return ret;
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}
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/*
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* Initializes the BPMP<--->CCPlex communication path.
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*/
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int32_t tegra_bpmp_ipc_init(void)
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{
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size_t msg_size;
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uint32_t frame_size, timeout;
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int32_t error = 0;
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/* allow bpmp to ring CCPLEX's doorbell */
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tegra_bpmp_enable_ccplex_doorbell();
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/* wait for BPMP to actually ring the doorbell */
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timeout = TIMEOUT_RESPONSE_FROM_BPMP_US;
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while ((timeout != 0U) && !tegra_bpmp_can_ccplex_ring_doorbell()) {
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udelay(1); /* bpmp turn-around time */
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timeout--;
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}
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if (timeout == 0U) {
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ERROR("%s: BPMP firmware is not ready\n", __func__);
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return -ENOTSUP;
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}
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INFO("%s: BPMP handshake completed\n", __func__);
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msg_size = tegra_ivc_align(IVC_CMD_SZ_BYTES);
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frame_size = (uint32_t)tegra_ivc_total_queue_size(msg_size);
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if (frame_size > TEGRA_BPMP_IPC_CH_MAP_SIZE) {
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ERROR("%s: carveout size is not sufficient\n", __func__);
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return -EINVAL;
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}
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error = tegra_ivc_init(&ivc_ccplex_bpmp_channel,
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(uint32_t)TEGRA_BPMP_IPC_RX_PHYS_BASE,
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(uint32_t)TEGRA_BPMP_IPC_TX_PHYS_BASE,
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1U, frame_size, tegra_bpmp_ivc_notify);
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if (error != 0) {
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ERROR("%s: IVC init failed (%d)\n", __func__, error);
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} else {
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/* reset channel */
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tegra_ivc_channel_reset(&ivc_ccplex_bpmp_channel);
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/* wait for notification from BPMP */
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while (tegra_ivc_channel_notified(&ivc_ccplex_bpmp_channel) != 0) {
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/*
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* Interrupt BPMP with doorbell each time after
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* tegra_ivc_channel_notified() returns non zero
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* value.
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*/
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tegra_bpmp_ring_bpmp_doorbell();
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}
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INFO("%s: All communication channels initialized\n", __func__);
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}
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return error;
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}
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/* Handler to reset a hardware module */
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int32_t tegra_bpmp_ipc_reset_module(uint32_t rst_id)
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{
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int32_t ret;
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struct mrq_reset_request req = {
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.cmd = (uint32_t)CMD_RESET_MODULE,
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.reset_id = rst_id
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};
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/* only GPCDMA/XUSB_PADCTL resets are supported */
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assert((rst_id == TEGRA_RESET_ID_XUSB_PADCTL) ||
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(rst_id == TEGRA_RESET_ID_GPCDMA));
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ret = tegra_bpmp_ipc_send_req_atomic(MRQ_RESET, &req,
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(uint32_t)sizeof(req), NULL, 0);
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if (ret != 0) {
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ERROR("%s: failed for module %d with error %d\n", __func__,
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rst_id, ret);
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}
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return ret;
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}
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef INTF_H
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#define INTF_H
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/**
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* Flags used in IPC req
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*/
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#define FLAG_DO_ACK (U(1) << 0)
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#define FLAG_RING_DOORBELL (U(1) << 1)
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/* Bit 1 is designated for CCPlex in secure world */
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#define HSP_MASTER_CCPLEX_BIT (U(1) << 1)
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/* Bit 19 is designated for BPMP in non-secure world */
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#define HSP_MASTER_BPMP_BIT (U(1) << 19)
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/* Timeout to receive response from BPMP is 1 sec */
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#define TIMEOUT_RESPONSE_FROM_BPMP_US U(1000000) /* in microseconds */
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/**
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* IVC protocol defines and command/response frame
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*/
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/**
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* IVC specific defines
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*/
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#define IVC_CMD_SZ_BYTES U(128)
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#define IVC_DATA_SZ_BYTES U(120)
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/**
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* Holds frame data for an IPC request
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*/
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struct frame_data {
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/* Identification as to what kind of data is being transmitted */
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uint32_t mrq;
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/* Flags for slave as to how to respond back */
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uint32_t flags;
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/* Actual data being sent */
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uint8_t data[IVC_DATA_SZ_BYTES];
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};
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/**
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* Commands send to the BPMP firmware
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*/
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/**
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* MRQ code to issue a module reset command to BPMP
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*/
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#define MRQ_RESET U(20)
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/**
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* Reset sub-commands
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*/
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#define CMD_RESET_ASSERT U(1)
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#define CMD_RESET_DEASSERT U(2)
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#define CMD_RESET_MODULE U(3)
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/**
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* Used by the sender of an #MRQ_RESET message to request BPMP to
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* assert or deassert a given reset line.
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*/
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struct __attribute__((packed)) mrq_reset_request {
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/* reset action to perform (mrq_reset_commands) */
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uint32_t cmd;
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/* id of the reset to affected */
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uint32_t reset_id;
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};
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#endif /* INTF_H */
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@ -0,0 +1,653 @@
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <errno.h>
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#include <stddef.h>
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#include <string.h>
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#include "ivc.h"
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/*
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* IVC channel reset protocol.
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*
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* Each end uses its tx_channel.state to indicate its synchronization state.
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*/
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enum {
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/*
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* This value is zero for backwards compatibility with services that
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* assume channels to be initially zeroed. Such channels are in an
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* initially valid state, but cannot be asynchronously reset, and must
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* maintain a valid state at all times.
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*
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* The transmitting end can enter the established state from the sync or
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* ack state when it observes the receiving endpoint in the ack or
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* established state, indicating that has cleared the counters in our
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* rx_channel.
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*/
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ivc_state_established = U(0),
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/*
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* If an endpoint is observed in the sync state, the remote endpoint is
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* allowed to clear the counters it owns asynchronously with respect to
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* the current endpoint. Therefore, the current endpoint is no longer
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* allowed to communicate.
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*/
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ivc_state_sync = U(1),
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/*
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* When the transmitting end observes the receiving end in the sync
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* state, it can clear the w_count and r_count and transition to the ack
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* state. If the remote endpoint observes us in the ack state, it can
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* return to the established state once it has cleared its counters.
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*/
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ivc_state_ack = U(2)
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};
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/*
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* This structure is divided into two-cache aligned parts, the first is only
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* written through the tx_channel pointer, while the second is only written
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* through the rx_channel pointer. This delineates ownership of the cache lines,
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* which is critical to performance and necessary in non-cache coherent
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* implementations.
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*/
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struct ivc_channel_header {
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struct {
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/* fields owned by the transmitting end */
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uint32_t w_count;
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uint32_t state;
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uint32_t w_rsvd[IVC_CHHDR_TX_FIELDS - 2];
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};
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struct {
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/* fields owned by the receiving end */
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uint32_t r_count;
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uint32_t r_rsvd[IVC_CHHDR_RX_FIELDS - 1];
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};
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};
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static inline bool ivc_channel_empty(const struct ivc *ivc,
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volatile const struct ivc_channel_header *ch)
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{
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/*
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* This function performs multiple checks on the same values with
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* security implications, so sample the counters' current values in
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* shared memory to ensure that these checks use the same values.
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*/
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uint32_t wr_count = ch->w_count;
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uint32_t rd_count = ch->r_count;
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bool ret = false;
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(void)ivc;
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/*
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* Perform an over-full check to prevent denial of service attacks where
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* a server could be easily fooled into believing that there's an
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* extremely large number of frames ready, since receivers are not
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* expected to check for full or over-full conditions.
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*
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* Although the channel isn't empty, this is an invalid case caused by
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* a potentially malicious peer, so returning empty is safer, because it
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* gives the impression that the channel has gone silent.
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*/
|
||||
if (((wr_count - rd_count) > ivc->nframes) || (wr_count == rd_count)) {
|
||||
ret = true;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline bool ivc_channel_full(const struct ivc *ivc,
|
||||
volatile const struct ivc_channel_header *ch)
|
||||
{
|
||||
uint32_t wr_count = ch->w_count;
|
||||
uint32_t rd_count = ch->r_count;
|
||||
|
||||
(void)ivc;
|
||||
|
||||
/*
|
||||
* Invalid cases where the counters indicate that the queue is over
|
||||
* capacity also appear full.
|
||||
*/
|
||||
return ((wr_count - rd_count) >= ivc->nframes);
|
||||
}
|
||||
|
||||
static inline uint32_t ivc_channel_avail_count(const struct ivc *ivc,
|
||||
volatile const struct ivc_channel_header *ch)
|
||||
{
|
||||
uint32_t wr_count = ch->w_count;
|
||||
uint32_t rd_count = ch->r_count;
|
||||
|
||||
(void)ivc;
|
||||
|
||||
/*
|
||||
* This function isn't expected to be used in scenarios where an
|
||||
* over-full situation can lead to denial of service attacks. See the
|
||||
* comment in ivc_channel_empty() for an explanation about special
|
||||
* over-full considerations.
|
||||
*/
|
||||
return (wr_count - rd_count);
|
||||
}
|
||||
|
||||
static inline void ivc_advance_tx(struct ivc *ivc)
|
||||
{
|
||||
ivc->tx_channel->w_count++;
|
||||
|
||||
if (ivc->w_pos == (ivc->nframes - (uint32_t)1U)) {
|
||||
ivc->w_pos = 0U;
|
||||
} else {
|
||||
ivc->w_pos++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void ivc_advance_rx(struct ivc *ivc)
|
||||
{
|
||||
ivc->rx_channel->r_count++;
|
||||
|
||||
if (ivc->r_pos == (ivc->nframes - (uint32_t)1U)) {
|
||||
ivc->r_pos = 0U;
|
||||
} else {
|
||||
ivc->r_pos++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int32_t ivc_check_read(const struct ivc *ivc)
|
||||
{
|
||||
/*
|
||||
* tx_channel->state is set locally, so it is not synchronized with
|
||||
* state from the remote peer. The remote peer cannot reset its
|
||||
* transmit counters until we've acknowledged its synchronization
|
||||
* request, so no additional synchronization is required because an
|
||||
* asynchronous transition of rx_channel->state to ivc_state_ack is not
|
||||
* allowed.
|
||||
*/
|
||||
if (ivc->tx_channel->state != ivc_state_established) {
|
||||
return -ECONNRESET;
|
||||
}
|
||||
|
||||
/*
|
||||
* Avoid unnecessary invalidations when performing repeated accesses to
|
||||
* an IVC channel by checking the old queue pointers first.
|
||||
* Synchronization is only necessary when these pointers indicate empty
|
||||
* or full.
|
||||
*/
|
||||
if (!ivc_channel_empty(ivc, ivc->rx_channel)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return ivc_channel_empty(ivc, ivc->rx_channel) ? -ENOMEM : 0;
|
||||
}
|
||||
|
||||
static inline int32_t ivc_check_write(const struct ivc *ivc)
|
||||
{
|
||||
if (ivc->tx_channel->state != ivc_state_established) {
|
||||
return -ECONNRESET;
|
||||
}
|
||||
|
||||
if (!ivc_channel_full(ivc, ivc->tx_channel)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return ivc_channel_full(ivc, ivc->tx_channel) ? -ENOMEM : 0;
|
||||
}
|
||||
|
||||
bool tegra_ivc_can_read(const struct ivc *ivc)
|
||||
{
|
||||
return ivc_check_read(ivc) == 0;
|
||||
}
|
||||
|
||||
bool tegra_ivc_can_write(const struct ivc *ivc)
|
||||
{
|
||||
return ivc_check_write(ivc) == 0;
|
||||
}
|
||||
|
||||
bool tegra_ivc_tx_empty(const struct ivc *ivc)
|
||||
{
|
||||
return ivc_channel_empty(ivc, ivc->tx_channel);
|
||||
}
|
||||
|
||||
static inline uintptr_t calc_frame_offset(uint32_t frame_index,
|
||||
uint32_t frame_size, uint32_t frame_offset)
|
||||
{
|
||||
return ((uintptr_t)frame_index * (uintptr_t)frame_size) +
|
||||
(uintptr_t)frame_offset;
|
||||
}
|
||||
|
||||
static void *ivc_frame_pointer(const struct ivc *ivc,
|
||||
volatile const struct ivc_channel_header *ch,
|
||||
uint32_t frame)
|
||||
{
|
||||
assert(frame < ivc->nframes);
|
||||
return (void *)((uintptr_t)(&ch[1]) +
|
||||
calc_frame_offset(frame, ivc->frame_size, 0));
|
||||
}
|
||||
|
||||
int32_t tegra_ivc_read(struct ivc *ivc, void *buf, size_t max_read)
|
||||
{
|
||||
const void *src;
|
||||
int32_t result;
|
||||
|
||||
if (buf == NULL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (max_read > ivc->frame_size) {
|
||||
return -E2BIG;
|
||||
}
|
||||
|
||||
result = ivc_check_read(ivc);
|
||||
if (result != 0) {
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* Order observation of w_pos potentially indicating new data before
|
||||
* data read.
|
||||
*/
|
||||
dmbish();
|
||||
|
||||
src = ivc_frame_pointer(ivc, ivc->rx_channel, ivc->r_pos);
|
||||
|
||||
(void)memcpy(buf, src, max_read);
|
||||
|
||||
ivc_advance_rx(ivc);
|
||||
|
||||
/*
|
||||
* Ensure our write to r_pos occurs before our read from w_pos.
|
||||
*/
|
||||
dmbish();
|
||||
|
||||
/*
|
||||
* Notify only upon transition from full to non-full.
|
||||
* The available count can only asynchronously increase, so the
|
||||
* worst possible side-effect will be a spurious notification.
|
||||
*/
|
||||
if (ivc_channel_avail_count(ivc, ivc->rx_channel) == (ivc->nframes - (uint32_t)1U)) {
|
||||
ivc->notify(ivc);
|
||||
}
|
||||
|
||||
return (int32_t)max_read;
|
||||
}
|
||||
|
||||
/* directly peek at the next frame rx'ed */
|
||||
void *tegra_ivc_read_get_next_frame(const struct ivc *ivc)
|
||||
{
|
||||
if (ivc_check_read(ivc) != 0) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Order observation of w_pos potentially indicating new data before
|
||||
* data read.
|
||||
*/
|
||||
dmbld();
|
||||
|
||||
return ivc_frame_pointer(ivc, ivc->rx_channel, ivc->r_pos);
|
||||
}
|
||||
|
||||
int32_t tegra_ivc_read_advance(struct ivc *ivc)
|
||||
{
|
||||
/*
|
||||
* No read barriers or synchronization here: the caller is expected to
|
||||
* have already observed the channel non-empty. This check is just to
|
||||
* catch programming errors.
|
||||
*/
|
||||
int32_t result = ivc_check_read(ivc);
|
||||
if (result != 0) {
|
||||
return result;
|
||||
}
|
||||
|
||||
ivc_advance_rx(ivc);
|
||||
|
||||
/*
|
||||
* Ensure our write to r_pos occurs before our read from w_pos.
|
||||
*/
|
||||
dmbish();
|
||||
|
||||
/*
|
||||
* Notify only upon transition from full to non-full.
|
||||
* The available count can only asynchronously increase, so the
|
||||
* worst possible side-effect will be a spurious notification.
|
||||
*/
|
||||
if (ivc_channel_avail_count(ivc, ivc->rx_channel) == (ivc->nframes - (uint32_t)1U)) {
|
||||
ivc->notify(ivc);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t tegra_ivc_write(struct ivc *ivc, const void *buf, size_t size)
|
||||
{
|
||||
void *p;
|
||||
int32_t result;
|
||||
|
||||
if ((buf == NULL) || (ivc == NULL)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (size > ivc->frame_size) {
|
||||
return -E2BIG;
|
||||
}
|
||||
|
||||
result = ivc_check_write(ivc);
|
||||
if (result != 0) {
|
||||
return result;
|
||||
}
|
||||
|
||||
p = ivc_frame_pointer(ivc, ivc->tx_channel, ivc->w_pos);
|
||||
|
||||
(void)memset(p, 0, ivc->frame_size);
|
||||
(void)memcpy(p, buf, size);
|
||||
|
||||
/*
|
||||
* Ensure that updated data is visible before the w_pos counter
|
||||
* indicates that it is ready.
|
||||
*/
|
||||
dmbst();
|
||||
|
||||
ivc_advance_tx(ivc);
|
||||
|
||||
/*
|
||||
* Ensure our write to w_pos occurs before our read from r_pos.
|
||||
*/
|
||||
dmbish();
|
||||
|
||||
/*
|
||||
* Notify only upon transition from empty to non-empty.
|
||||
* The available count can only asynchronously decrease, so the
|
||||
* worst possible side-effect will be a spurious notification.
|
||||
*/
|
||||
if (ivc_channel_avail_count(ivc, ivc->tx_channel) == 1U) {
|
||||
ivc->notify(ivc);
|
||||
}
|
||||
|
||||
return (int32_t)size;
|
||||
}
|
||||
|
||||
/* directly poke at the next frame to be tx'ed */
|
||||
void *tegra_ivc_write_get_next_frame(const struct ivc *ivc)
|
||||
{
|
||||
if (ivc_check_write(ivc) != 0) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return ivc_frame_pointer(ivc, ivc->tx_channel, ivc->w_pos);
|
||||
}
|
||||
|
||||
/* advance the tx buffer */
|
||||
int32_t tegra_ivc_write_advance(struct ivc *ivc)
|
||||
{
|
||||
int32_t result = ivc_check_write(ivc);
|
||||
|
||||
if (result != 0) {
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* Order any possible stores to the frame before update of w_pos.
|
||||
*/
|
||||
dmbst();
|
||||
|
||||
ivc_advance_tx(ivc);
|
||||
|
||||
/*
|
||||
* Ensure our write to w_pos occurs before our read from r_pos.
|
||||
*/
|
||||
dmbish();
|
||||
|
||||
/*
|
||||
* Notify only upon transition from empty to non-empty.
|
||||
* The available count can only asynchronously decrease, so the
|
||||
* worst possible side-effect will be a spurious notification.
|
||||
*/
|
||||
if (ivc_channel_avail_count(ivc, ivc->tx_channel) == (uint32_t)1U) {
|
||||
ivc->notify(ivc);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void tegra_ivc_channel_reset(const struct ivc *ivc)
|
||||
{
|
||||
ivc->tx_channel->state = ivc_state_sync;
|
||||
ivc->notify(ivc);
|
||||
}
|
||||
|
||||
/*
|
||||
* ===============================================================
|
||||
* IVC State Transition Table - see tegra_ivc_channel_notified()
|
||||
* ===============================================================
|
||||
*
|
||||
* local remote action
|
||||
* ----- ------ -----------------------------------
|
||||
* SYNC EST <none>
|
||||
* SYNC ACK reset counters; move to EST; notify
|
||||
* SYNC SYNC reset counters; move to ACK; notify
|
||||
* ACK EST move to EST; notify
|
||||
* ACK ACK move to EST; notify
|
||||
* ACK SYNC reset counters; move to ACK; notify
|
||||
* EST EST <none>
|
||||
* EST ACK <none>
|
||||
* EST SYNC reset counters; move to ACK; notify
|
||||
*
|
||||
* ===============================================================
|
||||
*/
|
||||
int32_t tegra_ivc_channel_notified(struct ivc *ivc)
|
||||
{
|
||||
uint32_t peer_state;
|
||||
|
||||
/* Copy the receiver's state out of shared memory. */
|
||||
peer_state = ivc->rx_channel->state;
|
||||
|
||||
if (peer_state == (uint32_t)ivc_state_sync) {
|
||||
/*
|
||||
* Order observation of ivc_state_sync before stores clearing
|
||||
* tx_channel.
|
||||
*/
|
||||
dmbld();
|
||||
|
||||
/*
|
||||
* Reset tx_channel counters. The remote end is in the SYNC
|
||||
* state and won't make progress until we change our state,
|
||||
* so the counters are not in use at this time.
|
||||
*/
|
||||
ivc->tx_channel->w_count = 0U;
|
||||
ivc->rx_channel->r_count = 0U;
|
||||
|
||||
ivc->w_pos = 0U;
|
||||
ivc->r_pos = 0U;
|
||||
|
||||
/*
|
||||
* Ensure that counters appear cleared before new state can be
|
||||
* observed.
|
||||
*/
|
||||
dmbst();
|
||||
|
||||
/*
|
||||
* Move to ACK state. We have just cleared our counters, so it
|
||||
* is now safe for the remote end to start using these values.
|
||||
*/
|
||||
ivc->tx_channel->state = ivc_state_ack;
|
||||
|
||||
/*
|
||||
* Notify remote end to observe state transition.
|
||||
*/
|
||||
ivc->notify(ivc);
|
||||
|
||||
} else if ((ivc->tx_channel->state == (uint32_t)ivc_state_sync) &&
|
||||
(peer_state == (uint32_t)ivc_state_ack)) {
|
||||
/*
|
||||
* Order observation of ivc_state_sync before stores clearing
|
||||
* tx_channel.
|
||||
*/
|
||||
dmbld();
|
||||
|
||||
/*
|
||||
* Reset tx_channel counters. The remote end is in the ACK
|
||||
* state and won't make progress until we change our state,
|
||||
* so the counters are not in use at this time.
|
||||
*/
|
||||
ivc->tx_channel->w_count = 0U;
|
||||
ivc->rx_channel->r_count = 0U;
|
||||
|
||||
ivc->w_pos = 0U;
|
||||
ivc->r_pos = 0U;
|
||||
|
||||
/*
|
||||
* Ensure that counters appear cleared before new state can be
|
||||
* observed.
|
||||
*/
|
||||
dmbst();
|
||||
|
||||
/*
|
||||
* Move to ESTABLISHED state. We know that the remote end has
|
||||
* already cleared its counters, so it is safe to start
|
||||
* writing/reading on this channel.
|
||||
*/
|
||||
ivc->tx_channel->state = ivc_state_established;
|
||||
|
||||
/*
|
||||
* Notify remote end to observe state transition.
|
||||
*/
|
||||
ivc->notify(ivc);
|
||||
|
||||
} else if (ivc->tx_channel->state == (uint32_t)ivc_state_ack) {
|
||||
/*
|
||||
* At this point, we have observed the peer to be in either
|
||||
* the ACK or ESTABLISHED state. Next, order observation of
|
||||
* peer state before storing to tx_channel.
|
||||
*/
|
||||
dmbld();
|
||||
|
||||
/*
|
||||
* Move to ESTABLISHED state. We know that we have previously
|
||||
* cleared our counters, and we know that the remote end has
|
||||
* cleared its counters, so it is safe to start writing/reading
|
||||
* on this channel.
|
||||
*/
|
||||
ivc->tx_channel->state = ivc_state_established;
|
||||
|
||||
/*
|
||||
* Notify remote end to observe state transition.
|
||||
*/
|
||||
ivc->notify(ivc);
|
||||
|
||||
} else {
|
||||
/*
|
||||
* There is no need to handle any further action. Either the
|
||||
* channel is already fully established, or we are waiting for
|
||||
* the remote end to catch up with our current state. Refer
|
||||
* to the diagram in "IVC State Transition Table" above.
|
||||
*/
|
||||
}
|
||||
|
||||
return ((ivc->tx_channel->state == (uint32_t)ivc_state_established) ? 0 : -EAGAIN);
|
||||
}
|
||||
|
||||
size_t tegra_ivc_align(size_t size)
|
||||
{
|
||||
return (size + (IVC_ALIGN - 1U)) & ~(IVC_ALIGN - 1U);
|
||||
}
|
||||
|
||||
size_t tegra_ivc_total_queue_size(size_t queue_size)
|
||||
{
|
||||
if ((queue_size & (IVC_ALIGN - 1U)) != 0U) {
|
||||
ERROR("queue_size (%d) must be %d-byte aligned\n",
|
||||
(int32_t)queue_size, IVC_ALIGN);
|
||||
return 0;
|
||||
}
|
||||
return queue_size + sizeof(struct ivc_channel_header);
|
||||
}
|
||||
|
||||
static int32_t check_ivc_params(uintptr_t queue_base1, uintptr_t queue_base2,
|
||||
uint32_t nframes, uint32_t frame_size)
|
||||
{
|
||||
assert((offsetof(struct ivc_channel_header, w_count)
|
||||
& (IVC_ALIGN - 1U)) == 0U);
|
||||
assert((offsetof(struct ivc_channel_header, r_count)
|
||||
& (IVC_ALIGN - 1U)) == 0U);
|
||||
assert((sizeof(struct ivc_channel_header) & (IVC_ALIGN - 1U)) == 0U);
|
||||
|
||||
if (((uint64_t)nframes * (uint64_t)frame_size) >= 0x100000000ULL) {
|
||||
ERROR("nframes * frame_size overflows\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* The headers must at least be aligned enough for counters
|
||||
* to be accessed atomically.
|
||||
*/
|
||||
if ((queue_base1 & (IVC_ALIGN - 1U)) != 0U) {
|
||||
ERROR("ivc channel start not aligned: %lx\n", queue_base1);
|
||||
return -EINVAL;
|
||||
}
|
||||
if ((queue_base2 & (IVC_ALIGN - 1U)) != 0U) {
|
||||
ERROR("ivc channel start not aligned: %lx\n", queue_base2);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((frame_size & (IVC_ALIGN - 1U)) != 0U) {
|
||||
ERROR("frame size not adequately aligned: %u\n",
|
||||
frame_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (queue_base1 < queue_base2) {
|
||||
if ((queue_base1 + ((uint64_t)frame_size * nframes)) > queue_base2) {
|
||||
ERROR("queue regions overlap: %lx + %x, %x\n",
|
||||
queue_base1, frame_size,
|
||||
frame_size * nframes);
|
||||
return -EINVAL;
|
||||
}
|
||||
} else {
|
||||
if ((queue_base2 + ((uint64_t)frame_size * nframes)) > queue_base1) {
|
||||
ERROR("queue regions overlap: %lx + %x, %x\n",
|
||||
queue_base2, frame_size,
|
||||
frame_size * nframes);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t tegra_ivc_init(struct ivc *ivc, uintptr_t rx_base, uintptr_t tx_base,
|
||||
uint32_t nframes, uint32_t frame_size,
|
||||
ivc_notify_function notify)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
/* sanity check input params */
|
||||
if ((ivc == NULL) || (notify == NULL)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
result = check_ivc_params(rx_base, tx_base, nframes, frame_size);
|
||||
if (result != 0) {
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* All sizes that can be returned by communication functions should
|
||||
* fit in a 32-bit integer.
|
||||
*/
|
||||
if (frame_size > (1u << 31)) {
|
||||
return -E2BIG;
|
||||
}
|
||||
|
||||
ivc->rx_channel = (struct ivc_channel_header *)rx_base;
|
||||
ivc->tx_channel = (struct ivc_channel_header *)tx_base;
|
||||
ivc->notify = notify;
|
||||
ivc->frame_size = frame_size;
|
||||
ivc->nframes = nframes;
|
||||
ivc->w_pos = 0U;
|
||||
ivc->r_pos = 0U;
|
||||
|
||||
INFO("%s: done\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IVC_H
|
||||
#define IVC_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <utils_def.h>
|
||||
|
||||
#define IVC_ALIGN U(64)
|
||||
#define IVC_CHHDR_TX_FIELDS U(16)
|
||||
#define IVC_CHHDR_RX_FIELDS U(16)
|
||||
|
||||
struct ivc;
|
||||
struct ivc_channel_header;
|
||||
|
||||
/* callback handler for notify on receiving a response */
|
||||
typedef void (* ivc_notify_function)(const struct ivc *);
|
||||
|
||||
struct ivc {
|
||||
struct ivc_channel_header *rx_channel;
|
||||
struct ivc_channel_header *tx_channel;
|
||||
uint32_t w_pos;
|
||||
uint32_t r_pos;
|
||||
ivc_notify_function notify;
|
||||
uint32_t nframes;
|
||||
uint32_t frame_size;
|
||||
};
|
||||
|
||||
int32_t tegra_ivc_init(struct ivc *ivc, uintptr_t rx_base, uintptr_t tx_base,
|
||||
uint32_t nframes, uint32_t frame_size,
|
||||
ivc_notify_function notify);
|
||||
size_t tegra_ivc_total_queue_size(size_t queue_size);
|
||||
size_t tegra_ivc_align(size_t size);
|
||||
int32_t tegra_ivc_channel_notified(struct ivc *ivc);
|
||||
void tegra_ivc_channel_reset(const struct ivc *ivc);
|
||||
int32_t tegra_ivc_write_advance(struct ivc *ivc);
|
||||
void *tegra_ivc_write_get_next_frame(const struct ivc *ivc);
|
||||
int32_t tegra_ivc_write(struct ivc *ivc, const void *buf, size_t size);
|
||||
int32_t tegra_ivc_read_advance(struct ivc *ivc);
|
||||
void *tegra_ivc_read_get_next_frame(const struct ivc *ivc);
|
||||
int32_t tegra_ivc_read(struct ivc *ivc, void *buf, size_t max_read);
|
||||
bool tegra_ivc_tx_empty(const struct ivc *ivc);
|
||||
bool tegra_ivc_can_write(const struct ivc *ivc);
|
||||
bool tegra_ivc_can_read(const struct ivc *ivc);
|
||||
|
||||
#endif /* IVC_H */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __BPMP_IPC_H__
|
||||
#define __BPMP_IPC_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <utils_def.h>
|
||||
|
||||
/**
|
||||
* Currently supported reset identifiers
|
||||
*/
|
||||
#define TEGRA_RESET_ID_XUSB_PADCTL U(114)
|
||||
#define TEGRA_RESET_ID_GPCDMA U(70)
|
||||
|
||||
/**
|
||||
* Function to initialise the IPC with the bpmp
|
||||
*/
|
||||
int32_t tegra_bpmp_ipc_init(void);
|
||||
|
||||
/**
|
||||
* Handler to reset a module
|
||||
*/
|
||||
int32_t tegra_bpmp_ipc_reset_module(uint32_t rst_id);
|
||||
|
||||
#endif /* __BPMP_IPC_H__ */
|
||||
Loading…
Reference in New Issue