From f8e6a09c64b59eebb1de712ccb7d3203b0184ad6 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Thu, 14 May 2020 15:32:43 +0800 Subject: [PATCH 01/13] intel: common: Improve mailbox driver readability Use pre-defined macros for return values and common mailbox arguments Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e --- .../soc/common/include/socfpga_mailbox.h | 5 +- plat/intel/soc/common/soc/socfpga_mailbox.c | 59 ++++++++++--------- plat/intel/soc/common/socfpga_sip_svc.c | 18 +++--- 3 files changed, 42 insertions(+), 40 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index b250b3e90..f44bc0ecc 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -64,6 +64,7 @@ /* Mailbox Definitions */ #define CMD_DIRECT 0 +#define CMD_INDIRECT 1 #define CMD_CASUAL 0 #define CMD_URGENT 1 @@ -123,7 +124,7 @@ #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) -#define MBOX_INDIRECT (1 << 11) +#define MBOX_INDIRECT(val) ((val) << 11) /* RSU Macros */ #define RSU_VERSION_ACMF BIT(8) @@ -140,7 +141,7 @@ void mailbox_set_qspi_direct(void); int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response, int resp_len); int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent); + int len, int urgent, int indirect); int mailbox_read_response(int job_id, uint32_t *response, int resp_len); void mailbox_reset_cold(void); void mailbox_clear_response(void); diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index d066f27b5..cbc6bfba3 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2020, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,7 +32,7 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset); - return 0; + return MBOX_RET_OK; } int mailbox_read_response(int job_id, uint32_t *response, int resp_len) @@ -120,12 +120,12 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response, MBOX_STATUS_UA_MASK) ^ (urgent & MBOX_STATUS_UA_MASK)) { mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - return 0; + return MBOX_RET_OK; } mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); INFO("Error: Mailbox did not get UA"); - return -1; + return MBOX_RET_ERROR; } rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); @@ -168,7 +168,7 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response, } int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent) + int len, int urgent, int indirect) { if (urgent) mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); @@ -176,12 +176,12 @@ int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | MBOX_JOB_ID_CMD(job_id) | MBOX_CMD_LEN_CMD(len) | - MBOX_INDIRECT | + MBOX_INDIRECT(indirect) | cmd, args, len); mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - return 0; + return MBOX_RET_OK; } int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, @@ -229,25 +229,21 @@ void mailbox_set_int(int interrupt) void mailbox_set_qspi_open(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, NULL, 0, + CMD_CASUAL, NULL, 0); } void mailbox_set_qspi_direct(void) { - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, NULL, 0, + CMD_CASUAL, NULL, 0); } void mailbox_set_qspi_close(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, NULL, 0); -} - -int mailbox_get_qspi_clock(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, - NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, NULL, 0, + CMD_CASUAL, NULL, 0); } void mailbox_qspi_set_cs(int device_select) @@ -258,19 +254,20 @@ void mailbox_qspi_set_cs(int device_select) cs_setting = (cs_setting << 28); mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, - 1, 0, NULL, 0); + 1, CMD_CASUAL, NULL, 0); } void mailbox_reset_cold(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, NULL, 0, + CMD_CASUAL, NULL, 0); } int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_SUBPARTITION_TABLE, - NULL, 0, 0, (uint32_t *)resp_buf, + NULL, 0, CMD_CASUAL, (uint32_t *)resp_buf, resp_buf_len); } @@ -291,8 +288,9 @@ int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len) info->retry_counter = ~0; - ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0, 0, - (uint32_t *)resp_buf, resp_buf_len); + ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0, + CMD_CASUAL, (uint32_t *)resp_buf, + resp_buf_len); if (ret < 0) return ret; @@ -307,13 +305,15 @@ int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len) int mailbox_rsu_update(uint32_t *flash_offset) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE, - flash_offset, 2, 0, NULL, 0); + flash_offset, 2, + CMD_CASUAL, NULL, 0); } int mailbox_hps_stage_notify(uint32_t execution_stage) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY, - &execution_stage, 1, 0, NULL, 0); + &execution_stage, 1, CMD_CASUAL, + NULL, 0); } int mailbox_init(void) @@ -325,7 +325,8 @@ int mailbox_init(void) mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, NULL, 0); + status = mailbox_send_cmd(0, MBOX_CMD_RESTART, NULL, 0, + CMD_URGENT, NULL, 0); if (status) return status; @@ -333,7 +334,7 @@ int mailbox_init(void) mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | MBOX_INT_FLAG_UAE); - return 0; + return MBOX_RET_OK; } int intel_mailbox_get_config_status(uint32_t cmd) @@ -341,8 +342,8 @@ int intel_mailbox_get_config_status(uint32_t cmd) int status; uint32_t res, response[6]; - status = mailbox_send_cmd(1, cmd, NULL, 0, 0, response, - sizeof(response) / sizeof(response[0])); + status = mailbox_send_cmd(MBOX_JOB_ID, cmd, NULL, 0, CMD_CASUAL, response, + ARRAY_SIZE(response)); if (status < 0) return status; @@ -361,7 +362,7 @@ int intel_mailbox_get_config_status(uint32_t cmd) if ((res & SOFTFUNC_STATUS_CONF_DONE) && (res & SOFTFUNC_STATUS_INIT_DONE)) - return 0; + return MBOX_RET_OK; return MBOX_CFGSTAT_STATE_CONFIG; } diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index a20baab4c..b879cfc3b 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,10 +74,9 @@ static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) args[2] = bytes_per_block; buffer->size_written += args[2]; - mailbox_send_cmd_async( - send_id++ % MBOX_MAX_JOB_ID, - MBOX_RECONFIG_DATA, - args, 3, 0); + mailbox_send_cmd_async(send_id++ % MBOX_MAX_JOB_ID, + MBOX_RECONFIG_DATA, args, 3, + CMD_CASUAL, CMD_INDIRECT); buffer->subblocks_sent++; max_blocks--; @@ -154,7 +153,7 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr, while (*count < 3) { resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID, - resp, sizeof(resp) / sizeof(resp[0])); + resp, ARRAY_SIZE(resp)); if (resp_len < 0) break; @@ -208,10 +207,10 @@ static int intel_fpga_config_start(uint32_t config_type) mailbox_clear_response(); - mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); + mailbox_send_cmd(1, MBOX_CMD_CANCEL, NULL, 0, CMD_CASUAL, NULL, 0); - status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0, - response, sizeof(response) / sizeof(response[0])); + status = mailbox_send_cmd(1, MBOX_RECONFIG, NULL, 0, CMD_CASUAL, + response, ARRAY_SIZE(response)); if (status < 0) return status; @@ -449,6 +448,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, u_register_t x5, x6; int mbox_status, len_in_resp; + switch (smc_fid) { case SIP_SVC_UID: /* Return UID to the caller */ From d191eb247adc53b913b44f4ad9df90c5445f55c8 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Mon, 18 May 2020 10:32:15 +0800 Subject: [PATCH 02/13] intel: common: Remove urgent from mailbox async Remove urgent argument from asynchrounous mailbox command as any urgent command should always be synchronous Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319 --- plat/intel/soc/common/include/socfpga_mailbox.h | 2 +- plat/intel/soc/common/soc/socfpga_mailbox.c | 5 +---- plat/intel/soc/common/socfpga_sip_svc.c | 2 +- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index f44bc0ecc..710ecf0c5 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -141,7 +141,7 @@ void mailbox_set_qspi_direct(void); int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response, int resp_len); int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, int indirect); + int len, int indirect); int mailbox_read_response(int job_id, uint32_t *response, int resp_len); void mailbox_reset_cold(void); void mailbox_clear_response(void); diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index cbc6bfba3..39b63c987 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -168,11 +168,8 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response, } int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, int indirect) + int len, int indirect) { - if (urgent) - mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); - fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | MBOX_JOB_ID_CMD(job_id) | MBOX_CMD_LEN_CMD(len) | diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index b879cfc3b..8588e933b 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -76,7 +76,7 @@ static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) buffer->size_written += args[2]; mailbox_send_cmd_async(send_id++ % MBOX_MAX_JOB_ID, MBOX_RECONFIG_DATA, args, 3, - CMD_CASUAL, CMD_INDIRECT); + CMD_INDIRECT); buffer->subblocks_sent++; max_blocks--; From 1ae7b6f6b1dcc8669743c81a41423d8eca45949b Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Mon, 13 Apr 2020 09:40:43 -0500 Subject: [PATCH 03/13] intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher pre-reserved memory size between Intel service layer and secure monitor software so we can handle JIC file authorization. Signed-off-by: Richard Gong Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c --- plat/intel/soc/common/include/socfpga_sip_svc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 22e54e895..329f511ad 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -44,7 +44,7 @@ /* FPGA config helpers */ #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 -#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216 +#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 /* SMC function IDs for SiP Service queries */ #define SIP_SVC_CALL_COUNT 0x8200ff00 From 941fc5c0d2a6129e8e8791449e6ffa70f21ac378 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Wed, 12 Feb 2020 19:57:44 +0800 Subject: [PATCH 04/13] intel: common: Improve readability of mailbox read response Rename variables to improve readability of mailbox read response and mailbox poll response flow. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: Icd33ff1d2abb28eeead15e4eb9c7f9629f8cb402 --- plat/intel/soc/common/soc/socfpga_mailbox.c | 59 +++++++++++---------- 1 file changed, 31 insertions(+), 28 deletions(-) diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 39b63c987..4f02b6948 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -39,9 +39,10 @@ int mailbox_read_response(int job_id, uint32_t *response, int resp_len) { int rin = 0; int rout = 0; - int response_length = 0; - int resp = 0; + int mbox_resp_len = 0; + int resp_data = 0; int total_resp_len = 0; + uint32_t *resp_buf = response; if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)) mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); @@ -50,31 +51,31 @@ int mailbox_read_response(int job_id, uint32_t *response, int resp_len) rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); if (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + + resp_data = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + ((rout++)*4)); rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) { + if (MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID || + MBOX_RESP_JOB_ID(resp_data) != job_id) { return MBOX_WRONG_ID; } - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -resp; + if (MBOX_RESP_ERR(resp_data) > 0) { + INFO("Error in response: %x\n", resp_data); + return -resp_data; } - response_length = MBOX_RESP_LEN(resp); + mbox_resp_len = MBOX_RESP_LEN(resp_data); - while (response_length) { + while (mbox_resp_len > 0) { - response_length--; - resp = mmio_read_32(MBOX_OFFSET + + mbox_resp_len--; + resp_data = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + (rout)*4); - if (response && resp_len) { - *(response + total_resp_len) = resp; + if (resp_buf && resp_len) { + *(resp_buf + total_resp_len) = resp_data; resp_len--; total_resp_len++; } @@ -95,9 +96,10 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response, int timeout = 0xFFFFFF; int rin = 0; int rout = 0; - int response_length = 0; - int resp = 0; + int mbox_resp_len = 0; + int resp_data = 0; int total_resp_len = 0; + uint32_t *resp_buf = response; while (1) { @@ -132,29 +134,30 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response, rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); while (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + + resp_data = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + ((rout++)*4)); rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) + if (MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID + || MBOX_RESP_JOB_ID(resp_data) != job_id) continue; - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -MBOX_RESP_ERR(resp); + if (MBOX_RESP_ERR(resp_data) > 0) { + INFO("Error in response: %x\n", resp_data); + return -MBOX_RESP_ERR(resp_data); } - response_length = MBOX_RESP_LEN(resp); + mbox_resp_len = MBOX_RESP_LEN(resp_data); - while (response_length) { - response_length--; - resp = mmio_read_32(MBOX_OFFSET + + while (mbox_resp_len > 0) { + mbox_resp_len--; + resp_data = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + (rout)*4); - if (response && resp_len) { - *(response + total_resp_len) = resp; + if (resp_buf && resp_len) { + *(resp_buf + total_resp_len) + = resp_data; resp_len--; total_resp_len++; } From aad868b4d955fe827821f40830aa3392b9b24a83 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Mon, 18 May 2020 11:16:48 +0800 Subject: [PATCH 05/13] intel: common: Change how mailbox handles job id & buffer This patch modifies several basic mailbox driver features to prepare for FCS enablement: - Job id management for asynchronous response - SDM command buffer full Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2 --- .../soc/common/include/socfpga_mailbox.h | 14 +++-- .../soc/common/include/socfpga_sip_svc.h | 15 +++++ plat/intel/soc/common/soc/socfpga_mailbox.c | 39 ++++++++---- plat/intel/soc/common/socfpga_sip_svc.c | 60 +++++++------------ 4 files changed, 70 insertions(+), 58 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 710ecf0c5..75323fdf5 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -12,9 +12,10 @@ #define MBOX_OFFSET 0xffa30000 -#define MBOX_MAX_JOB_ID 0xf -#define MBOX_ATF_CLIENT_ID 0x1 -#define MBOX_JOB_ID 0x1 +#define MBOX_ATF_CLIENT_ID 0x1U +#define MBOX_MAX_JOB_ID 0xFU +#define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U) +#define MBOX_JOB_ID MBOX_MAX_JOB_ID /* Mailbox Shared Memory Register Map */ @@ -81,6 +82,7 @@ #define MBOX_RET_ERROR -1 #define MBOX_NO_RESPONSE -2 #define MBOX_WRONG_ID -3 +#define MBOX_BUFFER_FULL -4 #define MBOX_TIMEOUT -2047 /* Reconfig Status Response */ @@ -138,11 +140,11 @@ int mailbox_init(void); void mailbox_set_qspi_close(void); void mailbox_set_qspi_open(void); void mailbox_set_qspi_direct(void); -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, +int mailbox_send_cmd(uint32_t job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response, int resp_len); -int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, +int mailbox_send_cmd_async(uint32_t *job_id, unsigned int cmd, uint32_t *args, int len, int indirect); -int mailbox_read_response(int job_id, uint32_t *response, int resp_len); +int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len); void mailbox_reset_cold(void); void mailbox_clear_response(void); diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 329f511ad..92adfa3a7 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -55,4 +55,19 @@ #define SIP_SVC_VERSION_MAJOR 0 #define SIP_SVC_VERSION_MINOR 1 + +/* Structure Definitions */ +struct fpga_config_info { + uint32_t addr; + int size; + int size_written; + uint32_t write_requested; + int subblocks_sent; + int block_number; +}; + +/* Function Definitions */ + +bool is_address_in_ddr_range(uint64_t addr, uint64_t size); + #endif /* SOCFPGA_SIP_SVC_H */ diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 4f02b6948..5935777c0 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -14,10 +14,16 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, int len) { - uint32_t cmd_free_offset; + uint32_t sdm_read_offset, cmd_free_offset; int i; cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN); + sdm_read_offset = mmio_read_32(MBOX_OFFSET + MBOX_COUT); + + if ((cmd_free_offset < sdm_read_offset) && + (cmd_free_offset + len > sdm_read_offset)) { + return MBOX_BUFFER_FULL; + } mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4), header_cmd); @@ -35,7 +41,7 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, return MBOX_RET_OK; } -int mailbox_read_response(int job_id, uint32_t *response, int resp_len) +int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) { int rin = 0; int rout = 0; @@ -57,11 +63,13 @@ int mailbox_read_response(int job_id, uint32_t *response, int resp_len) rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - if (MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp_data) != job_id) { + + if (MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID) { return MBOX_WRONG_ID; } + *job_id = MBOX_RESP_JOB_ID(resp_data); + if (MBOX_RESP_ERR(resp_data) > 0) { INFO("Error in response: %x\n", resp_data); return -resp_data; @@ -90,7 +98,7 @@ int mailbox_read_response(int job_id, uint32_t *response, int resp_len) } -int mailbox_poll_response(int job_id, int urgent, uint32_t *response, +int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, int resp_len) { int timeout = 0xFFFFFF; @@ -170,21 +178,28 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response, } } -int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, +int mailbox_send_cmd_async(uint32_t *job_id, unsigned int cmd, uint32_t *args, int len, int indirect) { - fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | - MBOX_JOB_ID_CMD(job_id) | - MBOX_CMD_LEN_CMD(len) | - MBOX_INDIRECT(indirect) | - cmd, args, len); + int status; + + status = fill_mailbox_circular_buffer( + MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | + MBOX_JOB_ID_CMD(*job_id) | + MBOX_CMD_LEN_CMD(len) | + MBOX_INDIRECT(indirect) | + cmd, args, len); + if (status < 0) { + return status; + } mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); + *job_id = (*job_id + 1) % MBOX_MAX_IND_JOB_ID; return MBOX_RET_OK; } -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, +int mailbox_send_cmd(uint32_t job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response, int resp_len) { int status = 0; diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 8588e933b..d5789f247 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -14,30 +14,15 @@ #include "socfpga_reset_manager.h" #include "socfpga_sip_svc.h" -/* Number of SiP Calls implemented */ -#define SIP_NUM_CALLS 0x3 /* Total buffer the driver can hold */ #define FPGA_CONFIG_BUFFER_SIZE 4 -static int current_block; -static int read_block; -static int current_buffer; -static int send_id; -static int rcv_id; -static int max_blocks; -static uint32_t bytes_per_block; -static uint32_t blocks_submitted; -static int is_partial_reconfig; +static int current_block, current_buffer; +static int read_block, max_blocks, is_partial_reconfig; +static uint32_t send_id, rcv_id; +static uint32_t bytes_per_block, blocks_submitted; -struct fpga_config_info { - uint32_t addr; - int size; - int size_written; - uint32_t write_requested; - int subblocks_sent; - int block_number; -}; /* SiP Service UUID */ DEFINE_SVC_UUID2(intl_svc_uid, @@ -74,9 +59,8 @@ static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) args[2] = bytes_per_block; buffer->size_written += args[2]; - mailbox_send_cmd_async(send_id++ % MBOX_MAX_JOB_ID, - MBOX_RECONFIG_DATA, args, 3, - CMD_INDIRECT); + mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, + 3, CMD_INDIRECT); buffer->subblocks_sent++; max_blocks--; @@ -142,7 +126,7 @@ static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) } static int intel_fpga_config_completed_write(uint32_t *completed_addr, - uint32_t *count) + uint32_t *count, uint32_t *job_id) { uint32_t status = INTEL_SIP_SMC_STATUS_OK; *count = 0; @@ -152,14 +136,13 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr, while (*count < 3) { - resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID, + resp_len = mailbox_read_response(job_id, resp, ARRAY_SIZE(resp)); if (resp_len < 0) break; max_blocks++; - rcv_id++; if (mark_last_buffer_xfer_completed( &completed_addr[*count]) == 0) @@ -231,8 +214,6 @@ static int intel_fpga_config_start(uint32_t config_type) current_block = 0; read_block = 0; current_buffer = 0; - send_id = 0; - rcv_id = 0; /* full reconfiguration */ if (!is_partial_reconfig) { @@ -251,7 +232,7 @@ static bool is_fpga_config_buffer_full(void) return true; } -static bool is_address_in_ddr_range(uint64_t addr, uint64_t size) +bool is_address_in_ddr_range(uint64_t addr, uint64_t size) { if (size > (UINT64_MAX - addr)) return false; @@ -440,11 +421,10 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, void *handle, u_register_t flags) { - uint32_t val = 0; + uint32_t retval = 0; uint32_t status = INTEL_SIP_SMC_STATUS_OK; uint32_t completed_addr[3]; uint64_t rsu_respbuf[9]; - uint32_t count = 0; u_register_t x5, x6; int mbox_status, len_in_resp; @@ -474,8 +454,8 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: status = intel_fpga_config_completed_write(completed_addr, - &count); - switch (count) { + &retval, &rcv_id); + switch (retval) { case 1: SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, completed_addr[0], 0, 0); @@ -500,17 +480,17 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, } case INTEL_SIP_SMC_REG_READ: - status = intel_secure_reg_read(x1, &val); - SMC_RET3(handle, status, val, x1); + status = intel_secure_reg_read(x1, &retval); + SMC_RET3(handle, status, retval, x1); case INTEL_SIP_SMC_REG_WRITE: - status = intel_secure_reg_write(x1, (uint32_t)x2, &val); - SMC_RET3(handle, status, val, x1); + status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); + SMC_RET3(handle, status, retval, x1); case INTEL_SIP_SMC_REG_UPDATE: status = intel_secure_reg_update(x1, (uint32_t)x2, - (uint32_t)x3, &val); - SMC_RET3(handle, status, val, x1); + (uint32_t)x3, &retval); + SMC_RET3(handle, status, retval, x1); case INTEL_SIP_SMC_RSU_STATUS: status = intel_rsu_status(rsu_respbuf, @@ -532,11 +512,11 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, case INTEL_SIP_SMC_RSU_RETRY_COUNTER: status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, - ARRAY_SIZE(rsu_respbuf), &val); + ARRAY_SIZE(rsu_respbuf), &retval); if (status) { SMC_RET1(handle, status); } else { - SMC_RET2(handle, status, val); + SMC_RET2(handle, status, retval); } case INTEL_SIP_SMC_MBOX_SEND_CMD: From 39aebd358e7d430f5803fe47416ac4749684dbb9 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Wed, 29 Apr 2020 22:26:40 +0800 Subject: [PATCH 06/13] intel: mailbox: Driver now handles larger response This patch factorizes mailbox read response from SDM into a function. Also fix the logic to support reading larger than 16 words response from SDM. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5 --- .../soc/common/include/socfpga_mailbox.h | 1 + plat/intel/soc/common/soc/socfpga_mailbox.c | 83 +++++++++---------- 2 files changed, 42 insertions(+), 42 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 75323fdf5..59714fdb1 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -145,6 +145,7 @@ int mailbox_send_cmd(uint32_t job_id, unsigned int cmd, uint32_t *args, int mailbox_send_cmd_async(uint32_t *job_id, unsigned int cmd, uint32_t *args, int len, int indirect); int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len); +int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len); void mailbox_reset_cold(void); void mailbox_clear_response(void); diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 5935777c0..3bb2561cb 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -45,10 +45,7 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) { int rin = 0; int rout = 0; - int mbox_resp_len = 0; int resp_data = 0; - int total_resp_len = 0; - uint32_t *resp_buf = response; if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)) mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); @@ -74,26 +71,10 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) INFO("Error in response: %x\n", resp_data); return -resp_data; } - mbox_resp_len = MBOX_RESP_LEN(resp_data); - while (mbox_resp_len > 0) { - - mbox_resp_len--; - resp_data = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (resp_buf && resp_len) { - *(resp_buf + total_resp_len) = resp_data; - resp_len--; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; + return iterate_resp(MBOX_RESP_LEN(resp_data), + response, resp_len); } - return MBOX_NO_RESPONSE; } @@ -104,10 +85,7 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, int timeout = 0xFFFFFF; int rin = 0; int rout = 0; - int mbox_resp_len = 0; int resp_data = 0; - int total_resp_len = 0; - uint32_t *resp_buf = response; while (1) { @@ -118,7 +96,7 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, } if (!timeout) { - INFO("Timed out waiting for SDM"); + INFO("Timed out waiting for SDM\n"); return MBOX_TIMEOUT; } @@ -156,28 +134,49 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, INFO("Error in response: %x\n", resp_data); return -MBOX_RESP_ERR(resp_data); } - mbox_resp_len = MBOX_RESP_LEN(resp_data); - while (mbox_resp_len > 0) { - mbox_resp_len--; - resp_data = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (resp_buf && resp_len) { - *(resp_buf + total_resp_len) - = resp_data; - resp_len--; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; + return iterate_resp(MBOX_RESP_LEN(resp_data), + response, resp_len); } } } +int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len) +{ + uint32_t timeout; + int resp_data = 0, total_resp_len = 0; + int rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); + int rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); + + while (mbox_resp_len > 0) { + timeout = 0xFFFFFF; + mbox_resp_len--; + resp_data = mmio_read_32(MBOX_OFFSET + + MBOX_RESP_BUFFER + + (rout)*4); + if (resp_buf && resp_len) { + *(resp_buf + total_resp_len) + = resp_data; + resp_len--; + total_resp_len++; + } + rout++; + rout %= MBOX_RESP_BUFFER_SIZE; + mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); + + do { + timeout--; + rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); + } while ((rout == rin) && (mbox_resp_len > 0) && (timeout > 0)); + + if (timeout == 0) { + INFO("Timed out waiting for SDM\n"); + return MBOX_TIMEOUT; + } + } + return total_resp_len; +} + int mailbox_send_cmd_async(uint32_t *job_id, unsigned int cmd, uint32_t *args, int len, int indirect) { From 6d9f9f5ea0be1bc9d7daf6ecbe2e58e743dc9f28 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Mon, 11 May 2020 00:40:18 +0800 Subject: [PATCH 07/13] intel: mailbox: Read mailbox response even there is an error Mailbox driver should read the response data if the response length in the response header is non-zero even the response header indicates error (non-zero). Signed-off-by: Chee Hong Ang Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640 --- plat/intel/soc/common/soc/socfpga_mailbox.c | 23 +++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 3bb2561cb..4bae66efd 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -46,6 +46,7 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) int rin = 0; int rout = 0; int resp_data = 0; + int ret_resp_len; if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)) mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); @@ -67,13 +68,19 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) *job_id = MBOX_RESP_JOB_ID(resp_data); + ret_resp_len = MBOX_RESP_LEN(resp_data); + + if (ret_resp_len != 0) { + ret_resp_len = iterate_resp(ret_resp_len, response, + resp_len); + } + if (MBOX_RESP_ERR(resp_data) > 0) { INFO("Error in response: %x\n", resp_data); return -resp_data; } - return iterate_resp(MBOX_RESP_LEN(resp_data), - response, resp_len); + return ret_resp_len; } return MBOX_NO_RESPONSE; } @@ -86,6 +93,7 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, int rin = 0; int rout = 0; int resp_data = 0; + int ret_resp_len; while (1) { @@ -130,13 +138,20 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, || MBOX_RESP_JOB_ID(resp_data) != job_id) continue; + ret_resp_len = MBOX_RESP_LEN(resp_data); + + if (ret_resp_len != 0) { + ret_resp_len = iterate_resp(ret_resp_len, + response, + resp_len); + } + if (MBOX_RESP_ERR(resp_data) > 0) { INFO("Error in response: %x\n", resp_data); return -MBOX_RESP_ERR(resp_data); } - return iterate_resp(MBOX_RESP_LEN(resp_data), - response, resp_len); + return ret_resp_len; } } } From d96e7cda8a9f84ca8d0054bc1c86aabcb27db1d1 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Mon, 11 May 2020 00:55:01 +0800 Subject: [PATCH 08/13] intel: mailbox: Ensure time out duration is predictive For each count down of time out counter, wait for number of miliseconds to ensure the time out duration is predictive. Signed-off-by: Chee Hong Ang Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b --- plat/intel/soc/agilex/bl31_plat_setup.c | 2 ++ plat/intel/soc/agilex/platform.mk | 4 +-- plat/intel/soc/common/soc/socfpga_mailbox.c | 29 +++++++++++++-------- plat/intel/soc/stratix10/bl31_plat_setup.c | 2 ++ plat/intel/soc/stratix10/platform.mk | 4 +-- 5 files changed, 26 insertions(+), 15 deletions(-) diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index 436538b39..168236b64 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -101,6 +101,8 @@ static const gicv2_driver_data_t plat_gicv2_gic_data = { ******************************************************************************/ void bl31_platform_setup(void) { + socfpga_delay_timer_init(); + /* Initialize the gic cpu and distributor interfaces */ gicv2_driver_init(&plat_gicv2_gic_data); gicv2_distif_init(); diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 814d9c663..bf5cc1445 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -25,7 +25,8 @@ PLAT_BL_COMMON_SOURCES := \ lib/xlat_tables/aarch64/xlat_tables.c \ lib/xlat_tables/xlat_tables_common.c \ plat/intel/soc/common/aarch64/platform_common.c \ - plat/intel/soc/common/aarch64/plat_helpers.S + plat/intel/soc/common/aarch64/plat_helpers.S \ + plat/intel/soc/common/socfpga_delay_timer.c BL2_SOURCES += \ common/desc_image_load.c \ @@ -44,7 +45,6 @@ BL2_SOURCES += \ plat/intel/soc/agilex/soc/agilex_mmc.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ - plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_emac.c \ diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 4bae66efd..984aa9c6e 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -89,7 +89,7 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, int resp_len) { - int timeout = 0xFFFFFF; + uint32_t timeout = 40U; int rin = 0; int rout = 0; int resp_data = 0; @@ -97,13 +97,15 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, while (1) { - while (timeout > 0 && - !(mmio_read_32(MBOX_OFFSET + - MBOX_DOORBELL_FROM_SDM) & 1)) { - timeout--; - } + do { + if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) + & 1) { + break; + } + mdelay(25); + } while (--timeout != 0U); - if (!timeout) { + if (timeout == 0U) { INFO("Timed out waiting for SDM\n"); return MBOX_TIMEOUT; } @@ -164,7 +166,7 @@ int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len) int rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); while (mbox_resp_len > 0) { - timeout = 0xFFFFFF; + timeout = 40; mbox_resp_len--; resp_data = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + @@ -180,11 +182,16 @@ int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len) mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); do { - timeout--; rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - } while ((rout == rin) && (mbox_resp_len > 0) && (timeout > 0)); + if (rout == rin) { + mdelay(25); + } else { + break; + } + timeout--; + } while ((mbox_resp_len > 0) && (timeout != 0U)); - if (timeout == 0) { + if (timeout == 0U) { INFO("Timed out waiting for SDM\n"); return MBOX_TIMEOUT; } diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index e0c3054ed..128a8080d 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -109,6 +109,8 @@ static const gicv2_driver_data_t plat_gicv2_gic_data = { ******************************************************************************/ void bl31_platform_setup(void) { + socfpga_delay_timer_init(); + /* Initialize the gic cpu and distributor interfaces */ gicv2_driver_init(&plat_gicv2_gic_data); gicv2_distif_init(); diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 3bd6af9ce..8bbd01027 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -25,7 +25,8 @@ PLAT_BL_COMMON_SOURCES := \ lib/xlat_tables/aarch64/xlat_tables.c \ lib/xlat_tables/xlat_tables_common.c \ plat/intel/soc/common/aarch64/platform_common.c \ - plat/intel/soc/common/aarch64/plat_helpers.S + plat/intel/soc/common/aarch64/plat_helpers.S \ + plat/intel/soc/common/socfpga_delay_timer.c BL2_SOURCES += \ common/desc_image_load.c \ @@ -43,7 +44,6 @@ BL2_SOURCES += \ plat/intel/soc/stratix10/soc/s10_memory_controller.c \ plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ - plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_emac.c \ From 4978bc28325f5337bac5b2a2df1b772409628cb2 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Tue, 2 Jun 2020 01:05:24 +0800 Subject: [PATCH 09/13] intel: mailbox: Use retry count in mailbox poll Change the main loop inside mailbox poll function from while(1) to a retry counter named sdm_loop. This is to limit the maximum possible looping of the function and prevent unexpected behaviour. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I63afad958fe5f656f6333b60d5a8b4c0ada3b23d --- plat/intel/soc/common/soc/socfpga_mailbox.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 984aa9c6e..ddfe34cd0 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -90,12 +90,13 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, int resp_len) { uint32_t timeout = 40U; + uint32_t sdm_loop = 255U; int rin = 0; int rout = 0; int resp_data = 0; int ret_resp_len; - while (1) { + while (sdm_loop != 0U) { do { if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) @@ -106,8 +107,7 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, } while (--timeout != 0U); if (timeout == 0U) { - INFO("Timed out waiting for SDM\n"); - return MBOX_TIMEOUT; + break; } mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); @@ -155,7 +155,12 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, return ret_resp_len; } + + sdm_loop--; } + + INFO("Timed out waiting for SDM\n"); + return MBOX_TIMEOUT; } int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len) From d14e965c036af6b7164164a28d65771559760189 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Tue, 2 Jun 2020 01:06:33 +0800 Subject: [PATCH 10/13] intel: mailbox: Enable sending large mailbox command Allow mailbox command that is larger than mailbox command FIFO buffer size to be sent to SDM in multiple chunks. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I683d5f1d04c4fdf57d11ecae6232b7ed3fc49e26 --- plat/intel/soc/common/soc/socfpga_mailbox.c | 110 ++++++++++++++++---- 1 file changed, 91 insertions(+), 19 deletions(-) diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index ddfe34cd0..870ef10d4 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -11,32 +11,105 @@ #include "socfpga_mailbox.h" #include "socfpga_sip_svc.h" + +static bool is_mailbox_cmdbuf_full(uint32_t cin) +{ + uint32_t cout = mmio_read_32(MBOX_OFFSET + MBOX_COUT); + + return (((cin + 1U) % MBOX_CMD_BUFFER_SIZE) == cout); +} + +static bool is_mailbox_cmdbuf_empty(uint32_t cin) +{ + uint32_t cout = mmio_read_32(MBOX_OFFSET + MBOX_COUT); + + return (((cout + 1U) % MBOX_CMD_BUFFER_SIZE) == cin); +} + +static int wait_for_mailbox_cmdbuf_empty(uint32_t cin) +{ + uint32_t timeout = 200U; + + do { + if (is_mailbox_cmdbuf_empty(cin)) { + break; + } + mdelay(10U); + } while (--timeout != 0U); + + if (timeout == 0U) { + return MBOX_TIMEOUT; + } + + return MBOX_RET_OK; +} + +static int write_mailbox_cmd_buffer(uint32_t *cin, uint32_t cout, + uint32_t data, + bool *is_doorbell_triggered) +{ + uint32_t timeout = 100U; + + do { + if (is_mailbox_cmdbuf_full(*cin)) { + if (!(*is_doorbell_triggered)) { + mmio_write_32(MBOX_OFFSET + + MBOX_DOORBELL_TO_SDM, 1); + *is_doorbell_triggered = true; + } + mdelay(10U); + } else { + mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + + (*cin * 4), data); + (*cin)++; + *cin %= MBOX_CMD_BUFFER_SIZE; + mmio_write_32(MBOX_OFFSET + MBOX_CIN, *cin); + break; + } + } while (--timeout != 0U); + + if (timeout == 0U) { + return MBOX_TIMEOUT; + } + + if (*is_doorbell_triggered) { + int ret = wait_for_mailbox_cmdbuf_empty(*cin); + return ret; + } + + return MBOX_RET_OK; +} + static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, int len) { uint32_t sdm_read_offset, cmd_free_offset; - int i; + uint32_t i; + int ret; + bool is_doorbell_triggered = false; cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN); sdm_read_offset = mmio_read_32(MBOX_OFFSET + MBOX_COUT); - if ((cmd_free_offset < sdm_read_offset) && - (cmd_free_offset + len > sdm_read_offset)) { - return MBOX_BUFFER_FULL; + ret = write_mailbox_cmd_buffer(&cmd_free_offset, sdm_read_offset, + header_cmd, &is_doorbell_triggered); + if (ret != 0) { + return ret; } - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4), - header_cmd); - - - for (i = 0; i < len; i++) { - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + - (cmd_free_offset++ * 4), args[i]); + for (i = 0U; i < len; i++) { + is_doorbell_triggered = false; + ret = write_mailbox_cmd_buffer(&cmd_free_offset, + sdm_read_offset, args[i], + &is_doorbell_triggered); + if (ret != 0) { + return ret; + } } - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset); + if (!is_doorbell_triggered) { + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); + } return MBOX_RET_OK; } @@ -103,7 +176,7 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, & 1) { break; } - mdelay(25); + mdelay(10U); } while (--timeout != 0U); if (timeout == 0U) { @@ -171,7 +244,7 @@ int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len) int rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); while (mbox_resp_len > 0) { - timeout = 40; + timeout = 100U; mbox_resp_len--; resp_data = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + @@ -189,7 +262,7 @@ int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len) do { rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); if (rout == rin) { - mdelay(25); + mdelay(10U); } else { break; } @@ -219,7 +292,6 @@ int mailbox_send_cmd_async(uint32_t *job_id, unsigned int cmd, uint32_t *args, return status; } - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); *job_id = (*job_id + 1) % MBOX_MAX_IND_JOB_ID; return MBOX_RET_OK; @@ -234,6 +306,7 @@ int mailbox_send_cmd(uint32_t job_id, unsigned int cmd, uint32_t *args, urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & MBOX_STATUS_UA_MASK; mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd); + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); } else { @@ -247,7 +320,6 @@ int mailbox_send_cmd(uint32_t job_id, unsigned int cmd, uint32_t *args, if (status) return status; - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); status = mailbox_poll_response(job_id, urgent, response, resp_len); return status; From 997560470a18e1f0b84f35b2d51960fee9b5fc61 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Mon, 11 May 2020 11:23:21 +0800 Subject: [PATCH 11/13] intel: mailbox: Mailbox error recovery handling Attempt to restart the mailbox if the mailbox driver not able to write any data into the mailbox command buffer. Signed-off-by: Chee Hong Ang Change-Id: Ia45291c985844dec9da82839cac701347534d32b --- .../soc/common/include/socfpga_mailbox.h | 1 + plat/intel/soc/common/soc/socfpga_mailbox.c | 22 ++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 59714fdb1..3a2bf309e 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -127,6 +127,7 @@ #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) #define MBOX_INDIRECT(val) ((val) << 11) +#define MBOX_CMD_MASK(header) ((header) & 0x7ff) /* RSU Macros */ #define RSU_VERSION_ACMF BIT(8) diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 870ef10d4..9ba9b3171 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -94,7 +94,7 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, ret = write_mailbox_cmd_buffer(&cmd_free_offset, sdm_read_offset, header_cmd, &is_doorbell_triggered); if (ret != 0) { - return ret; + goto restart_mailbox; } for (i = 0U; i < len; i++) { @@ -103,7 +103,7 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, sdm_read_offset, args[i], &is_doorbell_triggered); if (ret != 0) { - return ret; + goto restart_mailbox; } } @@ -112,6 +112,22 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, } return MBOX_RET_OK; + +restart_mailbox: + /* + * Attempt to restart mailbox if the driver not able to write + * into mailbox command buffer + */ + if (MBOX_CMD_MASK(header_cmd) != MBOX_CMD_RESTART) { + INFO("Mailbox timed out: Attempting mailbox reset\n"); + ret = mailbox_init(); + + if (ret == MBOX_TIMEOUT) { + INFO("Error: Mailbox fail to restart\n"); + } + } + + return MBOX_TIMEOUT; } int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) @@ -150,7 +166,7 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) if (MBOX_RESP_ERR(resp_data) > 0) { INFO("Error in response: %x\n", resp_data); - return -resp_data; + return -MBOX_RESP_ERR(resp_data); } return ret_resp_len; From 9e285909ae02ba61ada6620f89c8575b2941e3b3 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Tue, 1 Sep 2020 21:05:18 +0800 Subject: [PATCH 12/13] intel: mailbox: Fix non-MISRA compliant code This patch is used to fix remaining non compliant code for Intel SocFPGA's mailbox driver. These changes include: - adding integer literal for unsigned constant - fix non-boolean controlling expression - add braces even on conditional single statement bodies Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I0f8fd96a3540f35ee102fd2f2369b76fa73e39e1 --- plat/intel/soc/common/soc/socfpga_mailbox.c | 79 ++++++++++++--------- 1 file changed, 46 insertions(+), 33 deletions(-) diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 9ba9b3171..29f3df28d 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -54,7 +54,7 @@ static int write_mailbox_cmd_buffer(uint32_t *cin, uint32_t cout, if (is_mailbox_cmdbuf_full(*cin)) { if (!(*is_doorbell_triggered)) { mmio_write_32(MBOX_OFFSET + - MBOX_DOORBELL_TO_SDM, 1); + MBOX_DOORBELL_TO_SDM, 1U); *is_doorbell_triggered = true; } mdelay(10U); @@ -108,7 +108,7 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, } if (!is_doorbell_triggered) { - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U); } return MBOX_RET_OK; @@ -137,8 +137,9 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) int resp_data = 0; int ret_resp_len; - if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)) - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); + if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) == 1U) { + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U); + } rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); @@ -189,7 +190,7 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, do { if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) - & 1) { + == 1U) { break; } mdelay(10U); @@ -199,18 +200,18 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, break; } - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U); - if (urgent & 1) { - mdelay(5); + if ((urgent & 1) != 0) { + mdelay(5U); if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & MBOX_STATUS_UA_MASK) ^ (urgent & MBOX_STATUS_UA_MASK)) { - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); + mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U); return MBOX_RET_OK; } - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); + mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U); INFO("Error: Mailbox did not get UA"); return MBOX_RET_ERROR; } @@ -226,8 +227,9 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); if (MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID - || MBOX_RESP_JOB_ID(resp_data) != job_id) + || MBOX_RESP_JOB_ID(resp_data) != job_id) { continue; + } ret_resp_len = MBOX_RESP_LEN(resp_data); @@ -308,7 +310,7 @@ int mailbox_send_cmd_async(uint32_t *job_id, unsigned int cmd, uint32_t *args, return status; } - *job_id = (*job_id + 1) % MBOX_MAX_IND_JOB_ID; + *job_id = (*job_id + 1U) % MBOX_MAX_IND_JOB_ID; return MBOX_RET_OK; } @@ -318,11 +320,11 @@ int mailbox_send_cmd(uint32_t job_id, unsigned int cmd, uint32_t *args, { int status = 0; - if (urgent) { + if (urgent != 0) { urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & MBOX_STATUS_UA_MASK; mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd); - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U); } else { @@ -333,8 +335,9 @@ int mailbox_send_cmd(uint32_t job_id, unsigned int cmd, uint32_t *args, cmd, args, len); } - if (status) + if (status != 0) { return status; + } status = mailbox_poll_response(job_id, urgent, response, resp_len); @@ -375,12 +378,12 @@ void mailbox_set_qspi_close(void) CMD_CASUAL, NULL, 0); } -void mailbox_qspi_set_cs(int device_select) +void mailbox_qspi_set_cs(uint32_t device_select) { - uint32_t cs_setting = device_select; + uint32_t cs_setting; /* QSPI device select settings at 31:28 */ - cs_setting = (cs_setting << 28); + cs_setting = (device_select << 28); mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, 1, CMD_CASUAL, NULL, 0); @@ -415,18 +418,21 @@ int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len) int ret; struct rsu_status_info *info = (struct rsu_status_info *)resp_buf; - info->retry_counter = ~0; + info->retry_counter = ~0U; ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0, CMD_CASUAL, (uint32_t *)resp_buf, resp_buf_len); - if (ret < 0) + if (ret < 0) { return ret; + } - if (info->retry_counter != ~0) - if (!(info->version & RSU_VERSION_ACMF_MASK)) + if (info->retry_counter != ~0U) { + if ((info->version & RSU_VERSION_ACMF_MASK) == 0U) { info->version |= RSU_VERSION_ACMF; + } + } return ret; } @@ -451,14 +457,15 @@ int mailbox_init(void) mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | MBOX_INT_FLAG_UAE); - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); + mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U); + mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U); - status = mailbox_send_cmd(0, MBOX_CMD_RESTART, NULL, 0, + status = mailbox_send_cmd(0U, MBOX_CMD_RESTART, NULL, 0, CMD_URGENT, NULL, 0); - if (status) + if (status != 0) { return status; + } mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | MBOX_INT_FLAG_UAE); @@ -474,24 +481,29 @@ int intel_mailbox_get_config_status(uint32_t cmd) status = mailbox_send_cmd(MBOX_JOB_ID, cmd, NULL, 0, CMD_CASUAL, response, ARRAY_SIZE(response)); - if (status < 0) + if (status < 0) { return status; + } res = response[RECONFIG_STATUS_STATE]; - if (res && res != MBOX_CFGSTAT_STATE_CONFIG) + if ((res != 0U) && (res != MBOX_CFGSTAT_STATE_CONFIG)) { return res; + } res = response[RECONFIG_STATUS_PIN_STATUS]; - if (!(res & PIN_STATUS_NSTATUS)) + if ((res & PIN_STATUS_NSTATUS) == 0U) { return MBOX_CFGSTAT_STATE_ERROR_HARDWARE; + } res = response[RECONFIG_STATUS_SOFTFUNC_STATUS]; - if (res & SOFTFUNC_STATUS_SEU_ERROR) + if ((res & SOFTFUNC_STATUS_SEU_ERROR) != 0U) { return MBOX_CFGSTAT_STATE_ERROR_HARDWARE; + } - if ((res & SOFTFUNC_STATUS_CONF_DONE) && - (res & SOFTFUNC_STATUS_INIT_DONE)) + if ((res & SOFTFUNC_STATUS_CONF_DONE) != 0U && + (res & SOFTFUNC_STATUS_INIT_DONE) != 0U) { return MBOX_RET_OK; + } return MBOX_CFGSTAT_STATE_CONFIG; } @@ -500,8 +512,9 @@ int intel_mailbox_is_fpga_not_ready(void) { int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); - if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG) + if ((ret != MBOX_RET_OK) && (ret != MBOX_CFGSTAT_STATE_CONFIG)) { ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + } return ret; } From d57318b7c9584f1613c9223028ef8ea186d6d203 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Thu, 15 Oct 2020 15:27:18 +0800 Subject: [PATCH 13/13] intel: common: Fix non-MISRA compliant code v2 This patch is used to fix remaining non compliant code for Intel SoCFPGA's mailbox and sip driver. These changes include: - Change non-interface required uint32_t into unsigned int - Change non-negative variable to unsigned int - Remove obsolete variable initialization to 0 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5 --- .../soc/common/include/socfpga_mailbox.h | 19 ++- plat/intel/soc/common/soc/socfpga_mailbox.c | 128 +++++++++--------- plat/intel/soc/common/socfpga_sip_svc.c | 14 +- 3 files changed, 85 insertions(+), 76 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 3a2bf309e..923c4f154 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -136,17 +136,22 @@ /* Mailbox Function Definitions */ -void mailbox_set_int(int interrupt_input); +void mailbox_set_int(uint32_t interrupt_input); int mailbox_init(void); void mailbox_set_qspi_close(void); void mailbox_set_qspi_open(void); void mailbox_set_qspi_direct(void); -int mailbox_send_cmd(uint32_t job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response, int resp_len); -int mailbox_send_cmd_async(uint32_t *job_id, unsigned int cmd, uint32_t *args, - int len, int indirect); -int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len); -int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len); + +int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, + unsigned int len, uint32_t urgent, uint32_t *response, + unsigned int resp_len); +int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, + unsigned int len, unsigned int indirect); +int mailbox_read_response(uint32_t *job_id, uint32_t *response, + unsigned int resp_len); +unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, + unsigned int resp_len); + void mailbox_reset_cold(void); void mailbox_clear_response(void); diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 29f3df28d..aec94af94 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -28,7 +28,7 @@ static bool is_mailbox_cmdbuf_empty(uint32_t cin) static int wait_for_mailbox_cmdbuf_empty(uint32_t cin) { - uint32_t timeout = 200U; + unsigned int timeout = 200U; do { if (is_mailbox_cmdbuf_empty(cin)) { @@ -48,7 +48,7 @@ static int write_mailbox_cmd_buffer(uint32_t *cin, uint32_t cout, uint32_t data, bool *is_doorbell_triggered) { - uint32_t timeout = 100U; + unsigned int timeout = 100U; do { if (is_mailbox_cmdbuf_full(*cin)) { @@ -81,10 +81,10 @@ static int write_mailbox_cmd_buffer(uint32_t *cin, uint32_t cout, } static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, - int len) + unsigned int len) { uint32_t sdm_read_offset, cmd_free_offset; - uint32_t i; + unsigned int i; int ret; bool is_doorbell_triggered = false; @@ -130,12 +130,13 @@ restart_mailbox: return MBOX_TIMEOUT; } -int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) +int mailbox_read_response(unsigned int *job_id, uint32_t *response, + unsigned int resp_len) { - int rin = 0; - int rout = 0; - int resp_data = 0; - int ret_resp_len; + uint32_t rin; + uint32_t rout; + uint32_t resp_data; + unsigned int ret_resp_len; if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) == 1U) { mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U); @@ -146,7 +147,7 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) if (rout != rin) { resp_data = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); + MBOX_RESP_BUFFER + ((rout++)*4U)); rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); @@ -160,12 +161,12 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) ret_resp_len = MBOX_RESP_LEN(resp_data); - if (ret_resp_len != 0) { + if (ret_resp_len != 0U) { ret_resp_len = iterate_resp(ret_resp_len, response, resp_len); } - if (MBOX_RESP_ERR(resp_data) > 0) { + if (MBOX_RESP_ERR(resp_data) > 0U) { INFO("Error in response: %x\n", resp_data); return -MBOX_RESP_ERR(resp_data); } @@ -176,15 +177,15 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len) } -int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, - int resp_len) +int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response, + unsigned int resp_len) { - uint32_t timeout = 40U; - uint32_t sdm_loop = 255U; - int rin = 0; - int rout = 0; - int resp_data = 0; - int ret_resp_len; + unsigned int timeout = 40U; + unsigned int sdm_loop = 255U; + unsigned int ret_resp_len; + uint32_t rin; + uint32_t rout; + uint32_t resp_data; while (sdm_loop != 0U) { @@ -202,7 +203,7 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U); - if ((urgent & 1) != 0) { + if ((urgent & 1U) != 0U) { mdelay(5U); if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & MBOX_STATUS_UA_MASK) ^ @@ -221,7 +222,7 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, while (rout != rin) { resp_data = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); + MBOX_RESP_BUFFER + ((rout++)*4U)); rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); @@ -233,13 +234,13 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, ret_resp_len = MBOX_RESP_LEN(resp_data); - if (ret_resp_len != 0) { + if (ret_resp_len != 0U) { ret_resp_len = iterate_resp(ret_resp_len, response, resp_len); } - if (MBOX_RESP_ERR(resp_data) > 0) { + if (MBOX_RESP_ERR(resp_data) > 0U) { INFO("Error in response: %x\n", resp_data); return -MBOX_RESP_ERR(resp_data); } @@ -254,20 +255,22 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response, return MBOX_TIMEOUT; } -int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len) +unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, + unsigned int resp_len) { - uint32_t timeout; - int resp_data = 0, total_resp_len = 0; - int rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - int rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); + unsigned int timeout, total_resp_len = 0U; + uint32_t resp_data; + uint32_t rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); + uint32_t rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - while (mbox_resp_len > 0) { + while (mbox_resp_len > 0U) { timeout = 100U; mbox_resp_len--; resp_data = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + - (rout)*4); - if (resp_buf && resp_len) { + (rout)*4U); + + if ((resp_buf != NULL) && (resp_len != 0U)) { *(resp_buf + total_resp_len) = resp_data; resp_len--; @@ -285,7 +288,7 @@ int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len) break; } timeout--; - } while ((mbox_resp_len > 0) && (timeout != 0U)); + } while ((mbox_resp_len > 0U) && (timeout != 0U)); if (timeout == 0U) { INFO("Timed out waiting for SDM\n"); @@ -295,8 +298,8 @@ int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len) return total_resp_len; } -int mailbox_send_cmd_async(uint32_t *job_id, unsigned int cmd, uint32_t *args, - int len, int indirect) +int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, + unsigned int len, unsigned int indirect) { int status; @@ -315,12 +318,13 @@ int mailbox_send_cmd_async(uint32_t *job_id, unsigned int cmd, uint32_t *args, return MBOX_RET_OK; } -int mailbox_send_cmd(uint32_t job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response, int resp_len) +int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, + unsigned int len, uint32_t urgent, uint32_t *response, + unsigned int resp_len) { int status = 0; - if (urgent != 0) { + if (urgent != 0U) { urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & MBOX_STATUS_UA_MASK; mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd); @@ -350,7 +354,7 @@ void mailbox_clear_response(void) mmio_read_32(MBOX_OFFSET + MBOX_RIN)); } -void mailbox_set_int(int interrupt) +void mailbox_set_int(uint32_t interrupt) { mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) | @@ -361,21 +365,21 @@ void mailbox_set_int(int interrupt) void mailbox_set_qspi_open(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, NULL, 0, - CMD_CASUAL, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, NULL, 0U, + CMD_CASUAL, NULL, 0U); } void mailbox_set_qspi_direct(void) { - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, NULL, 0, - CMD_CASUAL, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, NULL, 0U, + CMD_CASUAL, NULL, 0U); } void mailbox_set_qspi_close(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, NULL, 0, - CMD_CASUAL, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, NULL, 0U, + CMD_CASUAL, NULL, 0U); } void mailbox_qspi_set_cs(uint32_t device_select) @@ -386,20 +390,20 @@ void mailbox_qspi_set_cs(uint32_t device_select) cs_setting = (device_select << 28); mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, - 1, CMD_CASUAL, NULL, 0); + 1U, CMD_CASUAL, NULL, 0U); } void mailbox_reset_cold(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, NULL, 0, - CMD_CASUAL, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, NULL, 0U, + CMD_CASUAL, NULL, 0U); } -int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len) +int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, unsigned int resp_buf_len) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_SUBPARTITION_TABLE, - NULL, 0, CMD_CASUAL, (uint32_t *)resp_buf, + NULL, 0U, CMD_CASUAL, resp_buf, resp_buf_len); } @@ -413,15 +417,15 @@ struct rsu_status_info { uint32_t retry_counter; }; -int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len) +int mailbox_rsu_status(uint32_t *resp_buf, unsigned int resp_buf_len) { int ret; struct rsu_status_info *info = (struct rsu_status_info *)resp_buf; info->retry_counter = ~0U; - ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0, - CMD_CASUAL, (uint32_t *)resp_buf, + ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0U, + CMD_CASUAL, resp_buf, resp_buf_len); if (ret < 0) { @@ -440,28 +444,28 @@ int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len) int mailbox_rsu_update(uint32_t *flash_offset) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE, - flash_offset, 2, - CMD_CASUAL, NULL, 0); + flash_offset, 2U, + CMD_CASUAL, NULL, 0U); } int mailbox_hps_stage_notify(uint32_t execution_stage) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY, - &execution_stage, 1, CMD_CASUAL, - NULL, 0); + &execution_stage, 1U, CMD_CASUAL, + NULL, 0U); } int mailbox_init(void) { - int status = 0; + int status; mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | MBOX_INT_FLAG_UAE); mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U); mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U); - status = mailbox_send_cmd(0U, MBOX_CMD_RESTART, NULL, 0, - CMD_URGENT, NULL, 0); + status = mailbox_send_cmd(0U, MBOX_CMD_RESTART, NULL, 0U, + CMD_URGENT, NULL, 0U); if (status != 0) { return status; @@ -478,8 +482,8 @@ int intel_mailbox_get_config_status(uint32_t cmd) int status; uint32_t res, response[6]; - status = mailbox_send_cmd(MBOX_JOB_ID, cmd, NULL, 0, CMD_CASUAL, response, - ARRAY_SIZE(response)); + status = mailbox_send_cmd(MBOX_JOB_ID, cmd, NULL, 0U, CMD_CASUAL, + response, ARRAY_SIZE(response)); if (status < 0) { return status; diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index d5789f247..86a44556a 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -60,7 +60,7 @@ static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) buffer->size_written += args[2]; mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, - 3, CMD_INDIRECT); + 3U, CMD_INDIRECT); buffer->subblocks_sent++; max_blocks--; @@ -190,9 +190,9 @@ static int intel_fpga_config_start(uint32_t config_type) mailbox_clear_response(); - mailbox_send_cmd(1, MBOX_CMD_CANCEL, NULL, 0, CMD_CASUAL, NULL, 0); + mailbox_send_cmd(1U, MBOX_CMD_CANCEL, NULL, 0U, CMD_CASUAL, NULL, 0U); - status = mailbox_send_cmd(1, MBOX_RECONFIG, NULL, 0, CMD_CASUAL, + status = mailbox_send_cmd(1U, MBOX_RECONFIG, NULL, 0U, CMD_CASUAL, response, ARRAY_SIZE(response)); if (status < 0) @@ -351,7 +351,7 @@ uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, /* Intel Remote System Update (RSU) services */ uint64_t intel_rsu_update_address; -static uint32_t intel_rsu_status(uint64_t *respbuf, uint32_t respbuf_sz) +static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) { if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) return INTEL_SIP_SMC_RSU_ERROR; @@ -384,9 +384,9 @@ static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, } /* Mailbox services */ -static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, int len, - int urgent, uint32_t *response, - int resp_len, int *mbox_status, +static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, uint32_t len, + uint32_t urgent, uint32_t *response, + uint32_t resp_len, int *mbox_status, int *len_in_resp) { *len_in_resp = 0;