feat(nxp/driver/ifc_nand): add IFC NAND flash driver
Support IFC NAND flash as boot device. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I1aba7035ff70b179915e181c04e7b00be2066abe
This commit is contained in:
Jiafei Pan
parent
e2fdc77ba4
commit
28279cf2c1
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@ -93,3 +93,7 @@ endif
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ifeq (${IFC_NOR_NEEDED},yes)
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include ${PLAT_DRIVERS_PATH}/ifc/nor/ifc_nor.mk
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endif
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ifeq (${IFC_NAND_NEEDED},yes)
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include ${PLAT_DRIVERS_PATH}/ifc/nand/ifc_nand.mk
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endif
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@ -0,0 +1,329 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IFC_H
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#define IFC_H
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#include <endian.h>
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#include <mmio.h>
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#define NXP_IFC_RUN_TIME_ADDR U(0x1000)
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/* CPSR - Chip Select Property Register Offset */
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#define EXT_CSPR(n) (U(0x000C) + (n * 0xC))
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#define CSPR(n) (U(0x0010) + (n * 0xC))
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#define CSOR(n) (U(0x0130) + (n * 0xC))
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#define EXT_CSOR(n) (U(0x0134) + (n * 0xC))
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#define IFC_AMASK_CS0 U(0x00A0)
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/* NAND specific Registers Offset */
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#define NCFGR (NXP_IFC_RUN_TIME_ADDR + U(0x0000))
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#define NAND_FCR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0014))
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#define ROW0 (NXP_IFC_RUN_TIME_ADDR + U(0x003C))
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#define ROW1 (NXP_IFC_RUN_TIME_ADDR + U(0x004C))
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#define COL0 (NXP_IFC_RUN_TIME_ADDR + U(0x0044))
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#define COL1 (NXP_IFC_RUN_TIME_ADDR + U(0x0054))
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#define NAND_BC (NXP_IFC_RUN_TIME_ADDR + U(0x0108))
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#define NAND_FIR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0110))
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#define NAND_FIR1 (NXP_IFC_RUN_TIME_ADDR + U(0x0114))
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#define NAND_FIR2 (NXP_IFC_RUN_TIME_ADDR + U(0x0118))
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#define NAND_CSEL (NXP_IFC_RUN_TIME_ADDR + U(0x015C))
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#define NANDSEQ_STRT (NXP_IFC_RUN_TIME_ADDR + U(0x0164))
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#define NAND_EVTER_STAT (NXP_IFC_RUN_TIME_ADDR + U(0x016C))
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#define NAND_AUTOBOOT_TRGR (NXP_IFC_RUN_TIME_ADDR + U(0x0284))
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/* Size of SRAM Buffer */
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#define CSPR_PS U(0x00000180)
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#define CSPR_PS_SHIFT 7
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#define CSPR_PS_8 0x1 // Port Size 8 bit
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#define CSPR_PS_16 0x2 // Port Size 16 bit
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#define CSPR_PS_32 0x3 // Port Size 32 bit
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/* Chip Select Option Register NAND Machine */
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#define CSOR_NAND_PGS U(0x00380000)
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#define CSOR_NAND_PGS_SHIFT 19
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#define CSOR_NAND_PGS_512 U(0x00000000)
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#define CSOR_NAND_PGS_2K U(0x00080000)
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#define CSOR_NAND_PGS_4K U(0x00100000)
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#define CSOR_NAND_PGS_8K U(0x00180000)
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#define CSOR_NAND_PGS_16K U(0x00200000)
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#define CSOR_NAND_PB U(0x00000700)
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#define CSOR_NAND_PB_32 U(0x00000000)
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#define CSOR_NAND_PB_64 U(0x00000100)
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#define CSOR_NAND_PB_128 U(0x00000200)
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#define CSOR_NAND_PB_256 U(0x00000300)
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#define CSOR_NAND_PB_512 U(0x00000400)
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#define CSOR_NAND_PB_1024 U(0x00000500)
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#define CSOR_NAND_PB_2048 U(0x00000600)
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#define CSOR_NAND_PPB_32 32
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#define CSOR_NAND_PPB_64 64
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#define CSOR_NAND_PPB_128 128
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#define CSOR_NAND_PPB_256 256
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#define CSOR_NAND_PPB_512 512
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#define CSOR_NAND_PPB_1024 1024
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#define CSOR_NAND_PPB_2048 2048
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/* NAND Chip select register */
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#define NAND_CSEL_SHIFT 26
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#define NAND_COL_MS_SHIFT 31
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/* FCR - Flash Command Register */
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#define FCR_CMD0 U(0xFF000000)
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#define FCR_CMD0_SHIFT 24
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#define FCR_CMD1 U(0x00FF0000)
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#define FCR_CMD1_SHIFT 16
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#define FCR_CMD2 U(0x0000FF00)
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#define FCR_CMD2_SHIFT 8
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#define FCR_CMD3 U(0x000000FF)
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#define FCR_CMD3_SHIFT 0
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/* FIR - Flash Instruction Register Opcode */
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#define FIR_OP0 U(0xFC000000)
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#define FIR_OP0_SHIFT 26
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#define FIR_OP1 U(0x03F00000)
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#define FIR_OP1_SHIFT 20
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#define FIR_OP2 U(0x000FC000)
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#define FIR_OP2_SHIFT 14
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#define FIR_OP3 U(0x00003F00)
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#define FIR_OP3_SHIFT 8
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#define FIR_OP4 U(0x000000FC)
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#define FIR_OP4_SHIFT 2
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#define FIR_OP5 U(0xFC000000)
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#define FIR_OP5_SHIFT 26
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#define FIR_OP6 U(0x03F00000)
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#define FIR_OP6_SHIFT 20
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/* Instruction Opcode - 6 bits */
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#define FIR_OP_NOP 0x00
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#define FIR_OP_CA0 0x01 /* Issue current column address */
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#define FIR_OP_CA1 0x02 /* Issue current column address */
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#define FIR_OP_RA0 0x05 /* Issue current column address */
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#define FIR_OP_RA1 0x06 /* Issue current column address */
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#define FIR_OP_CMD0 0x09 /* Issue command from FCR[CMD0] */
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#define FIR_OP_CMD1 0x0a /* Issue command from FCR[CMD1] */
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#define FIR_OP_CMD2 0x0b /* Issue command from FCR[CMD2] */
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#define FIR_OP_CMD3 0x0c /* Issue command from FCR[CMD3] */
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#define FIR_OP_CW0 0x11 /* Wait then issue FCR[CMD0] */
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#define FIR_OP_CW1 0x12 /* Wait then issue FCR[CMD1] */
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#define FIR_OP_CW2 0x13 /* Wait then issue FCR[CMD1] */
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#define FIR_OP_CW3 0x14 /* Wait then issue FCR[CMD1] */
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#define FIR_OP_WBCD 0x19 /* Wait then read FBCR bytes */
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#define FIR_OP_RBCD 0x1a /* Wait then read 1 or 2 bytes */
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#define FIR_OP_BTRD 0x1b /* Wait then read 1 or 2 bytes */
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#define FIR_OP_RDSTAT 0x1c /* Wait then read 1 or 2 bytes */
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#define FIR_OP_NWAIT 0x1d /* Wait then read 1 or 2 bytes */
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#define FIR_OP_WFR 0x1e /* Wait then read 1 or 2 bytes */
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#define NAND_SEQ_STRT_FIR_STRT U(0x80000000)
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#define NAND_SEQ_STRT_FIR_STRT_SHIFT 31
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#define NAND_EVTER_STAT_FTOER U(0x08000000)
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#define NAND_EVTER_STAT_WPER U(0x04000000)
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#define NAND_EVTER_STAT_ECCER U(0x02000000)
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#define NAND_EVTER_STAT_DQSER U(0x01000000)
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#define NAND_EVTER_STAT_RCW_DN U(0x00008000)
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#define NAND_EVTER_STAT_BOOT_DN U(0x00004000)
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#define NAND_EVTER_STAT_RCW_DN U(0x00008000)
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#define NAND_EVTER_STAT_OPC_DN U(0x80000000)
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#define NAND_EVTER_STAT_BBI_SRCH_SEL U(0x00000800)
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#define NCFGR_BOOT U(0x80000000)
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#define NAND_AUTOBOOT_TRGR_RCW_LD U(0x80000000)
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#define NAND_AUTOBOOT_TRGR_BOOT_LD U(0x20000000)
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/* ECC ERROR STATUS Registers */
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#define NAND_RCW_LD U(0x80000000)
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#define NAND_BOOT_LD U(0x20000000)
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/*Other Temp Defines */
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/*256 bad Blocks supported */
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#define BBT_SIZE 256
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/*Standard NAND flash commands */
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#define NAND_CMD_READ0 0
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#define NAND_CMD_READ1 1
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#define NAND_CMD_READOOB 0x50
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/*Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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#define NAND_TIMEOUT_MS 40
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#define EMPTY_VAL_CHECK U(0xFFFFFFFF)
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#define EMPTY_VAL 0xFF
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#define MAIN 0
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#define SPARE 1
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#define GOOD_BLK 1
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#define BAD_BLK 0
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#define DIV_2 2
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#define ATTRIBUTE_PGSZ 0xa
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#define ATTRIBUTE_PPB 0xb
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#define CSPR_PORT_SIZE_8 (0x1 << 7)
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#define CSPR_PORT_SIZE_16 (0x2 << 7)
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#define CSPR_PORT_SIZE_32 (0x3 << 7)
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/* NAND specific */
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#define RCW_SRC_NAND_PORT_MASK U(0x00000080)
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#define NAND_DEFAULT_CSPR U(0x00000053)
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#define NAND_DEFAULT_CSOR U(0x0180C00C)
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#define NAND_DEFAULT_EXT_CSPR U(0x00000000)
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#define NAND_DEFAULT_EXT_CSOR U(0x00000000)
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#define NAND_DEFAULT_FTIM0 U(0x181c0c10)
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#define NAND_DEFAULT_FTIM1 U(0x5454141e)
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#define NAND_DEFAULT_FTIM2 U(0x03808034)
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#define NAND_DEFAULT_FTIM3 U(0x2c000000)
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#define NAND_CSOR_ECC_MODE_DISABLE U(0x00000000)
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#define NAND_CSOR_ECC_MODE0 U(0x84000000)
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#define NAND_CSOR_ECC_MODE1 U(0x94000000)
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#define NAND_CSOR_ECC_MODE2 U(0xa4000000)
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#define NAND_CSOR_ECC_MODE3 U(0xb4000000)
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#define NAND_CSOR_PAGE_SIZE_2K (0x1 << 19)
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#define NAND_CSOR_PAGE_SIZE_4K (0x2 << 19)
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#define NAND_CSOR_PAGE_SIZE_8K (0x3 << 19)
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#define NAND_CSOR_PAGE_SIZE_16K (0x4 << 19)
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#define NAND_CSOR_PPB_64 (0x1 << 8)
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#define NAND_CSOR_PPB_128 (0x2 << 8)
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#define NAND_CSOR_PPB_256 (0x3 << 8)
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#define NAND_CSOR_PPB_512 (0x4 << 8)
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/* BBI INDICATOR for NAND_2K(CFG_RCW_SRC[1]) for
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* devices greater than 2K page size(CFG_RCW_SRC[3])
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*/
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#define RCW_SRC_NAND_BBI_MASK U(0x00000008)
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#define RCW_SRC_NAND_BBI_MASK_NAND_2K U(0x00000002)
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#define NAND_BBI_ONFI_2K (0x1 << 1)
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#define NAND_BBI_ONFI (0x1 << 3)
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#define RCW_SRC_NAND_PAGE_MASK U(0x00000070)
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#define RCW_SRC_NAND_PAGE_MASK_NAND_2K U(0x0000000C)
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#define NAND_2K_XXX 0x00
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#define NAND_2K_64 0x04
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#define NAND_2K_128 0x08
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#define NAND_4K_128 0x10
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#define NAND_4K_256 0x20
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#define NAND_4K_512 0x30
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#define NAND_8K_128 0x40
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#define NAND_8K_256 0x50
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#define NAND_8K_512 0x60
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#define NAND_16K_512 0x70
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#define BLOCK_LEN_2K 2048
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#define RCW_SRC_NAND_ECC_MASK U(0x00000007)
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#define RCW_SRC_NAND_ECC_MASK_NAND_2K U(0x00000001)
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#define NAND_ECC_DISABLE 0x0
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#define NAND_ECC_4_520 0x1
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#define NAND_ECC_8_528 0x5
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#define NAND_ECC_24_1K 0x6
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#define NAND_ECC_40_1K 0x7
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#define NAND_SPARE_2K U(0x00000040)
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#define NAND_SPARE_4K_ECC_M0 U(0x00000080)
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#define NAND_SPARE_4K_ECC_M1 U(0x000000D2)
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#define NAND_SPARE_4K_ECC_M2 U(0x000000B0)
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#define NAND_SPARE_4K_ECC_M3 U(0x00000120)
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#define NAND_SPARE_8K_ECC_M0 U(0x00000088)
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#define NAND_SPARE_8K_ECC_M1 U(0x00000108)
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#define NAND_SPARE_8K_ECC_M2 U(0x00000158)
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#define NAND_SPARE_8K_ECC_M3 U(0x00000238)
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#define NAND_SPARE_16K_ECC_M0 U(0x00000108)
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#define NAND_SPARE_16K_ECC_M1 U(0x00000208)
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#define NAND_SPARE_16K_ECC_M2 U(0x000002A8)
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#define NAND_SPARE_16K_ECC_M3 U(0x00000468)
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struct nand_info {
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uintptr_t ifc_register_addr;
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uintptr_t ifc_region_addr;
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uint32_t page_size;
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uint32_t port_size;
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uint32_t blk_size;
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uint32_t ppb;
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uint32_t pi_width; /* Bits Required to index a page in block */
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uint32_t ral;
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uint32_t ibr_flow;
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uint32_t bbt[BBT_SIZE];
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uint32_t lgb; /* Last Good Block */
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uint32_t bbt_max; /* Total entries in bbt */
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uint32_t bzero_good;
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uint8_t bbs;
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uint8_t bad_marker_loc;
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uint8_t onfi_dev_flag;
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uint8_t init_time_boot_flag;
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uint8_t *buf;
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};
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struct ifc_regs {
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uint32_t ext_cspr;
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uint32_t cspr;
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uint32_t csor;
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uint32_t ext_csor;
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};
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struct sec_nand_info {
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uint32_t cspr_port_size;
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uint32_t csor_ecc_mode;
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uint32_t csor_page_size;
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uint32_t csor_ppb;
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uint32_t ext_csor_spare_size;
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uint32_t onfi_flag;
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};
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struct sec_nor_info {
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uint32_t cspr_port_size;
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uint32_t csor_nor_mode;
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uint32_t csor_adm_shift;
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uint32_t port_size;
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uint32_t addr_bits;
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};
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enum ifc_chip_sel {
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IFC_CS0,
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IFC_CS1,
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IFC_CS2,
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IFC_CS3,
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IFC_CS4,
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IFC_CS5,
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IFC_CS6,
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IFC_CS7,
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};
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enum ifc_ftims {
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IFC_FTIM0,
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IFC_FTIM1,
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IFC_FTIM2,
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IFC_FTIM3,
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};
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#ifdef NXP_IFC_BE
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#define nand_in32(a) bswap32(mmio_read_32((uintptr_t)a))
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#define nand_out32(a, v) mmio_write_32((uintptr_t)a, bswap32(v))
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#else
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#define nand_in32(a) mmio_read_32((uintptr_t)a)
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#define nand_out32(a, v) mmio_write_32((uintptr_t)a, v)
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#endif
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/* Read Write on IFC registers */
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static inline void write_reg(struct nand_info *nand, uint32_t reg, uint32_t val)
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{
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nand_out32(nand->ifc_register_addr + reg, val);
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}
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static inline uint32_t read_reg(struct nand_info *nand, uint32_t reg)
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{
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return nand_in32(nand->ifc_register_addr + reg);
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}
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#endif /* IFC_H */
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@ -0,0 +1,658 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <common/debug.h>
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#include <drivers/io/io_block.h>
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#include "ifc.h"
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <nxp_timer.h>
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/* Private structure for NAND driver data */
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static struct nand_info nand_drv_data;
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static int update_bbt(uint32_t idx, uint32_t blk, uint32_t *updated,
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struct nand_info *nand);
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static int nand_wait(struct nand_info *nand)
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{
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int timeout = 1;
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uint32_t neesr;
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unsigned long start_time;
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start_time = get_timer_val(0);
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while (get_timer_val(start_time) < NAND_TIMEOUT_MS) {
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/* clear the OPC event */
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neesr = read_reg(nand, NAND_EVTER_STAT);
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if (neesr & NAND_EVTER_STAT_OPC_DN) {
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write_reg(nand, NAND_EVTER_STAT, neesr);
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timeout = 0;
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/* check for other errors */
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if (neesr & NAND_EVTER_STAT_FTOER) {
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ERROR("%s NAND_EVTER_STAT_FTOER occurs\n",
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__func__);
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return -1;
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} else if (neesr & NAND_EVTER_STAT_ECCER) {
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ERROR("%s NAND_EVTER_STAT_ECCER occurs\n",
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__func__);
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return -1;
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} else if (neesr & NAND_EVTER_STAT_DQSER) {
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ERROR("%s NAND_EVTER_STAT_DQSER occurs\n",
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__func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (timeout) {
|
||||
ERROR("%s ERROR_NAND_TIMEOUT occurs\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t nand_get_port_size(struct nand_info *nand)
|
||||
{
|
||||
uint32_t port_size = U(0);
|
||||
uint32_t cs_reg;
|
||||
uint32_t cur_cs;
|
||||
|
||||
cur_cs = U(0);
|
||||
cs_reg = CSPR(cur_cs);
|
||||
port_size = (read_reg(nand, cs_reg) & CSPR_PS) >> CSPR_PS_SHIFT;
|
||||
switch (port_size) {
|
||||
case CSPR_PS_8:
|
||||
port_size = U(8);
|
||||
break;
|
||||
case CSPR_PS_16:
|
||||
port_size = U(16);
|
||||
break;
|
||||
case CSPR_PS_32:
|
||||
port_size = U(32);
|
||||
break;
|
||||
default:
|
||||
port_size = U(8);
|
||||
}
|
||||
|
||||
return port_size;
|
||||
}
|
||||
|
||||
static uint32_t nand_get_page_size(struct nand_info *nand)
|
||||
{
|
||||
uint32_t pg_size;
|
||||
uint32_t cs_reg;
|
||||
uint32_t cur_cs;
|
||||
|
||||
cur_cs = 0;
|
||||
cs_reg = CSOR(cur_cs);
|
||||
pg_size = read_reg(nand, cs_reg) & CSOR_NAND_PGS;
|
||||
switch (pg_size) {
|
||||
case CSOR_NAND_PGS_2K:
|
||||
pg_size = U(2048);
|
||||
break;
|
||||
case CSOR_NAND_PGS_4K:
|
||||
pg_size = U(4096);
|
||||
break;
|
||||
case CSOR_NAND_PGS_8K:
|
||||
pg_size = U(8192);
|
||||
break;
|
||||
case CSOR_NAND_PGS_16K:
|
||||
pg_size = U(16384);
|
||||
break;
|
||||
default:
|
||||
pg_size = U(512);
|
||||
}
|
||||
|
||||
return pg_size;
|
||||
}
|
||||
|
||||
static uint32_t nand_get_pages_per_blk(struct nand_info *nand)
|
||||
{
|
||||
uint32_t pages_per_blk;
|
||||
uint32_t cs_reg;
|
||||
uint32_t cur_cs;
|
||||
|
||||
cur_cs = 0;
|
||||
cs_reg = CSOR(cur_cs);
|
||||
pages_per_blk = (read_reg(nand, cs_reg) & CSOR_NAND_PB);
|
||||
switch (pages_per_blk) {
|
||||
case CSOR_NAND_PB_32:
|
||||
pages_per_blk = U(32);
|
||||
break;
|
||||
case CSOR_NAND_PB_64:
|
||||
pages_per_blk = U(64);
|
||||
break;
|
||||
case CSOR_NAND_PB_128:
|
||||
pages_per_blk = U(128);
|
||||
break;
|
||||
case CSOR_NAND_PB_256:
|
||||
pages_per_blk = U(256);
|
||||
break;
|
||||
case CSOR_NAND_PB_512:
|
||||
pages_per_blk = U(512);
|
||||
break;
|
||||
case CSOR_NAND_PB_1024:
|
||||
pages_per_blk = U(1024);
|
||||
break;
|
||||
case CSOR_NAND_PB_2048:
|
||||
pages_per_blk = U(2048);
|
||||
break;
|
||||
default:
|
||||
pages_per_blk = U(0);
|
||||
}
|
||||
|
||||
return pages_per_blk;
|
||||
}
|
||||
|
||||
static uint32_t get_page_index_width(uint32_t ppb)
|
||||
{
|
||||
switch (ppb) {
|
||||
case CSOR_NAND_PPB_32:
|
||||
return U(5);
|
||||
case CSOR_NAND_PPB_64:
|
||||
return U(6);
|
||||
case CSOR_NAND_PPB_128:
|
||||
return U(7);
|
||||
case CSOR_NAND_PPB_256:
|
||||
return U(8);
|
||||
case CSOR_NAND_PPB_512:
|
||||
return U(9);
|
||||
case CSOR_NAND_PPB_1024:
|
||||
return U(10);
|
||||
case CSOR_NAND_PPB_2048:
|
||||
return U(11);
|
||||
default:
|
||||
return U(5);
|
||||
}
|
||||
}
|
||||
|
||||
static void nand_get_params(struct nand_info *nand)
|
||||
{
|
||||
nand->port_size = nand_get_port_size(nand);
|
||||
|
||||
nand->page_size = nand_get_page_size(nand);
|
||||
|
||||
/*
|
||||
* Set Bad marker Location for LP / SP
|
||||
* Small Page : 8 Bit : 0x5
|
||||
* Small Page : 16 Bit : 0xa
|
||||
* Large Page : 8 /16 Bit : 0x0
|
||||
*/
|
||||
nand->bad_marker_loc = (nand->page_size == 512) ?
|
||||
((nand->port_size == 8) ? 0x5 : 0xa) : 0;
|
||||
|
||||
/* check for the device is ONFI compliant or not */
|
||||
nand->onfi_dev_flag =
|
||||
(read_reg(nand, NAND_EVTER_STAT) & NAND_EVTER_STAT_BBI_SRCH_SEL)
|
||||
? 1 : 0;
|
||||
|
||||
/* NAND Blk serached count for incremental Bad block search cnt */
|
||||
nand->bbs = 0;
|
||||
|
||||
/* pages per Block */
|
||||
nand->ppb = nand_get_pages_per_blk(nand);
|
||||
|
||||
/* Blk size */
|
||||
nand->blk_size = nand->page_size * nand->ppb;
|
||||
|
||||
/* get_page_index_width */
|
||||
nand->pi_width = get_page_index_width(nand->ppb);
|
||||
|
||||
/* bad block table init */
|
||||
nand->lgb = 0;
|
||||
nand->bbt_max = 0;
|
||||
nand->bzero_good = 0;
|
||||
memset(nand->bbt, EMPTY_VAL, BBT_SIZE * sizeof(nand->bbt[0]));
|
||||
}
|
||||
|
||||
static int nand_init(struct nand_info *nand)
|
||||
{
|
||||
uint32_t ncfgr = 0;
|
||||
|
||||
/* Get nand Parameters from IFC */
|
||||
nand_get_params(nand);
|
||||
|
||||
/* Clear all errors */
|
||||
write_reg(nand, NAND_EVTER_STAT, U(0xffffffff));
|
||||
|
||||
/*
|
||||
* Disable autoboot in NCFGR. Mapping will change from
|
||||
* physical to logical for SRAM buffer
|
||||
*/
|
||||
ncfgr = read_reg(nand, NCFGR);
|
||||
write_reg(nand, NCFGR, (ncfgr & ~NCFGR_BOOT));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nand_read_data(
|
||||
uintptr_t ifc_region_addr,
|
||||
uint32_t row_add,
|
||||
uint32_t col_add,
|
||||
uint32_t byte_cnt,
|
||||
uint8_t *data,
|
||||
uint32_t main_spare,
|
||||
struct nand_info *nand)
|
||||
{
|
||||
uint32_t page_size_add_bits = U(0);
|
||||
uint32_t page_add_in_actual, page_add;
|
||||
uintptr_t sram_addr_calc;
|
||||
int ret;
|
||||
uint32_t col_val;
|
||||
|
||||
/* Programming MS bit to read from spare area.*/
|
||||
col_val = (main_spare << NAND_COL_MS_SHIFT) | col_add;
|
||||
|
||||
write_reg(nand, NAND_BC, byte_cnt);
|
||||
|
||||
write_reg(nand, ROW0, row_add);
|
||||
write_reg(nand, COL0, col_val);
|
||||
|
||||
/* Program FCR for small Page */
|
||||
if (nand->page_size == U(512)) {
|
||||
if (byte_cnt == 0 ||
|
||||
(byte_cnt != 0 && main_spare == 0 && col_add <= 255)) {
|
||||
write_reg(nand, NAND_FCR0,
|
||||
(NAND_CMD_READ0 << FCR_CMD0_SHIFT));
|
||||
} else if (main_spare == 0) {
|
||||
write_reg(nand, NAND_FCR0,
|
||||
(NAND_CMD_READ1 << FCR_CMD0_SHIFT));
|
||||
} else {
|
||||
write_reg(nand, NAND_FCR0,
|
||||
(NAND_CMD_READOOB << FCR_CMD0_SHIFT));
|
||||
}
|
||||
|
||||
} else {
|
||||
/* Program FCR for Large Page */
|
||||
write_reg(nand, NAND_FCR0, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
|
||||
(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
|
||||
}
|
||||
if (nand->page_size == U(512)) {
|
||||
write_reg(nand, NAND_FIR0, ((FIR_OP_CW0 << FIR_OP0_SHIFT) |
|
||||
(FIR_OP_CA0 << FIR_OP1_SHIFT) |
|
||||
(FIR_OP_RA0 << FIR_OP2_SHIFT) |
|
||||
(FIR_OP_BTRD << FIR_OP3_SHIFT) |
|
||||
(FIR_OP_NOP << FIR_OP4_SHIFT)));
|
||||
write_reg(nand, NAND_FIR1, U(0x00000000));
|
||||
} else {
|
||||
write_reg(nand, NAND_FIR0, ((FIR_OP_CW0 << FIR_OP0_SHIFT) |
|
||||
(FIR_OP_CA0 << FIR_OP1_SHIFT) |
|
||||
(FIR_OP_RA0 << FIR_OP2_SHIFT) |
|
||||
(FIR_OP_CMD1 << FIR_OP3_SHIFT) |
|
||||
(FIR_OP_BTRD << FIR_OP4_SHIFT)));
|
||||
|
||||
write_reg(nand, NAND_FIR1, (FIR_OP_NOP << FIR_OP5_SHIFT));
|
||||
}
|
||||
write_reg(nand, NANDSEQ_STRT, NAND_SEQ_STRT_FIR_STRT);
|
||||
|
||||
ret = nand_wait(nand);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
/* calculate page_size_add_bits i.e bits
|
||||
* in sram address corresponding to area
|
||||
* within a page for sram
|
||||
*/
|
||||
if (nand->page_size == U(512))
|
||||
page_size_add_bits = U(10);
|
||||
else if (nand->page_size == U(2048))
|
||||
page_size_add_bits = U(12);
|
||||
else if (nand->page_size == U(4096))
|
||||
page_size_add_bits = U(13);
|
||||
else if (nand->page_size == U(8192))
|
||||
page_size_add_bits = U(14);
|
||||
else if (nand->page_size == U(16384))
|
||||
page_size_add_bits = U(15);
|
||||
|
||||
page_add = row_add;
|
||||
|
||||
page_add_in_actual = (page_add << page_size_add_bits) & U(0x0000FFFF);
|
||||
|
||||
if (byte_cnt == 0)
|
||||
col_add = U(0);
|
||||
|
||||
/* Calculate SRAM address for main and spare area */
|
||||
if (main_spare == 0)
|
||||
sram_addr_calc = ifc_region_addr | page_add_in_actual | col_add;
|
||||
else
|
||||
sram_addr_calc = ifc_region_addr | page_add_in_actual |
|
||||
(col_add + nand->page_size);
|
||||
|
||||
/* Depending Byte_count copy full page or partial page from SRAM */
|
||||
if (byte_cnt == 0)
|
||||
memcpy(data, (void *)sram_addr_calc,
|
||||
nand->page_size);
|
||||
else
|
||||
memcpy(data, (void *)sram_addr_calc, byte_cnt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nand_read(struct nand_info *nand, int32_t src_addr,
|
||||
uintptr_t dst, uint32_t size)
|
||||
{
|
||||
uint32_t log_blk = U(0);
|
||||
uint32_t pg_no = U(0);
|
||||
uint32_t col_off = U(0);
|
||||
uint32_t row_off = U(0);
|
||||
uint32_t byte_cnt = U(0);
|
||||
uint32_t read_cnt = U(0);
|
||||
uint32_t i = U(0);
|
||||
uint32_t updated = U(0);
|
||||
|
||||
int ret = 0;
|
||||
uint8_t *out = (uint8_t *)dst;
|
||||
|
||||
uint32_t pblk;
|
||||
|
||||
/* loop till size */
|
||||
while (size) {
|
||||
log_blk = (src_addr / nand->blk_size);
|
||||
pg_no = ((src_addr - (log_blk * nand->blk_size)) /
|
||||
nand->page_size);
|
||||
pblk = log_blk;
|
||||
|
||||
// iterate the bbt to find the block
|
||||
for (i = 0; i <= nand->bbt_max; i++) {
|
||||
if (nand->bbt[i] == EMPTY_VAL_CHECK) {
|
||||
ret = update_bbt(i, pblk, &updated, nand);
|
||||
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
/*
|
||||
* if table not updated and we reached
|
||||
* end of table
|
||||
*/
|
||||
if (!updated)
|
||||
break;
|
||||
}
|
||||
|
||||
if (pblk < nand->bbt[i])
|
||||
break;
|
||||
else if (pblk >= nand->bbt[i])
|
||||
pblk++;
|
||||
}
|
||||
|
||||
col_off = (src_addr % nand->page_size);
|
||||
if (col_off) {
|
||||
if ((col_off + size) < nand->page_size)
|
||||
byte_cnt = size;
|
||||
else
|
||||
byte_cnt = nand->page_size - col_off;
|
||||
|
||||
row_off = (pblk << nand->pi_width) | pg_no;
|
||||
|
||||
ret = nand_read_data(
|
||||
nand->ifc_region_addr,
|
||||
row_off,
|
||||
col_off,
|
||||
byte_cnt, out, MAIN, nand);
|
||||
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
} else {
|
||||
/*
|
||||
* fullpage/Partial Page
|
||||
* if byte_cnt = 0 full page
|
||||
* else partial page
|
||||
*/
|
||||
if (size < nand->page_size) {
|
||||
byte_cnt = size;
|
||||
read_cnt = size;
|
||||
} else {
|
||||
byte_cnt = nand->page_size;
|
||||
read_cnt = 0;
|
||||
}
|
||||
row_off = (pblk << nand->pi_width) | pg_no;
|
||||
|
||||
ret = nand_read_data(
|
||||
nand->ifc_region_addr,
|
||||
row_off,
|
||||
0,
|
||||
read_cnt, out, MAIN, nand);
|
||||
|
||||
if (ret != 0) {
|
||||
ERROR("Error from nand-read_data %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
src_addr += byte_cnt;
|
||||
out += byte_cnt;
|
||||
size -= byte_cnt;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int isgoodblock(uint32_t blk, uint32_t *gb, struct nand_info *nand)
|
||||
{
|
||||
uint8_t buf[2];
|
||||
int ret;
|
||||
uint32_t row_add;
|
||||
|
||||
*gb = 0;
|
||||
|
||||
/* read Page 0 of blk */
|
||||
ret = nand_read_data(
|
||||
nand->ifc_region_addr,
|
||||
blk << nand->pi_width,
|
||||
nand->bad_marker_loc,
|
||||
0x2, buf, 1, nand);
|
||||
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
/* For ONFI devices check Page 0 and Last page of block for
|
||||
* Bad Marker and for NON-ONFI Page 0 and 1 for Bad Marker
|
||||
*/
|
||||
row_add = (blk << nand->pi_width);
|
||||
if (nand->port_size == 8) {
|
||||
/* port size is 8 Bit */
|
||||
/* check if page 0 has 0xff */
|
||||
if (buf[0] == 0xff) {
|
||||
/* check page 1 */
|
||||
if (nand->onfi_dev_flag)
|
||||
ret = nand_read_data(
|
||||
nand->ifc_region_addr,
|
||||
row_add | (nand->ppb - 1),
|
||||
nand->bad_marker_loc,
|
||||
0x2, buf, SPARE, nand);
|
||||
else
|
||||
ret = nand_read_data(
|
||||
nand->ifc_region_addr,
|
||||
row_add | 1,
|
||||
nand->bad_marker_loc,
|
||||
0x2, buf, SPARE, nand);
|
||||
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
if (buf[0] == 0xff)
|
||||
*gb = GOOD_BLK;
|
||||
else
|
||||
*gb = BAD_BLK;
|
||||
} else {
|
||||
/* no, so it is bad blk */
|
||||
*gb = BAD_BLK;
|
||||
}
|
||||
} else {
|
||||
/* Port size 16-Bit */
|
||||
/* check if page 0 has 0xffff */
|
||||
if ((buf[0] == 0xff) &&
|
||||
(buf[1] == 0xff)) {
|
||||
/* check page 1 for 0xffff */
|
||||
if (nand->onfi_dev_flag) {
|
||||
ret = nand_read_data(
|
||||
nand->ifc_region_addr,
|
||||
row_add | (nand->ppb - 1),
|
||||
nand->bad_marker_loc,
|
||||
0x2, buf, SPARE, nand);
|
||||
} else {
|
||||
ret = nand_read_data(
|
||||
nand->ifc_region_addr,
|
||||
row_add | 1,
|
||||
nand->bad_marker_loc,
|
||||
0x2, buf, SPARE, nand);
|
||||
}
|
||||
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
if ((buf[0] == 0xff) &&
|
||||
(buf[1] == 0xff)) {
|
||||
*gb = GOOD_BLK;
|
||||
} else {
|
||||
*gb = BAD_BLK;
|
||||
}
|
||||
} else {
|
||||
/* no, so it is bad blk */
|
||||
*gb = BAD_BLK;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int update_bbt(uint32_t idx, uint32_t blk,
|
||||
uint32_t *updated, struct nand_info *nand)
|
||||
{
|
||||
uint32_t sblk;
|
||||
uint32_t lgb;
|
||||
int ret;
|
||||
|
||||
if (nand->bzero_good && blk == 0)
|
||||
return 0;
|
||||
|
||||
/* special case for lgb == 0 */
|
||||
/* if blk <= lgb retrun */
|
||||
if (nand->lgb != 0 && blk <= nand->lgb)
|
||||
return 0;
|
||||
|
||||
*updated = 0;
|
||||
|
||||
/* if blk is more than lgb, iterate from lgb till a good block
|
||||
* is found for blk
|
||||
*/
|
||||
|
||||
if (nand->lgb < blk)
|
||||
sblk = nand->lgb;
|
||||
else
|
||||
/* this is when lgb = 0 */
|
||||
sblk = blk;
|
||||
|
||||
|
||||
lgb = nand->lgb;
|
||||
|
||||
/* loop from blk to find a good block */
|
||||
while (1) {
|
||||
while (lgb <= sblk) {
|
||||
uint32_t gb = 0;
|
||||
|
||||
ret = isgoodblock(lgb, &gb, nand);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
/* special case block 0 is good then set this flag */
|
||||
if (lgb == 0 && gb == GOOD_BLK)
|
||||
nand->bzero_good = 1;
|
||||
|
||||
if (gb == BAD_BLK) {
|
||||
if (idx >= BBT_SIZE) {
|
||||
ERROR("NAND BBT Table full\n");
|
||||
return -1;
|
||||
}
|
||||
*updated = 1;
|
||||
nand->bbt[idx] = lgb;
|
||||
idx++;
|
||||
blk++;
|
||||
sblk++;
|
||||
if (idx > nand->bbt_max)
|
||||
nand->bbt_max = idx;
|
||||
}
|
||||
lgb++;
|
||||
}
|
||||
/* the access block found */
|
||||
if (sblk == blk) {
|
||||
/* when good block found update lgb */
|
||||
nand->lgb = blk;
|
||||
break;
|
||||
}
|
||||
sblk++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static size_t ifc_nand_read(int lba, uintptr_t buf, size_t size)
|
||||
{
|
||||
int ret;
|
||||
uint32_t page_size;
|
||||
uint32_t src_addr;
|
||||
struct nand_info *nand = &nand_drv_data;
|
||||
|
||||
page_size = nand_get_page_size(nand);
|
||||
src_addr = lba * page_size;
|
||||
ret = nand_read(nand, src_addr, buf, size);
|
||||
return ret ? 0 : size;
|
||||
}
|
||||
|
||||
static struct io_block_dev_spec ifc_nand_spec = {
|
||||
.buffer = {
|
||||
.offset = 0,
|
||||
.length = 0,
|
||||
},
|
||||
.ops = {
|
||||
.read = ifc_nand_read,
|
||||
},
|
||||
/*
|
||||
* Default block size assumed as 2K
|
||||
* Would be updated based on actual size
|
||||
*/
|
||||
.block_size = UL(2048),
|
||||
};
|
||||
|
||||
int ifc_nand_init(uintptr_t *block_dev_spec,
|
||||
uintptr_t ifc_region_addr,
|
||||
uintptr_t ifc_register_addr,
|
||||
size_t ifc_sram_size,
|
||||
uintptr_t ifc_nand_blk_offset,
|
||||
size_t ifc_nand_blk_size)
|
||||
{
|
||||
struct nand_info *nand = NULL;
|
||||
int ret;
|
||||
|
||||
nand = &nand_drv_data;
|
||||
memset(nand, 0, sizeof(struct nand_info));
|
||||
|
||||
nand->ifc_region_addr = ifc_region_addr;
|
||||
nand->ifc_register_addr = ifc_register_addr;
|
||||
|
||||
VERBOSE("nand_init\n");
|
||||
ret = nand_init(nand);
|
||||
if (ret) {
|
||||
ERROR("nand init failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ifc_nand_spec.buffer.offset = ifc_nand_blk_offset;
|
||||
ifc_nand_spec.buffer.length = ifc_nand_blk_size;
|
||||
|
||||
ifc_nand_spec.block_size = nand_get_page_size(nand);
|
||||
|
||||
VERBOSE("Page size is %ld\n", ifc_nand_spec.block_size);
|
||||
|
||||
*block_dev_spec = (uintptr_t)&ifc_nand_spec;
|
||||
|
||||
/* Adding NAND SRAM< Buffer in XLAT Table */
|
||||
mmap_add_region(ifc_region_addr, ifc_region_addr,
|
||||
ifc_sram_size, MT_DEVICE | MT_RW);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#
|
||||
# Copyright 2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
ifeq (${NAND_ADDED},)
|
||||
|
||||
NAND_ADDED := 1
|
||||
|
||||
NAND_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/ifc/nand
|
||||
|
||||
NAND_SOURCES := $(NAND_DRIVERS_PATH)/ifc_nand.c \
|
||||
drivers/io/io_block.c
|
||||
|
||||
PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/ifc
|
||||
|
||||
ifeq (${BL_COMM_IFC_NAND_NEEDED},yes)
|
||||
BL_COMMON_SOURCES += ${NAND_SOURCES}
|
||||
else
|
||||
ifeq (${BL2_IFC_NAND_NEEDED},yes)
|
||||
BL2_SOURCES += ${NAND_SOURCES}
|
||||
endif
|
||||
ifeq (${BL31_IFC_NAND_NEEDED},yes)
|
||||
BL31_SOURCES += ${NAND_SOURCES}
|
||||
endif
|
||||
endif
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IFC_NAND_H
|
||||
#define IFC_NAND_H
|
||||
|
||||
#define NXP_IFC_SRAM_BUFFER_SIZE UL(0x100000) /* 1M */
|
||||
|
||||
int ifc_nand_init(uintptr_t *block_dev_spec,
|
||||
uintptr_t ifc_region_addr,
|
||||
uintptr_t ifc_register_addr,
|
||||
size_t ifc_sram_size,
|
||||
uintptr_t ifc_nand_blk_offset,
|
||||
size_t ifc_nand_blk_size);
|
||||
|
||||
#endif /*IFC_NAND_H*/
|
||||
Loading…
Reference in New Issue