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Merge "plat/rockchip: enable power domains of rk3399 before reset" into integration

This commit is contained in:
Soby Mathew 2019-12-17 16:41:30 +00:00 committed by TrustedFirmware Code Review
parent 37ebe8e5ee b4899041e5
commit 287a81dfad
3 changed files with 22 additions and 0 deletions
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19
plat/rockchip/rk3399/drivers/pmu/pmu.c
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@ -400,6 +400,25 @@ static void pmu_power_domains_resume(void)
clk_gate_con_restore();
}
void pmu_power_domains_on(void)
{
clk_gate_con_disable();
pmu_set_power_domain(PD_VDU, pmu_pd_on);
pmu_set_power_domain(PD_VCODEC, pmu_pd_on);
pmu_set_power_domain(PD_RGA, pmu_pd_on);
pmu_set_power_domain(PD_IEP, pmu_pd_on);
pmu_set_power_domain(PD_EDP, pmu_pd_on);
pmu_set_power_domain(PD_GMAC, pmu_pd_on);
pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on);
pmu_set_power_domain(PD_HDCP, pmu_pd_on);
pmu_set_power_domain(PD_ISP1, pmu_pd_on);
pmu_set_power_domain(PD_ISP0, pmu_pd_on);
pmu_set_power_domain(PD_VO, pmu_pd_on);
pmu_set_power_domain(PD_TCPD1, pmu_pd_on);
pmu_set_power_domain(PD_TCPD0, pmu_pd_on);
pmu_set_power_domain(PD_GPU, pmu_pd_on);
}
void rk3399_flush_l2_b(void)
{
uint32_t wait_cnt = 0;

1
plat/rockchip/rk3399/drivers/pmu/pmu.h
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@ -136,5 +136,6 @@ struct pmu_slpdata_s {
extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT];
extern void sram_func_set_ddrctl_pll(uint32_t pll_src);
void pmu_power_domains_on(void);
#endif /* PMU_H */

2
plat/rockchip/rk3399/drivers/soc/soc.c
View File

@ -17,6 +17,7 @@
#include <dram.h>
#include <m0_ctl.h>
#include <plat_private.h>
#include <pmu.h>
#include <rk3399_def.h>
#include <secure.h>
#include <soc.h>
@ -327,6 +328,7 @@ void soc_global_soft_reset_init(void)
void __dead2 soc_global_soft_reset(void)
{
pmu_power_domains_on();
set_pll_slow_mode(VPLL_ID);
set_pll_slow_mode(NPLL_ID);
set_pll_slow_mode(GPLL_ID);