From 28f45bb83c854be321397455cefb2048f7839ad0 Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Thu, 26 Oct 2017 16:59:58 +0530 Subject: [PATCH] Tegra186: smmu: add support for backup multiple smmu regs Modifying smmu macros to pass base address of smmu so that it can be used with multiple smmus. Added macro for combining smmu backup regs that can be used for multiple smmus. Change-Id: I4f3bb83d66d5df14a3b91bc82f7fc26ec8e4592e Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/include/drivers/smmu.h | 199 +++++++++++++++++++---- plat/nvidia/tegra/soc/t186/plat_smmu.c | 138 +--------------- 2 files changed, 170 insertions(+), 167 deletions(-) diff --git a/plat/nvidia/tegra/include/drivers/smmu.h b/plat/nvidia/tegra/include/drivers/smmu.h index 41b0c5187..424a91aea 100644 --- a/plat/nvidia/tegra/include/drivers/smmu.h +++ b/plat/nvidia/tegra/include/drivers/smmu.h @@ -618,9 +618,9 @@ typedef struct smmu_regs { .val = 0x00000000U, \ } -#define smmu_make_gnsr0_sec_cfg(name) \ +#define smmu_make_gnsr0_sec_cfg(base_addr, name) \ { \ - .reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_ ## name, \ + .reg = base_addr + SMMU_GNSR0_ ## name, \ .val = 0x00000000U, \ } @@ -628,60 +628,199 @@ typedef struct smmu_regs { * On ARM-SMMU, conditional offset to access secure aliases of non-secure registers * is 0x400. So, add it to register address */ -#define smmu_make_gnsr0_nsec_cfg(name) \ +#define smmu_make_gnsr0_nsec_cfg(base_addr, name) \ { \ - .reg = TEGRA_SMMU0_BASE + 0x400U + SMMU_GNSR0_ ## name, \ + .reg = base_addr + 0x400U + SMMU_GNSR0_ ## name, \ .val = 0x00000000U, \ } -#define smmu_make_gnsr0_smr_cfg(n) \ +#define smmu_make_gnsr0_smr_cfg(base_addr, n) \ { \ - .reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_SMR ## n, \ + .reg = base_addr + SMMU_GNSR0_SMR ## n, \ .val = 0x00000000U, \ } -#define smmu_make_gnsr0_s2cr_cfg(n) \ +#define smmu_make_gnsr0_s2cr_cfg(base_addr, n) \ { \ - .reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_S2CR ## n, \ + .reg = base_addr + SMMU_GNSR0_S2CR ## n, \ .val = 0x00000000U, \ } -#define smmu_make_gnsr1_cbar_cfg(n) \ +#define smmu_make_gnsr1_cbar_cfg(base_addr, n) \ { \ - .reg = TEGRA_SMMU0_BASE + (1U << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \ + .reg = base_addr + (1U << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \ .val = 0x00000000U, \ } -#define smmu_make_gnsr1_cba2r_cfg(n) \ +#define smmu_make_gnsr1_cba2r_cfg(base_addr, n) \ { \ - .reg = TEGRA_SMMU0_BASE + (1U << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \ + .reg = base_addr + (1U << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \ .val = 0x00000000U, \ } -#define make_smmu_cb_cfg(name, n) \ +#define smmu_make_cb_cfg(base_addr, name, n) \ { \ - .reg = TEGRA_SMMU0_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \ + .reg = base_addr + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \ + SMMU_CBn_ ## name, \ .val = 0x00000000U, \ } -#define smmu_make_smrg_group(n) \ - smmu_make_gnsr0_smr_cfg(n), \ - smmu_make_gnsr0_s2cr_cfg(n), \ - smmu_make_gnsr1_cbar_cfg(n), \ - smmu_make_gnsr1_cba2r_cfg(n) /* don't put "," here. */ +#define smmu_make_smrg_group(base_addr, n) \ + smmu_make_gnsr0_smr_cfg(base_addr, n), \ + smmu_make_gnsr0_s2cr_cfg(base_addr, n), \ + smmu_make_gnsr1_cbar_cfg(base_addr, n), \ + smmu_make_gnsr1_cba2r_cfg(base_addr, n) /* don't put "," here. */ -#define smmu_make_cb_group(n) \ - make_smmu_cb_cfg(SCTLR, n), \ - make_smmu_cb_cfg(TCR2, n), \ - make_smmu_cb_cfg(TTBR0_LO, n), \ - make_smmu_cb_cfg(TTBR0_HI, n), \ - make_smmu_cb_cfg(TCR, n), \ - make_smmu_cb_cfg(PRRR_MAIR0, n),\ - make_smmu_cb_cfg(FSR, n), \ - make_smmu_cb_cfg(FAR_LO, n), \ - make_smmu_cb_cfg(FAR_HI, n), \ - make_smmu_cb_cfg(FSYNR0, n) /* don't put "," here. */ +#define smmu_make_cb_group(base_addr, n) \ + smmu_make_cb_cfg(base_addr, SCTLR, n), \ + smmu_make_cb_cfg(base_addr, TCR2, n), \ + smmu_make_cb_cfg(base_addr, TTBR0_LO, n), \ + smmu_make_cb_cfg(base_addr, TTBR0_HI, n), \ + smmu_make_cb_cfg(base_addr, TCR, n), \ + smmu_make_cb_cfg(base_addr, PRRR_MAIR0, n),\ + smmu_make_cb_cfg(base_addr, FSR, n), \ + smmu_make_cb_cfg(base_addr, FAR_LO, n), \ + smmu_make_cb_cfg(base_addr, FAR_HI, n), \ + smmu_make_cb_cfg(base_addr, FSYNR0, n) /* don't put "," here. */ + +#define smmu_make_cfg(base_addr) \ + smmu_make_gnsr0_nsec_cfg(base_addr, CR0), \ + smmu_make_gnsr0_sec_cfg(base_addr, IDR0), \ + smmu_make_gnsr0_sec_cfg(base_addr, IDR1), \ + smmu_make_gnsr0_sec_cfg(base_addr, IDR2), \ + smmu_make_gnsr0_nsec_cfg(base_addr, GFSR), \ + smmu_make_gnsr0_nsec_cfg(base_addr, GFSYNR0), \ + smmu_make_gnsr0_nsec_cfg(base_addr, GFSYNR1), \ + smmu_make_gnsr0_nsec_cfg(base_addr, TLBGSTATUS),\ + smmu_make_gnsr0_nsec_cfg(base_addr, PIDR2), \ + smmu_make_smrg_group(base_addr, 0), \ + smmu_make_smrg_group(base_addr, 1), \ + smmu_make_smrg_group(base_addr, 2), \ + smmu_make_smrg_group(base_addr, 3), \ + smmu_make_smrg_group(base_addr, 4), \ + smmu_make_smrg_group(base_addr, 5), \ + smmu_make_smrg_group(base_addr, 6), \ + smmu_make_smrg_group(base_addr, 7), \ + smmu_make_smrg_group(base_addr, 8), \ + smmu_make_smrg_group(base_addr, 9), \ + smmu_make_smrg_group(base_addr, 10), \ + smmu_make_smrg_group(base_addr, 11), \ + smmu_make_smrg_group(base_addr, 12), \ + smmu_make_smrg_group(base_addr, 13), \ + smmu_make_smrg_group(base_addr, 14), \ + smmu_make_smrg_group(base_addr, 15), \ + smmu_make_smrg_group(base_addr, 16), \ + smmu_make_smrg_group(base_addr, 17), \ + smmu_make_smrg_group(base_addr, 18), \ + smmu_make_smrg_group(base_addr, 19), \ + smmu_make_smrg_group(base_addr, 20), \ + smmu_make_smrg_group(base_addr, 21), \ + smmu_make_smrg_group(base_addr, 22), \ + smmu_make_smrg_group(base_addr, 23), \ + smmu_make_smrg_group(base_addr, 24), \ + smmu_make_smrg_group(base_addr, 25), \ + smmu_make_smrg_group(base_addr, 26), \ + smmu_make_smrg_group(base_addr, 27), \ + smmu_make_smrg_group(base_addr, 28), \ + smmu_make_smrg_group(base_addr, 29), \ + smmu_make_smrg_group(base_addr, 30), \ + smmu_make_smrg_group(base_addr, 31), \ + smmu_make_smrg_group(base_addr, 32), \ + smmu_make_smrg_group(base_addr, 33), \ + smmu_make_smrg_group(base_addr, 34), \ + smmu_make_smrg_group(base_addr, 35), \ + smmu_make_smrg_group(base_addr, 36), \ + smmu_make_smrg_group(base_addr, 37), \ + smmu_make_smrg_group(base_addr, 38), \ + smmu_make_smrg_group(base_addr, 39), \ + smmu_make_smrg_group(base_addr, 40), \ + smmu_make_smrg_group(base_addr, 41), \ + smmu_make_smrg_group(base_addr, 42), \ + smmu_make_smrg_group(base_addr, 43), \ + smmu_make_smrg_group(base_addr, 44), \ + smmu_make_smrg_group(base_addr, 45), \ + smmu_make_smrg_group(base_addr, 46), \ + smmu_make_smrg_group(base_addr, 47), \ + smmu_make_smrg_group(base_addr, 48), \ + smmu_make_smrg_group(base_addr, 49), \ + smmu_make_smrg_group(base_addr, 50), \ + smmu_make_smrg_group(base_addr, 51), \ + smmu_make_smrg_group(base_addr, 52), \ + smmu_make_smrg_group(base_addr, 53), \ + smmu_make_smrg_group(base_addr, 54), \ + smmu_make_smrg_group(base_addr, 55), \ + smmu_make_smrg_group(base_addr, 56), \ + smmu_make_smrg_group(base_addr, 57), \ + smmu_make_smrg_group(base_addr, 58), \ + smmu_make_smrg_group(base_addr, 59), \ + smmu_make_smrg_group(base_addr, 60), \ + smmu_make_smrg_group(base_addr, 61), \ + smmu_make_smrg_group(base_addr, 62), \ + smmu_make_smrg_group(base_addr, 63), \ + smmu_make_cb_group(base_addr, 0), \ + smmu_make_cb_group(base_addr, 1), \ + smmu_make_cb_group(base_addr, 2), \ + smmu_make_cb_group(base_addr, 3), \ + smmu_make_cb_group(base_addr, 4), \ + smmu_make_cb_group(base_addr, 5), \ + smmu_make_cb_group(base_addr, 6), \ + smmu_make_cb_group(base_addr, 7), \ + smmu_make_cb_group(base_addr, 8), \ + smmu_make_cb_group(base_addr, 9), \ + smmu_make_cb_group(base_addr, 10), \ + smmu_make_cb_group(base_addr, 11), \ + smmu_make_cb_group(base_addr, 12), \ + smmu_make_cb_group(base_addr, 13), \ + smmu_make_cb_group(base_addr, 14), \ + smmu_make_cb_group(base_addr, 15), \ + smmu_make_cb_group(base_addr, 16), \ + smmu_make_cb_group(base_addr, 17), \ + smmu_make_cb_group(base_addr, 18), \ + smmu_make_cb_group(base_addr, 19), \ + smmu_make_cb_group(base_addr, 20), \ + smmu_make_cb_group(base_addr, 21), \ + smmu_make_cb_group(base_addr, 22), \ + smmu_make_cb_group(base_addr, 23), \ + smmu_make_cb_group(base_addr, 24), \ + smmu_make_cb_group(base_addr, 25), \ + smmu_make_cb_group(base_addr, 26), \ + smmu_make_cb_group(base_addr, 27), \ + smmu_make_cb_group(base_addr, 28), \ + smmu_make_cb_group(base_addr, 29), \ + smmu_make_cb_group(base_addr, 30), \ + smmu_make_cb_group(base_addr, 31), \ + smmu_make_cb_group(base_addr, 32), \ + smmu_make_cb_group(base_addr, 33), \ + smmu_make_cb_group(base_addr, 34), \ + smmu_make_cb_group(base_addr, 35), \ + smmu_make_cb_group(base_addr, 36), \ + smmu_make_cb_group(base_addr, 37), \ + smmu_make_cb_group(base_addr, 38), \ + smmu_make_cb_group(base_addr, 39), \ + smmu_make_cb_group(base_addr, 40), \ + smmu_make_cb_group(base_addr, 41), \ + smmu_make_cb_group(base_addr, 42), \ + smmu_make_cb_group(base_addr, 43), \ + smmu_make_cb_group(base_addr, 44), \ + smmu_make_cb_group(base_addr, 45), \ + smmu_make_cb_group(base_addr, 46), \ + smmu_make_cb_group(base_addr, 47), \ + smmu_make_cb_group(base_addr, 48), \ + smmu_make_cb_group(base_addr, 49), \ + smmu_make_cb_group(base_addr, 50), \ + smmu_make_cb_group(base_addr, 51), \ + smmu_make_cb_group(base_addr, 52), \ + smmu_make_cb_group(base_addr, 53), \ + smmu_make_cb_group(base_addr, 54), \ + smmu_make_cb_group(base_addr, 55), \ + smmu_make_cb_group(base_addr, 56), \ + smmu_make_cb_group(base_addr, 57), \ + smmu_make_cb_group(base_addr, 58), \ + smmu_make_cb_group(base_addr, 59), \ + smmu_make_cb_group(base_addr, 60), \ + smmu_make_cb_group(base_addr, 61), \ + smmu_make_cb_group(base_addr, 62), \ + smmu_make_cb_group(base_addr, 63) /* don't put "," here. */ #define smmu_bypass_cfg \ { \ diff --git a/plat/nvidia/tegra/soc/t186/plat_smmu.c b/plat/nvidia/tegra/soc/t186/plat_smmu.c index 95f6def9b..b4a7fe596 100644 --- a/plat/nvidia/tegra/soc/t186/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t186/plat_smmu.c @@ -161,143 +161,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra186_smmu_context[] = { mc_make_sid_override_cfg(UFSHCR), mc_make_sid_override_cfg(NVENCSWR), mc_make_sid_override_cfg(AFIW), - smmu_make_gnsr0_nsec_cfg(CR0), - smmu_make_gnsr0_sec_cfg(IDR0), - smmu_make_gnsr0_sec_cfg(IDR1), - smmu_make_gnsr0_sec_cfg(IDR2), - smmu_make_gnsr0_nsec_cfg(GFSR), - smmu_make_gnsr0_nsec_cfg(GFSYNR0), - smmu_make_gnsr0_nsec_cfg(GFSYNR1), - smmu_make_gnsr0_nsec_cfg(TLBGSTATUS), - smmu_make_gnsr0_nsec_cfg(PIDR2), - smmu_make_smrg_group(0), - smmu_make_smrg_group(1), - smmu_make_smrg_group(2), - smmu_make_smrg_group(3), - smmu_make_smrg_group(4), - smmu_make_smrg_group(5), - smmu_make_smrg_group(6), - smmu_make_smrg_group(7), - smmu_make_smrg_group(8), - smmu_make_smrg_group(9), - smmu_make_smrg_group(10), - smmu_make_smrg_group(11), - smmu_make_smrg_group(12), - smmu_make_smrg_group(13), - smmu_make_smrg_group(14), - smmu_make_smrg_group(15), - smmu_make_smrg_group(16), - smmu_make_smrg_group(17), - smmu_make_smrg_group(18), - smmu_make_smrg_group(19), - smmu_make_smrg_group(20), - smmu_make_smrg_group(21), - smmu_make_smrg_group(22), - smmu_make_smrg_group(23), - smmu_make_smrg_group(24), - smmu_make_smrg_group(25), - smmu_make_smrg_group(26), - smmu_make_smrg_group(27), - smmu_make_smrg_group(28), - smmu_make_smrg_group(29), - smmu_make_smrg_group(30), - smmu_make_smrg_group(31), - smmu_make_smrg_group(32), - smmu_make_smrg_group(33), - smmu_make_smrg_group(34), - smmu_make_smrg_group(35), - smmu_make_smrg_group(36), - smmu_make_smrg_group(37), - smmu_make_smrg_group(38), - smmu_make_smrg_group(39), - smmu_make_smrg_group(40), - smmu_make_smrg_group(41), - smmu_make_smrg_group(42), - smmu_make_smrg_group(43), - smmu_make_smrg_group(44), - smmu_make_smrg_group(45), - smmu_make_smrg_group(46), - smmu_make_smrg_group(47), - smmu_make_smrg_group(48), - smmu_make_smrg_group(49), - smmu_make_smrg_group(50), - smmu_make_smrg_group(51), - smmu_make_smrg_group(52), - smmu_make_smrg_group(53), - smmu_make_smrg_group(54), - smmu_make_smrg_group(55), - smmu_make_smrg_group(56), - smmu_make_smrg_group(57), - smmu_make_smrg_group(58), - smmu_make_smrg_group(59), - smmu_make_smrg_group(60), - smmu_make_smrg_group(61), - smmu_make_smrg_group(62), - smmu_make_smrg_group(63), - smmu_make_cb_group(0), - smmu_make_cb_group(1), - smmu_make_cb_group(2), - smmu_make_cb_group(3), - smmu_make_cb_group(4), - smmu_make_cb_group(5), - smmu_make_cb_group(6), - smmu_make_cb_group(7), - smmu_make_cb_group(8), - smmu_make_cb_group(9), - smmu_make_cb_group(10), - smmu_make_cb_group(11), - smmu_make_cb_group(12), - smmu_make_cb_group(13), - smmu_make_cb_group(14), - smmu_make_cb_group(15), - smmu_make_cb_group(16), - smmu_make_cb_group(17), - smmu_make_cb_group(18), - smmu_make_cb_group(19), - smmu_make_cb_group(20), - smmu_make_cb_group(21), - smmu_make_cb_group(22), - smmu_make_cb_group(23), - smmu_make_cb_group(24), - smmu_make_cb_group(25), - smmu_make_cb_group(26), - smmu_make_cb_group(27), - smmu_make_cb_group(28), - smmu_make_cb_group(29), - smmu_make_cb_group(30), - smmu_make_cb_group(31), - smmu_make_cb_group(32), - smmu_make_cb_group(33), - smmu_make_cb_group(34), - smmu_make_cb_group(35), - smmu_make_cb_group(36), - smmu_make_cb_group(37), - smmu_make_cb_group(38), - smmu_make_cb_group(39), - smmu_make_cb_group(40), - smmu_make_cb_group(41), - smmu_make_cb_group(42), - smmu_make_cb_group(43), - smmu_make_cb_group(44), - smmu_make_cb_group(45), - smmu_make_cb_group(46), - smmu_make_cb_group(47), - smmu_make_cb_group(48), - smmu_make_cb_group(49), - smmu_make_cb_group(50), - smmu_make_cb_group(51), - smmu_make_cb_group(52), - smmu_make_cb_group(53), - smmu_make_cb_group(54), - smmu_make_cb_group(55), - smmu_make_cb_group(56), - smmu_make_cb_group(57), - smmu_make_cb_group(58), - smmu_make_cb_group(59), - smmu_make_cb_group(60), - smmu_make_cb_group(61), - smmu_make_cb_group(62), - smmu_make_cb_group(63), + smmu_make_cfg(TEGRA_SMMU0_BASE), smmu_bypass_cfg, /* TBU settings */ _END_OF_TABLE_, };