feat(plat/st): use FCONF to configure platform
Add required code to support FCONF on STM32MP1 platform. The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2. It will be used to configure the addresses where to load other binaries. BL2 should be agnostic of which BL32 is in the FIP (OP-TEE or SP_min), so optee_utils.c is always compiled, and some OP-TEE flags are removed. Change-Id: Id957b49b0117864136250bfc416664f815043ada Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
This commit is contained in:
Yann Gautier
parent
d9e0586b61
commit
29332bcd68
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@ -97,6 +97,10 @@ static io_mtd_dev_spec_t spi_nand_dev_spec = {
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static const io_dev_connector_t *spi_dev_con;
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#endif
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static const io_uuid_spec_t fw_config_uuid_spec = {
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.uuid = UUID_FW_CONFIG,
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};
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static const io_uuid_spec_t bl33_partition_spec = {
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.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33
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};
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@ -175,6 +179,11 @@ static const struct plat_io_policy policies[] = {
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.image_spec = (uintptr_t)&bl33_partition_spec,
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.check = open_fip
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},
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[FW_CONFIG_ID] = {
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.dev_handle = &fip_dev_handle,
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.image_spec = (uintptr_t)&fw_config_uuid_spec,
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.check = open_fip
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},
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[TOS_FW_CONFIG_ID] = {
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.dev_handle = &fip_dev_handle,
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.image_spec = (uintptr_t)&tos_fw_config_uuid_spec,
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@ -5,6 +5,7 @@
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <platform_def.h>
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@ -24,6 +25,8 @@
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#include <drivers/st/stm32mp1_clk.h>
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#include <drivers/st/stm32mp1_pwr.h>
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#include <drivers/st/stm32mp1_ram.h>
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#include <lib/fconf/fconf.h>
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#include <lib/fconf/fconf_dyn_cfg_getter.h>
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#include <lib/mmio.h>
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#include <lib/optee_utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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@ -341,10 +344,76 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
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bl_mem_params_node_t *bl32_mem_params;
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bl_mem_params_node_t *pager_mem_params __unused;
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bl_mem_params_node_t *paged_mem_params __unused;
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#if !STM32MP_USE_STM32IMAGE
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const struct dyn_cfg_dtb_info_t *config_info;
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bl_mem_params_node_t *tos_fw_mem_params;
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unsigned int i;
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unsigned long long ddr_top __unused;
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const unsigned int image_ids[] = {
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BL32_IMAGE_ID,
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BL33_IMAGE_ID,
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HW_CONFIG_ID,
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TOS_FW_CONFIG_ID,
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};
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#endif /* !STM32MP_USE_STM32IMAGE */
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assert(bl_mem_params != NULL);
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switch (image_id) {
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#if !STM32MP_USE_STM32IMAGE
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case FW_CONFIG_ID:
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/* Set global DTB info for fixed fw_config information */
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set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID);
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fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
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/* Iterate through all the fw config IDs */
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for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
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bl_mem_params = get_bl_mem_params_node(image_ids[i]);
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assert(bl_mem_params != NULL);
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config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
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if (config_info == NULL) {
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continue;
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}
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bl_mem_params->image_info.image_base = config_info->config_addr;
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bl_mem_params->image_info.image_max_size = config_info->config_max_size;
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bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
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switch (image_ids[i]) {
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case BL32_IMAGE_ID:
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bl_mem_params->ep_info.pc = config_info->config_addr;
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/* In case of OPTEE, initialize address space with tos_fw addr */
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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pager_mem_params->image_info.image_base = config_info->config_addr;
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pager_mem_params->image_info.image_max_size =
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config_info->config_max_size;
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/* Init base and size for pager if exist */
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
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(dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
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STM32MP_DDR_SHMEM_SIZE);
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paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
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break;
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case BL33_IMAGE_ID:
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bl_mem_params->ep_info.pc = config_info->config_addr;
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break;
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case HW_CONFIG_ID:
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case TOS_FW_CONFIG_ID:
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break;
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default:
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return -EINVAL;
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}
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}
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break;
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#endif /* !STM32MP_USE_STM32IMAGE */
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case BL32_IMAGE_ID:
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if (optee_header_is_valid(bl_mem_params->image_info.image_base)) {
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/* BL32 is OP-TEE header */
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@ -380,6 +449,9 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
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} else {
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#if !STM32MP_USE_STM32IMAGE
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bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
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tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID);
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bl_mem_params->image_info.image_max_size +=
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tos_fw_mem_params->image_info.image_max_size;
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#endif /* !STM32MP_USE_STM32IMAGE */
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bl_mem_params->ep_info.args.arg0 = 0;
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}
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@ -19,6 +19,22 @@
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* the next executable image id.
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******************************************************************************/
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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/* Fill FW_CONFIG related information if it exists */
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{
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.image_id = FW_CONFIG_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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VERSION_2, entry_point_info_t,
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SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = STM32MP_FW_CONFIG_BASE,
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.image_info.image_max_size = STM32MP_FW_CONFIG_MAX_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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/* Fill BL32 related information */
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{
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.image_id = BL32_IMAGE_ID,
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@ -27,25 +43,17 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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/* Updated at runtime if OP-TEE is loaded */
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.ep_info.pc = STM32MP_BL32_BASE,
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.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
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SPSR_E_LITTLE,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP),
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/* Updated at runtime if OP-TEE is loaded */
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.image_info.image_base = STM32MP_BL32_BASE,
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.image_info.image_max_size = STM32MP_BL32_SIZE,
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IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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#if defined(AARCH32_SP_OPTEE)
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/* Fill BL32 external 1 image related information */
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{
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.image_id = BL32_EXTRA1_IMAGE_ID,
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@ -74,7 +82,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#endif /* AARCH32_SP_OPTEE */
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/* Fill HW_CONFIG related information if it exists */
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{
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.image_id = HW_CONFIG_ID,
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@ -83,15 +91,12 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
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NON_SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t,
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0U),
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.image_info.image_base = STM32MP_HW_CONFIG_BASE,
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.image_info.image_max_size =
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PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_HW_CONFIG_BASE,
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IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#if !defined(AARCH32_SP_OPTEE)
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/* Fill TOS_FW_CONFIG related information if it exists */
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{
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.image_id = TOS_FW_CONFIG_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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@ -99,13 +104,11 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
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SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t,
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0U),
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IMAGE_ATTRIB_SKIP_LOADING),
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.image_info.image_base = STM32MP_BL32_DTB_BASE,
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.image_info.image_max_size = STM32MP_BL32_DTB_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#endif
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/* Fill BL33 related information */
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{
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.image_id = BL33_IMAGE_ID,
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@ -114,17 +117,13 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
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VERSION_2, entry_point_info_t,
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NON_SECURE | EXECUTABLE),
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.ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET,
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.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
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SPSR_E_LITTLE,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0U),
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.image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET,
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.image_info.image_max_size = STM32MP_DDR_MAX_SIZE -
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(PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE),
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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}
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@ -70,6 +70,7 @@ BL32_DTSI := stm32mp15-bl32.dtsi
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FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME)))
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endif
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endif
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DTC_CPPFLAGS += ${INCLUDES}
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DTC_FLAGS += -Wno-unit_address_vs_reg
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# Macros and rules to build TF binary
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@ -92,6 +93,13 @@ STM32IMAGE_SRC := ${STM32IMAGEPATH}/stm32image.c
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ifneq (${STM32MP_USE_STM32IMAGE},1)
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FIP_DEPS += dtbs
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STM32MP_HW_CONFIG := ${BL33_CFG}
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STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
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STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
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ifneq (${AARCH32_SP},none)
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FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
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endif
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# Add the FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
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# Add the HW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_HW_CONFIG},--hw-config))
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ifeq ($(AARCH32_SP),sp_min)
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@ -185,6 +193,8 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \
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ifneq (${STM32MP_USE_STM32IMAGE},1)
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BL2_SOURCES += drivers/io/io_fip.c \
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lib/fconf/fconf.c \
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lib/fconf/fconf_dyn_cfg_getter.c \
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plat/st/common/bl2_io_storage.c \
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plat/st/stm32mp1/plat_bl2_mem_params_desc.c
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else
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@ -45,6 +45,7 @@ void sp_min_plat_fiq_handler(uint32_t id)
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{
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switch (id & INT_ID_MASK) {
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case STM32MP1_IRQ_TZC400:
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tzc400_init(STM32MP1_TZC_BASE);
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(void)tzc400_it_handler();
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panic();
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break;
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@ -117,6 +118,11 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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struct dt_node_info dt_uart_info;
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int result;
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bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
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#if STM32MP_USE_STM32IMAGE
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uintptr_t dt_addr = STM32MP_DTB_BASE;
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#else
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uintptr_t dt_addr = arg1;
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#endif
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/* Imprecise aborts can be masked in NonSecure */
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write_scr(read_scr() | SCR_AW_BIT);
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@ -156,7 +162,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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bl_params = bl_params->next_params_info;
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}
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if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
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if (dt_open_and_check(dt_addr) < 0) {
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panic();
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}
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@ -195,9 +201,6 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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******************************************************************************/
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void sp_min_platform_setup(void)
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{
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/* Initialize tzc400 after DDR initialization */
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stm32mp1_security_setup();
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generic_delay_timer_init();
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stm32mp1_gic_init();
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@ -87,13 +87,6 @@
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/* DDR configuration */
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#define STM32MP_DDR_BASE U(0xC0000000)
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#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
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#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
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#else
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#define STM32MP_DDR_S_SIZE U(0)
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#define STM32MP_DDR_SHMEM_SIZE U(0)
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#endif
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/* DDR power initializations */
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#ifndef __ASSEMBLER__
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@ -7,10 +7,14 @@
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#ifndef STM32MP1_FIP_DEF_H
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#define STM32MP1_FIP_DEF_H
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#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
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#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
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#define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */
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#define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
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#define STM32MP_BL32_SIZE U(0x00019000) /* 100 KB for BL32 */
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#define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
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#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */
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#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */
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#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
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@ -25,6 +29,7 @@
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#define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \
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STM32MP_BL32_DTB_SIZE)
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#if defined(IMAGE_BL2)
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#define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
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#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
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@ -41,6 +46,9 @@
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STM32MP_OPTEE_BASE)
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#endif
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#define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \
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STM32MP_SYSRAM_SIZE - \
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PAGE_SIZE)
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#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
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STM32MP_BL33_MAX_SIZE)
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@ -7,6 +7,14 @@
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#ifndef STM32MP1_STM32IMAGE_DEF_H
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#define STM32MP1_STM32IMAGE_DEF_H
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
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#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
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#else
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#define STM32MP_DDR_S_SIZE U(0)
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#define STM32MP_DDR_SHMEM_SIZE U(0)
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#endif
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#define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */
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#define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
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