From 2973dc5df85b11fac44a1c329b7c85daf1666889 Mon Sep 17 00:00:00 2001 From: Jeremy Linton Date: Wed, 18 Nov 2020 10:17:15 -0600 Subject: [PATCH] rpi4: update the iobase constant The PCIe root port is outside of the current RPi MMIO regions, so we need to adjust the address map. Given much of the code depends on the legacy IOBASE lets separate that from the actual MMIO begin/end. Signed-off-by: Jeremy Linton Change-Id: Id65460ae58556bd8826dba08bbad79953e2a7c0b --- plat/rpi/rpi4/include/rpi_hw.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h index 718510610..0430d464d 100644 --- a/plat/rpi/rpi4/include/rpi_hw.h +++ b/plat/rpi/rpi4/include/rpi_hw.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,14 +13,16 @@ * Peripherals */ -#define RPI_IO_BASE ULL(0xFE000000) -#define RPI_IO_SIZE ULL(0x02000000) +#define RPI_IO_BASE ULL(0xFC000000) +#define RPI_IO_SIZE ULL(0x04000000) + +#define RPI_LEGACY_BASE (ULL(0x02000000) + RPI_IO_BASE) /* * ARM <-> VideoCore mailboxes */ #define RPI3_MBOX_OFFSET ULL(0x0000B880) -#define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET) +#define RPI3_MBOX_BASE (RPI_LEGACY_BASE + RPI3_MBOX_OFFSET) /* VideoCore -> ARM */ #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) @@ -41,7 +43,7 @@ * Power management, reset controller, watchdog. */ #define RPI3_IO_PM_OFFSET ULL(0x00100000) -#define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET) +#define RPI3_PM_BASE (RPI_LEGACY_BASE + RPI3_IO_PM_OFFSET) /* Registers on top of RPI3_PM_BASE. */ #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) #define RPI3_PM_RSTS_OFFSET ULL(0x00000020) @@ -62,7 +64,7 @@ * Hardware random number generator. */ #define RPI3_IO_RNG_OFFSET ULL(0x00104000) -#define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET) +#define RPI3_RNG_BASE (RPI_LEGACY_BASE + RPI3_IO_RNG_OFFSET) #define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) #define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) #define RPI3_RNG_DATA_OFFSET ULL(0x00000008) @@ -82,22 +84,22 @@ * There is also a PL011 UART, multiplexed to the same pins. */ #define RPI4_IO_MINI_UART_OFFSET ULL(0x00215040) -#define RPI4_MINI_UART_BASE (RPI_IO_BASE + RPI4_IO_MINI_UART_OFFSET) +#define RPI4_MINI_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_MINI_UART_OFFSET) #define RPI4_IO_PL011_UART_OFFSET ULL(0x00201000) -#define RPI4_PL011_UART_BASE (RPI_IO_BASE + RPI4_IO_PL011_UART_OFFSET) +#define RPI4_PL011_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_PL011_UART_OFFSET) #define RPI4_PL011_UART_CLOCK ULL(48000000) /* * GPIO controller */ #define RPI3_IO_GPIO_OFFSET ULL(0x00200000) -#define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET) +#define RPI3_GPIO_BASE (RPI_LEGACY_BASE + RPI3_IO_GPIO_OFFSET) /* * SDHost controller */ #define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) -#define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET) +#define RPI3_SDHOST_BASE (RPI_LEGACY_BASE + RPI3_IO_SDHOST_OFFSET) /* * GIC interrupt controller