andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Enable ARMv8.6-ECV Self-Synch when booting to EL2 

Enhanced Counter Virtualization, ECV, is an architecture extension introduced
in ARMv8.6. This extension allows the hypervisor, at EL2, to setup
self-synchronizing views of the timers for it's EL1 Guests. This patch pokes the
control register to enable this extension when booting a hypervisor at EL2.

Change-Id: I4e929ecdf400cea17eff1de5cf8704aa7e40973d
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
This commit is contained in:
Jimmy Brisson 2020-04-16 10:48:02 -05:00
parent 110ee4330a
commit 29d0ee542d
3 changed files with 21 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
include/arch/aarch64/arch.h
View File

@ -211,6 +211,12 @@
#define PARANGE_0101 U(48)
#define PARANGE_0110 U(52)
#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
@ -329,6 +335,7 @@
#define SCR_TWEDEL_SHIFT U(30)
#define SCR_TWEDEL_MASK ULL(0xf)
#define SCR_TWEDEn_BIT (UL(1) << 29)
#define SCR_ECVEN_BIT (U(1) << 28)
#define SCR_FGTEN_BIT (U(1) << 27)
#define SCR_ATA_BIT (U(1) << 26)
#define SCR_FIEN_BIT (U(1) << 21)

6
include/arch/aarch64/arch_features.h
View File

@ -70,6 +70,12 @@ static inline bool is_armv8_6_fgt_present(void)
ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED;
}
static inline unsigned long int get_armv8_6_ecv_support(void)
{
return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) &
ID_AA64MMFR0_EL1_ECV_MASK);
}
/*
* Return MPAM version:
*

8
lib/el3_runtime/aarch64/context_mgmt.c
View File

@ -176,6 +176,9 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
* SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
* same conditions as HVC instructions and when the processor supports
* ARMv8.6-FGT.
* SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
* CNTPOFF_EL2 register under the same conditions as HVC instructions
* and when the processor supports ECV.
*/
if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
|| ((GET_RW(ep->spsr) != MODE_RW_64)
@ -185,6 +188,11 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
if (is_armv8_6_fgt_present()) {
scr_el3 |= SCR_FGTEN_BIT;
}
if (get_armv8_6_ecv_support()
== ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) {
scr_el3 |= SCR_ECVEN_BIT;
}
}
/* Enable S-EL2 if the next EL is EL2 and security state is secure */