juno: Initialise GIC
Signed-off-by: Jon Medhurst <tixy@linaro.org>
This commit is contained in:
Jon Medhurst
Sandrine Bailleux
parent
39fa81bc37
commit
29dfa23b0f
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@ -28,120 +28,17 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include <arch_helpers.h>
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#include <platform.h>
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#include <gic.h>
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#include <debug.h>
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/*******************************************************************************
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* TODO: Revisit if priorities are being set such that no non-secure interrupt
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* can have a higher priority than a secure one as recommended in the GICv2 spec
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******************************************************************************/
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/*******************************************************************************
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* This function does some minimal GICv3 configuration. The Firmware itself does
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* not fully support GICv3 at this time and relies on GICv2 emulation as
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* provided by GICv3. This function allows software (like Linux) in later stages
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* to use full GICv3 features.
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******************************************************************************/
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void gicv3_cpuif_setup(void)
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{
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unsigned int scr_val, val;
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uintptr_t base;
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/*
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* When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
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* bit set. In order to allow interrupts to get routed to the CPU we
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* need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
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* to clear (GICv3 Architecture specification 5.4.23).
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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*/
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base = gicv3_get_rdist(GICR_BASE, read_mpidr());
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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* configured.
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*/
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panic();
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}
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val = gicr_read_waker(base);
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val &= ~WAKER_PS;
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gicr_write_waker(base, val);
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dsb();
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/* We need to wait for ChildrenAsleep to clear. */
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val = gicr_read_waker(base);
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while (val & WAKER_CA) {
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val = gicr_read_waker(base);
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}
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/*
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* We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
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* Restore SCR_EL3.NS again before exit.
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*/
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scr_val = read_scr();
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write_scr(scr_val | SCR_NS_BIT);
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/*
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* By default EL2 and NS-EL1 software should be able to enable GICv3
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* System register access without any configuration at EL3. But it turns
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* out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So
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* we need to set it here again. In order to do that we need to enable
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* register access. We leave it enabled as it should be fine and might
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* prevent problems with later software trying to access GIC System
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* Registers.
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*/
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val = read_icc_sre_el3();
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write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
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val = read_icc_sre_el2();
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write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
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write_icc_pmr_el1(GIC_PRI_MASK);
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/* Restore SCR_EL3 */
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write_scr(scr_val);
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}
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/*******************************************************************************
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* This function does some minimal GICv3 configuration when cores go
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* down.
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******************************************************************************/
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void gicv3_cpuif_deactivate(void)
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{
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unsigned int val;
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uintptr_t base;
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/*
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* When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
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* wait for GICR_WAKER.ChildrenAsleep to get set.
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* (GICv3 Architecture specification 5.4.23).
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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*/
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base = gicv3_get_rdist(GICR_BASE, read_mpidr());
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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* configured.
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*/
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panic();
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}
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val = gicr_read_waker(base);
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val |= WAKER_PS;
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gicr_write_waker(base, val);
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dsb();
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/* We need to wait for ChildrenAsleep to set. */
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val = gicr_read_waker(base);
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while ((val & WAKER_CA) == 0) {
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val = gicr_read_waker(base);
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}
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}
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/* Value used to initialise Non-Secure irq priorities four at a time */
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#define DEFAULT_NS_PRIORITY_X4 \
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(GIC_HIGHEST_NS_PRIORITY | \
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(GIC_HIGHEST_NS_PRIORITY << 8) | \
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(GIC_HIGHEST_NS_PRIORITY << 16) | \
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(GIC_HIGHEST_NS_PRIORITY << 24))
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/*******************************************************************************
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@ -152,21 +49,11 @@ void gic_cpuif_setup(unsigned int gicc_base)
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{
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unsigned int val;
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val = gicc_read_iidr(gicc_base);
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/*
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* If GICv3 we need to do a bit of additional setup. We want to
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* allow default GICv2 behaviour but allow the next stage to
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* enable full gicv3 features.
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
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gicv3_cpuif_setup();
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}
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val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gicc_write_pmr(gicc_base, GIC_PRI_MASK);
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val = ENABLE_GRP0 | FIQ_EN;
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val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0;
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val |= FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(gicc_base, val);
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}
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@ -184,16 +71,15 @@ void gic_cpuif_deactivate(unsigned int gicc_base)
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(gicc_base, val);
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}
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val = gicc_read_iidr(gicc_base);
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static void gic_set_secure(unsigned int gicd_base, unsigned id)
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{
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/* Set interrupt as Group 0 */
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gicd_clr_igroupr(gicd_base, id);
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/*
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* If GICv3 we need to do a bit of additional setup. Make sure the
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* RDIST is put to sleep.
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
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gicv3_cpuif_deactivate();
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}
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/* Set priority to max */
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gicd_set_ipriorityr(gicd_base, id, GIC_HIGHEST_SEC_PRIORITY);
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}
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/*******************************************************************************
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@ -202,37 +88,31 @@ void gic_cpuif_deactivate(unsigned int gicc_base)
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******************************************************************************/
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void gic_pcpu_distif_setup(unsigned int gicd_base)
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{
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gicd_write_igroupr(gicd_base, 0, ~0);
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unsigned i;
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gicd_clr_igroupr(gicd_base, IRQ_SEC_PHY_TIMER);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_0);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_1);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_2);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_3);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_4);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_5);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_6);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_7);
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/* Mark all 32 PPI interrupts as Group 1 (non-secure) */
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mmio_write_32(gicd_base + GICD_IGROUPR, 0xffffffffu);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY);
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/* Setup PPI priorities doing four at a time */
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for (i = 0; i < 32; i += 4)
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mmio_write_32(gicd_base + GICD_IPRIORITYR + i, DEFAULT_NS_PRIORITY_X4);
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gicd_set_isenabler(gicd_base, IRQ_SEC_PHY_TIMER);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_0);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_1);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_2);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_3);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_4);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_5);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_6);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_7);
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/* Configure those PPIs we want as secure, and enable them. */
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static const char sec_irq[] = {
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IRQ_SEC_PHY_TIMER,
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IRQ_SEC_SGI_0,
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IRQ_SEC_SGI_1,
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IRQ_SEC_SGI_2,
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IRQ_SEC_SGI_3,
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IRQ_SEC_SGI_4,
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IRQ_SEC_SGI_5,
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IRQ_SEC_SGI_6,
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IRQ_SEC_SGI_7
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};
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for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++) {
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gic_set_secure(gicd_base, sec_irq[i]);
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gicd_set_isenabler(gicd_base, sec_irq[i]);
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}
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}
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/*******************************************************************************
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@ -240,33 +120,46 @@ void gic_pcpu_distif_setup(unsigned int gicd_base)
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* cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
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* then enables the secure GIC distributor interface.
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******************************************************************************/
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void gic_distif_setup(unsigned int gicd_base)
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static void gic_distif_setup(unsigned int gicd_base)
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{
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unsigned int ctr, num_ints, ctlr;
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unsigned int i, ctlr;
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const unsigned int ITLinesNumber =
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gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
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/* Disable the distributor before going further */
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ctlr = gicd_read_ctlr(gicd_base);
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ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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gicd_write_ctlr(gicd_base, ctlr);
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/*
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* Mark out non-secure interrupts. Calculate number of
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* IGROUPR registers to consider. Will be equal to the
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* number of IT_LINES
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*/
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num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
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num_ints++;
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for (ctr = 0; ctr < num_ints; ctr++)
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gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0);
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/* Mark all lines of SPIs as Group 1 (non-secure) */
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for (i = 0; i < ITLinesNumber; i++)
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mmio_write_32(gicd_base + GICD_IGROUPR + 4 + i * 4, 0xffffffffu);
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/* Configure secure interrupts now */
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gicd_clr_igroupr(gicd_base, IRQ_TZ_WDOG);
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gicd_set_ipriorityr(gicd_base, IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY);
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/* Setup SPI priorities doing four at a time */
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for (i = 0; i < ITLinesNumber * 32; i += 4)
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mmio_write_32(gicd_base + GICD_IPRIORITYR + 32 + i, DEFAULT_NS_PRIORITY_X4);
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/* Configure the SPIs we want as secure */
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static const char sec_irq[] = {
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IRQ_MHU,
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IRQ_GPU_SMMU_0,
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IRQ_GPU_SMMU_1,
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IRQ_ETR_SMMU,
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IRQ_TZC400,
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IRQ_TZ_WDOG
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};
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for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++)
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gic_set_secure(gicd_base, sec_irq[i]);
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/* Route watchdog interrupt to this CPU and enable it. */
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gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG,
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platform_get_core_pos(read_mpidr()));
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gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG);
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/* Now setup the PPIs */
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gic_pcpu_distif_setup(gicd_base);
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/* Enable Group 0 (secure) interrupts */
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gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0);
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}
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@ -171,7 +171,15 @@
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#define GICH_BASE 0x2c04f000
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#define GICV_BASE 0x2c06f000
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#define IRQ_TZ_WDOG 86
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#define IRQ_MHU 69
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#define IRQ_GPU_SMMU_0 71
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#define IRQ_GPU_SMMU_1 73
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#define IRQ_ETR_SMMU 75
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#define IRQ_TZC400 80
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#define IRQ_TZ_WDOG 86
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#define IRQ_SEC_PHY_TIMER 29
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#define IRQ_SEC_SGI_0 8
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#define IRQ_SEC_SGI_1 9
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