Rework handover interface between BL stages
This patch reworks the handover interface from: BL1 to BL2 and BL2 to BL3-1. It removes the raise_el(), change_el(), drop_el() and run_image() functions as they catered for code paths that were never exercised. BL1 calls bl1_run_bl2() to jump into BL2 instead of doing the same by calling run_image(). Similarly, BL2 issues the SMC to transfer execution to BL3-1 through BL1 directly. Only x0 and x1 are used to pass arguments to BL31. These arguments and parameters for running BL3-1 are passed through a reference to a 'el_change_info_t' structure. They were being passed value in general purpose registers earlier. Change-Id: Id4fd019a19a9595de063766d4a66295a2c9307e1
This commit is contained in:
Vikram Kanigiri
parent
23ff9baa7e
commit
29fb905d5f
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@ -112,13 +112,51 @@ SErrorSPx:
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*/
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.align 7
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SynchronousExceptionA64:
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/* ---------------------------------------------
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/* ------------------------------------------------
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* Only a single SMC exception from BL2 to ask
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* BL1 to pass EL3 control to BL31 is expected
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* here.
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* ---------------------------------------------
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* It expects X0 with RUN_IMAGE SMC function id
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* X1 with address of a el_change_info_t structure
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* describing the BL3-1 entrypoint
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* ------------------------------------------------
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*/
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b process_exception
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mov x19, x0
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mov x20, x1
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mrs x0, esr_el3
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ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x1, #EC_AARCH64_SMC
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b.ne panic
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mov x0, #RUN_IMAGE
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cmp x19, x0
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b.ne panic
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mov x0, x20
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bl display_boot_progress
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ldp x0, x1, [x20, #EL_CHANGE_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ubfx x0, x1, #MODE_EL_SHIFT, #2
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cmp x0, #MODE_EL3
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b.ne panic
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bl disable_mmu_icache_el3
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tlbi alle3
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ldp x6, x7, [x20, #(EL_CHANGE_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(EL_CHANGE_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(EL_CHANGE_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(EL_CHANGE_INFO_ARGS_OFFSET + 0x0)]
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eret
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panic:
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl plat_report_exception
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wfi
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b panic
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check_vector_size SynchronousExceptionA64
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.align 7
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@ -173,56 +211,3 @@ SErrorA32:
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bl plat_report_exception
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b SErrorA32
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check_vector_size SErrorA32
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.align 7
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func process_exception
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sub sp, sp, #0x40
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stp x0, x1, [sp, #0x0]
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stp x2, x3, [sp, #0x10]
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stp x4, x5, [sp, #0x20]
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stp x6, x7, [sp, #0x30]
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mov x19, x0
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mov x20, x1
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mov x21, x2
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl plat_report_exception
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mrs x0, esr_el3
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ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x1, #EC_AARCH64_SMC
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b.ne panic
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mov x1, #RUN_IMAGE
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cmp x19, x1
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b.ne panic
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mov x0, x20
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mov x1, x21
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mov x2, x3
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mov x3, x4
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bl display_boot_progress
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msr elr_el3, x20
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msr spsr_el3, x21
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ubfx x0, x21, #MODE_EL_SHIFT, #2
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cmp x0, #MODE_EL3
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b.ne skip_mmu_teardown
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/* ---------------------------------------------
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* If BL31 is to be executed in EL3 as well
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* then turn off the MMU so that it can perform
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* its own setup.
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* ---------------------------------------------
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*/
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bl disable_mmu_icache_el3
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tlbi alle3
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skip_mmu_teardown:
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ldp x6, x7, [sp, #0x30]
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ldp x4, x5, [sp, #0x20]
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ldp x2, x3, [sp, #0x10]
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ldp x0, x1, [sp, #0x0]
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add sp, sp, #0x40
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eret
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panic:
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wfi
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b panic
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@ -37,6 +37,34 @@
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#include <stdio.h>
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#include "bl1_private.h"
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/*******************************************************************************
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* Runs BL2 from the given entry point. It results in dropping the
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* exception level
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******************************************************************************/
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static void __dead2 bl1_run_bl2(el_change_info_t *bl2_ep)
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{
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bl1_arch_next_el_setup();
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/* Tell next EL what we want done */
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bl2_ep->args.arg0 = RUN_IMAGE;
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if (bl2_ep->security_state == NON_SECURE)
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change_security_state(bl2_ep->security_state);
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write_spsr_el3(bl2_ep->spsr);
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write_elr_el3(bl2_ep->entrypoint);
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eret(bl2_ep->args.arg0,
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bl2_ep->args.arg1,
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bl2_ep->args.arg2,
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bl2_ep->args.arg3,
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bl2_ep->args.arg4,
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bl2_ep->args.arg5,
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bl2_ep->args.arg6,
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bl2_ep->args.arg7);
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}
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/*******************************************************************************
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* Function to perform late architectural and platform specific initialization.
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* It also locates and loads the BL2 raw binary image in the trusted DRAM. Only
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@ -50,9 +78,10 @@ void bl1_main(void)
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unsigned long sctlr_el3 = read_sctlr_el3();
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#endif
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unsigned long bl2_base;
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unsigned int load_type = TOP_LOAD, spsr;
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unsigned int load_type = TOP_LOAD;
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meminfo_t *bl1_tzram_layout;
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meminfo_t *bl2_tzram_layout = 0x0;
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el_change_info_t bl2_ep = {0};
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/*
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* Ensure that MMU/Caches and coherency are turned on
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@ -94,20 +123,19 @@ void bl1_main(void)
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bl2_base);
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if (bl2_base) {
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bl1_arch_next_el_setup();
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spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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bl2_ep.spsr =
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SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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bl2_ep.entrypoint = bl2_base;
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bl2_ep.security_state = SECURE;
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bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout;
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printf("Booting trusted firmware boot loader stage 2\n\r");
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#if DEBUG
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printf("BL2 address = 0x%llx \n\r", (unsigned long long) bl2_base);
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printf("BL2 cpsr = 0x%x \n\r", spsr);
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printf("BL2 cpsr = 0x%x \n\r", bl2_ep.spsr);
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printf("BL2 memory layout address = 0x%llx \n\r",
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(unsigned long long) bl2_tzram_layout);
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#endif
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run_image(bl2_base,
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spsr,
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SECURE,
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(void *) bl2_tzram_layout,
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NULL);
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bl1_run_bl2(&bl2_ep);
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}
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/*
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@ -122,17 +150,16 @@ void bl1_main(void)
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* Temporary function to print the fact that BL2 has done its job and BL31 is
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* about to be loaded. This is needed as long as printfs cannot be used
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******************************************************************************/
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void display_boot_progress(unsigned long entrypoint,
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unsigned long spsr,
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unsigned long mem_layout,
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unsigned long ns_image_info)
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void display_boot_progress(el_change_info_t *bl31_ep_info)
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{
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printf("Booting trusted firmware boot loader stage 3\n\r");
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#if DEBUG
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printf("BL31 address = 0x%llx \n\r", (unsigned long long) entrypoint);
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printf("BL31 cpsr = 0x%llx \n\r", (unsigned long long)spsr);
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printf("BL31 memory layout address = 0x%llx \n\r", (unsigned long long)mem_layout);
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printf("BL31 non-trusted image info address = 0x%llx\n\r", (unsigned long long)ns_image_info);
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printf("BL31 address = 0x%llx\n",
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(unsigned long long)bl31_ep_info->entrypoint);
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printf("BL31 cpsr = 0x%llx\n",
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(unsigned long long)bl31_ep_info->spsr);
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printf("BL31 args address = 0x%llx\n",
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(unsigned long long)bl31_ep_info->args.arg0);
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#endif
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return;
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}
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@ -46,7 +46,6 @@ func bl2_entrypoint
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*/
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mov x20, x0
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mov x21, x1
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mov x22, x2
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/* ---------------------------------------------
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* This is BL2 which is expected to be executed
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@ -110,7 +109,6 @@ func bl2_entrypoint
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* ---------------------------------------------
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*/
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mov x0, x21
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mov x1, x22
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bl bl2_early_platform_setup
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bl bl2_plat_arch_setup
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@ -38,6 +38,27 @@
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#include <stdio.h>
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#include "bl2_private.h"
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/*******************************************************************************
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* Runs BL31 from the given entry point. It jumps to a higher exception level
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* through an SMC.
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******************************************************************************/
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static void __dead2 bl2_run_bl31(bl31_args_t *bl2_to_bl31_args,
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unsigned long arg1,
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unsigned long arg2)
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{
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/* Set the args pointers for X0 and X1 to BL31 */
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bl2_to_bl31_args->bl31_image_info.args.arg0 = arg1;
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bl2_to_bl31_args->bl31_image_info.args.arg1 = arg2;
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/* Flush the entire BL31 args buffer */
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flush_dcache_range((unsigned long) bl2_to_bl31_args,
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sizeof(*bl2_to_bl31_args));
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smc(RUN_IMAGE, (unsigned long)&bl2_to_bl31_args->bl31_image_info,
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0, 0, 0, 0, 0, 0);
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}
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/*******************************************************************************
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* The only thing to do in BL2 is to load further images and pass control to
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* BL31. The memory occupied by BL2 will be reclaimed by BL3_x stages. BL2 runs
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@ -86,19 +107,9 @@ void bl2_main(void)
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*/
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bl2_to_bl31_args = bl2_get_bl31_args_ptr();
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/*
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* Load the BL32 image if there's one. It is upto to platform
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* to specify where BL32 should be loaded if it exists. It
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* could create space in the secure sram or point to a
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* completely different memory. A zero size indicates that the
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* platform does not want to load a BL32 image.
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*/
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if (bl2_to_bl31_args->bl32_meminfo.total_size)
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bl32_base = load_image(&bl2_to_bl31_args->bl32_meminfo,
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BL32_IMAGE_NAME,
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bl2_to_bl31_args->bl32_meminfo.attr &
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LOAD_MASK,
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BL32_BASE);
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bl2_to_bl31_args->bl31_image_info.entrypoint = bl31_base;
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bl2_to_bl31_args->bl31_image_info.spsr =
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SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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/*
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* Create a new layout of memory for BL31 as seen by BL2. This
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@ -143,6 +154,20 @@ void bl2_main(void)
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SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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bl2_to_bl31_args->bl33_image_info.security_state = NON_SECURE;
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/*
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* Load the BL32 image if there's one. It is upto to platform
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* to specify where BL32 should be loaded if it exists. It
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* could create space in the secure sram or point to a
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* completely different memory. A zero size indicates that the
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* platform does not want to load a BL32 image.
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*/
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if (bl2_to_bl31_args->bl32_meminfo.total_size)
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bl32_base = load_image(&bl2_to_bl31_args->bl32_meminfo,
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BL32_IMAGE_NAME,
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bl2_to_bl31_args->bl32_meminfo.attr &
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LOAD_MASK,
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BL32_BASE);
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if (bl32_base) {
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/* Fill BL32 image info */
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bl2_to_bl31_args->bl32_image_info.entrypoint = bl32_base;
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@ -155,18 +180,10 @@ void bl2_main(void)
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bl2_to_bl31_args->bl32_image_info.spsr = 0;
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}
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/* Flush the entire BL31 args buffer */
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flush_dcache_range((unsigned long) bl2_to_bl31_args,
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sizeof(*bl2_to_bl31_args));
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/*
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* Run BL31 via an SMC to BL1. Information on how to pass control to
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* the BL32 (if present) and BL33 software images will be passed to
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* BL31 as an argument.
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*/
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run_image(bl31_base,
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SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
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SECURE,
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(void *) bl2_to_bl31_args,
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NULL);
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bl2_run_bl31(bl2_to_bl31_args, (unsigned long)bl2_to_bl31_args, 0);
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}
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@ -45,12 +45,13 @@
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func bl31_entrypoint
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/* ---------------------------------------------
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* BL2 has populated x0 with the opcode
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* indicating BL31 should be run, x3 with
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* a pointer to a 'bl31_args' structure & x4
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* Preceding bootloader has populated x0 with a
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* pointer to a 'bl31_args' structure & x1
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* with any other optional information
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* ---------------------------------------------
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*/
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mov x20, x0
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mov x21, x1
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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@ -91,16 +92,6 @@ func bl31_entrypoint
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msr sctlr_el3, x1
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isb
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/* ---------------------------------------------
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* Check the opcodes out of paranoia.
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* ---------------------------------------------
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*/
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mov x19, #RUN_IMAGE
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cmp x0, x19
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b.ne _panic
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mov x20, x3
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mov x21, x4
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/* ---------------------------------------------
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* This is BL31 which is expected to be executed
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* only by the primary cpu (at least for now).
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@ -71,57 +71,6 @@ void change_security_state(unsigned int target_security_state)
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write_scr(scr);
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}
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void __dead2 drop_el(aapcs64_params_t *args,
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unsigned long spsr,
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unsigned long entrypoint)
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{
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write_spsr_el3(spsr);
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write_elr_el3(entrypoint);
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eret(args->arg0,
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args->arg1,
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args->arg2,
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args->arg3,
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args->arg4,
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args->arg5,
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args->arg6,
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args->arg7);
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}
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void __dead2 raise_el(aapcs64_params_t *args)
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{
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smc(args->arg0,
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args->arg1,
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args->arg2,
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args->arg3,
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args->arg4,
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args->arg5,
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args->arg6,
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args->arg7);
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}
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/*
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* TODO: If we are not EL3 then currently we only issue an SMC.
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* Add support for dropping into EL0 etc. Consider adding support
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* for switching from S-EL1 to S-EL0/1 etc.
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*/
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void __dead2 change_el(el_change_info_t *info)
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{
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if (IS_IN_EL3()) {
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/*
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* We can go anywhere from EL3. So find where.
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* TODO: Lots to do if we are going non-secure.
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* Flip the NS bit. Restore NS registers etc.
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* Just doing the bare minimal for now.
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*/
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if (info->security_state == NON_SECURE)
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change_security_state(info->security_state);
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drop_el(&info->args, info->spsr, info->entrypoint);
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} else
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raise_el(&info->args);
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}
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/*******************************************************************************
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* The next two functions are the weak definitions. Platform specific
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@ -521,42 +470,3 @@ exit:
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fail: image_base = 0;
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goto exit;
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}
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/*******************************************************************************
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* Run a loaded image from the given entry point. This could result in either
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* dropping into a lower exception level or jumping to a higher exception level.
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* The only way of doing the latter is through an SMC. In either case, setup the
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* parameters for the EL change request correctly.
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******************************************************************************/
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void __dead2 run_image(unsigned long entrypoint,
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unsigned long spsr,
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unsigned long target_security_state,
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void *first_arg,
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void *second_arg)
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{
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el_change_info_t run_image_info;
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/* Tell next EL what we want done */
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run_image_info.args.arg0 = RUN_IMAGE;
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run_image_info.entrypoint = entrypoint;
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run_image_info.spsr = spsr;
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run_image_info.security_state = target_security_state;
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/*
|
||||
* If we are EL3 then only an eret can take us to the desired
|
||||
* exception level. Else for the time being assume that we have
|
||||
* to jump to a higher EL and issue an SMC. Contents of argY
|
||||
* will go into the general purpose register xY e.g. arg0->x0
|
||||
*/
|
||||
if (IS_IN_EL3()) {
|
||||
run_image_info.args.arg1 = (unsigned long) first_arg;
|
||||
run_image_info.args.arg2 = (unsigned long) second_arg;
|
||||
} else {
|
||||
run_image_info.args.arg1 = entrypoint;
|
||||
run_image_info.args.arg2 = spsr;
|
||||
run_image_info.args.arg3 = (unsigned long) first_arg;
|
||||
run_image_info.args.arg4 = (unsigned long) second_arg;
|
||||
}
|
||||
|
||||
change_el(&run_image_info);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -56,10 +56,17 @@
|
|||
*****************************************************************************/
|
||||
#define RUN_IMAGE 0xC0000000
|
||||
|
||||
/*******************************************************************************
|
||||
* Constants that allow assembler code to access members of and the
|
||||
* 'el_change_info' structure at their correct offsets.
|
||||
******************************************************************************/
|
||||
#define EL_CHANGE_INFO_PC_OFFSET 0x0
|
||||
#define EL_CHANGE_INFO_ARGS_OFFSET 0x18
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <cdefs.h> /* For __dead2 */
|
||||
#include <cassert.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Structure used for telling the next BL how much of a particular type of
|
||||
|
|
@ -89,6 +96,8 @@ typedef struct aapcs64_params {
|
|||
* This structure represents the superset of information needed while switching
|
||||
* exception levels. The only two mechanisms to do so are ERET & SMC. In case of
|
||||
* SMC all members apart from 'aapcs64_params' will be ignored.
|
||||
* NOTE: BL1 expects entrypoint followed by spsr while processing SMC to jump
|
||||
* to BL31 from the start of el_change_info
|
||||
******************************************************************************/
|
||||
typedef struct el_change_info {
|
||||
unsigned long entrypoint;
|
||||
|
|
@ -103,6 +112,7 @@ typedef struct el_change_info {
|
|||
* populated only if BL2 detects its presence.
|
||||
******************************************************************************/
|
||||
typedef struct bl31_args {
|
||||
el_change_info_t bl31_image_info;
|
||||
meminfo_t bl31_meminfo;
|
||||
el_change_info_t bl32_image_info;
|
||||
meminfo_t bl32_meminfo;
|
||||
|
|
@ -110,14 +120,29 @@ typedef struct bl31_args {
|
|||
meminfo_t bl33_meminfo;
|
||||
} bl31_args_t;
|
||||
|
||||
|
||||
/*
|
||||
* Compile time assertions related to the 'el_change_info' structure to
|
||||
* ensure that the assembler and the compiler view of the offsets of
|
||||
* the structure members is the same.
|
||||
*/
|
||||
CASSERT(EL_CHANGE_INFO_PC_OFFSET == \
|
||||
__builtin_offsetof(el_change_info_t, entrypoint), \
|
||||
assert_BL31_pc_offset_mismatch);
|
||||
|
||||
CASSERT(EL_CHANGE_INFO_ARGS_OFFSET == \
|
||||
__builtin_offsetof(el_change_info_t, args), \
|
||||
assert_BL31_args_offset_mismatch);
|
||||
|
||||
CASSERT(sizeof(unsigned long) == __builtin_offsetof(el_change_info_t, spsr) - \
|
||||
__builtin_offsetof(el_change_info_t, entrypoint), \
|
||||
assert_entrypoint_and_spsr_should_be_adjacent);
|
||||
|
||||
/*******************************************************************************
|
||||
* Function & variable prototypes
|
||||
******************************************************************************/
|
||||
extern unsigned long page_align(unsigned long, unsigned);
|
||||
extern void change_security_state(unsigned int);
|
||||
extern void __dead2 drop_el(aapcs64_params_t *, unsigned long, unsigned long);
|
||||
extern void __dead2 raise_el(aapcs64_params_t *);
|
||||
extern void __dead2 change_el(el_change_info_t *);
|
||||
extern void init_bl2_mem_layout(meminfo_t *,
|
||||
meminfo_t *,
|
||||
unsigned int,
|
||||
|
|
@ -130,11 +155,6 @@ extern unsigned long load_image(meminfo_t *,
|
|||
const char *,
|
||||
unsigned int,
|
||||
unsigned long);
|
||||
extern void __dead2 run_image(unsigned long entrypoint,
|
||||
unsigned long spsr,
|
||||
unsigned long security_state,
|
||||
void *first_arg,
|
||||
void *second_arg);
|
||||
extern unsigned long *get_el_change_mem_ptr(void);
|
||||
extern const char build_message[];
|
||||
|
||||
|
|
|
|||
|
|
@ -97,8 +97,7 @@ bl31_args_t *bl2_get_bl31_args_ptr(void)
|
|||
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
|
||||
* Copy it to a safe loaction before its reclaimed by later BL2 functionality.
|
||||
******************************************************************************/
|
||||
void bl2_early_platform_setup(meminfo_t *mem_layout,
|
||||
void *data)
|
||||
void bl2_early_platform_setup(meminfo_t *mem_layout)
|
||||
{
|
||||
/* Initialize the console to provide early debug support */
|
||||
console_init(PL011_UART0_BASE);
|
||||
|
|
|
|||
Loading…
Reference in New Issue