intel: agilex: Enable uboot BL31 loading
This patch enables uboot's spl entrypoint to BL31 and also handles secondary cpus state during cold boot. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c
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@ -11,8 +11,10 @@
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#include <common/bl_common.h>
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#include <common/bl_common.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include "socfpga_private.h"
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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@ -44,23 +46,33 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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void *from_bl2 = (void *) arg0;
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void *from_bl2 = (void *) arg0;
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bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
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bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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/*
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/*
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* Copy BL32 (if populated by BL31) and BL33 entry point information.
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* Copy BL32 (if populated by BL31) and BL33 entry point information.
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* They are stored in Secure RAM, in BL31's address space.
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* They are stored in Secure RAM, in BL31's address space.
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*/
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*/
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bl_params_node_t *bl_params = params_from_bl2->head;
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if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
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params_from_bl2->h.version >= VERSION_2) {
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while (bl_params) {
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bl_params_node_t *bl_params = params_from_bl2->head;
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if (bl_params->image_id == BL33_IMAGE_ID)
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bl33_image_ep_info = *bl_params->ep_info;
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bl_params = bl_params->next_params_info;
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while (bl_params) {
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if (bl_params->image_id == BL33_IMAGE_ID)
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bl33_image_ep_info = *bl_params->ep_info;
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bl_params = bl_params->next_params_info;
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}
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} else {
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struct socfpga_bl31_params *arg_from_bl2 =
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(struct socfpga_bl31_params *) from_bl2;
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assert(arg_from_bl2->h.type == PARAM_BL31);
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assert(arg_from_bl2->h.version >= VERSION_1);
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bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
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bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
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}
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}
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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}
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}
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@ -91,6 +103,10 @@ void bl31_platform_setup(void)
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gicv2_distif_init();
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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gicv2_cpuif_enable();
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/* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
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mmio_write_64(PLAT_CPU_RELEASE_ADDR,
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(uint64_t)plat_secondary_cpus_bl31_entry);
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}
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}
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const mmap_region_t plat_agilex_mmap[] = {
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const mmap_region_t plat_agilex_mmap[] = {
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