From 2a246d2e3284d853d1276b9495518aa52d8dba3c Mon Sep 17 00:00:00 2001 From: Dimitris Papastamos Date: Mon, 18 Jun 2018 13:01:06 +0100 Subject: [PATCH] CSS: Use SCMI AP core protocol to set the warm boot entrypoint Change-Id: Iaebbeac1a1d6fbd531e5694b95ed068b7a193e62 Signed-off-by: Dimitris Papastamos --- include/plat/arm/common/plat_arm.h | 2 +- plat/arm/common/arm_bl1_setup.c | 2 +- plat/arm/common/arm_common.mk | 2 +- plat/arm/common/arm_pm.c | 9 +++--- plat/arm/css/drivers/scp/css_pm_scmi.c | 41 ++++++++++++++++++++++++++ 5 files changed, 49 insertions(+), 7 deletions(-) diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 33f2c7dbe..473b758a3 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -171,7 +171,6 @@ int arm_validate_psci_entrypoint(uintptr_t entrypoint); int arm_validate_ns_entrypoint(uintptr_t entrypoint); void arm_system_pwr_domain_save(void); void arm_system_pwr_domain_resume(void); -void arm_program_trusted_mailbox(uintptr_t address); int arm_psci_read_mem_protect(int *enabled); int arm_nor_psci_write_mem_protect(int val); void arm_nor_psci_do_static_mem_protect(void); @@ -250,6 +249,7 @@ void plat_arm_pwrc_setup(void); void plat_arm_interconnect_init(void); void plat_arm_interconnect_enter_coherency(void); void plat_arm_interconnect_exit_coherency(void); +void plat_arm_program_trusted_mailbox(uintptr_t address); #if ARM_PLAT_MT unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index d141f647e..34e0a29e3 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -144,7 +144,7 @@ void bl1_plat_prepare_exit(entry_point_info_t *ep_info) * in order to release secondary CPUs from their holding pen and make * them jump there. */ - arm_program_trusted_mailbox(ep_info->pc); + plat_arm_program_trusted_mailbox(ep_info->pc); dsbsy(); sev(); #endif diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 533084708..67b574de6 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -166,7 +166,7 @@ BL1_SOURCES += drivers/arm/sp805/sp805.c \ plat/arm/common/arm_err.c \ plat/arm/common/arm_io_storage.c ifdef EL3_PAYLOAD_BASE -# Need the arm_program_trusted_mailbox() function to release secondary CPUs from +# Need the plat_arm_program_trusted_mailbox() function to release secondary CPUs from # their holding pen BL1_SOURCES += plat/arm/common/arm_pm.c endif diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index 4632099e7..73d7106bd 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -14,8 +14,9 @@ #include #include -/* Allow ARM Standard platforms to override this function */ +/* Allow ARM Standard platforms to override these functions */ #pragma weak plat_arm_psci_override_pm_ops +#pragma weak plat_arm_program_trusted_mailbox /* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */ extern plat_psci_ops_t plat_arm_psci_pm_ops; @@ -192,11 +193,11 @@ void arm_system_pwr_domain_resume(void) } /******************************************************************************* - * Private function to program the mailbox for a cpu before it is released + * ARM platform function to program the mailbox for a cpu before it is released * from reset. This function assumes that the Trusted mail box base is within * the ARM_SHARED_RAM region ******************************************************************************/ -void arm_program_trusted_mailbox(uintptr_t address) +void plat_arm_program_trusted_mailbox(uintptr_t address) { uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; @@ -221,6 +222,6 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); /* Setup mailbox with entry point. */ - arm_program_trusted_mailbox(sec_entrypoint); + plat_arm_program_trusted_mailbox(sec_entrypoint); return 0; } diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c index 715bf980b..703226771 100644 --- a/plat/arm/css/drivers/scp/css_pm_scmi.c +++ b/plat/arm/css/drivers/scp/css_pm_scmi.c @@ -306,6 +306,28 @@ static scmi_channel_plat_info_t plat_css_scmi_plat_info = { .ring_doorbell = &mhu_ring_doorbell, }; +static int scmi_ap_core_init(scmi_channel_t *ch) +{ +#if PROGRAMMABLE_RESET_ADDRESS + uint32_t version; + int ret; + + ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version); + if (ret != SCMI_E_SUCCESS) { + WARN("SCMI AP core protocol version message failed\n"); + return -1; + } + + if (!is_scmi_version_compatible(SCMI_AP_CORE_PROTO_VER, version)) { + WARN("SCMI AP core protocol version 0x%x incompatible with driver version 0x%x\n", + version, SCMI_AP_CORE_PROTO_VER); + return -1; + } + INFO("SCMI AP core protocol version 0x%x detected\n", version); +#endif + return 0; +} + void plat_arm_pwrc_setup(void) { channel.info = &plat_css_scmi_plat_info; @@ -315,6 +337,10 @@ void plat_arm_pwrc_setup(void) ERROR("SCMI Initialization failed\n"); panic(); } + if (scmi_ap_core_init(&channel) < 0) { + ERROR("SCMI AP core protocol initialization failed\n"); + panic(); + } } /****************************************************************************** @@ -386,3 +412,18 @@ int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie) */ return 0; } + +#if PROGRAMMABLE_RESET_ADDRESS +void plat_arm_program_trusted_mailbox(uintptr_t address) +{ + int ret; + + assert(scmi_handle); + ret = scmi_ap_core_set_reset_addr(scmi_handle, address, + SCMI_AP_CORE_LOCK_ATTR); + if (ret != SCMI_E_SUCCESS) { + ERROR("CSS: Failed to program reset address: %d\n", ret); + panic(); + } +} +#endif