refactor(context mgmt): refactor the cm_setup_context function
This patch splits the function 'cm_setup_context' into four functions to make it more readable and easier to maintain. The function is split into the following functions based on the security state of the context. - setup_context_common - performs common initializations - setup_secure_context - performs Secure state specific initializations - setup_realm_context - performs Realm state specific initializations - setup_ns_context - performs Non-secure state specific initializations Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: Ie14a1c2fc6586087e7aa36537cf9064c80802f8f
This commit is contained in:
Zelalem Aweke
Joanna Farley
parent
7f41bcc76d
commit
2bbad1d126
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -31,54 +31,133 @@
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static void manage_extensions_secure(cpu_context_t *ctx);
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/*******************************************************************************
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* Context management library initialisation routine. This library is used by
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* runtime services to share pointers to 'cpu_context' structures for the secure
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* and non-secure states. Management of the structures and their associated
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* memory is not done by the context management library e.g. the PSCI service
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* manages the cpu context used for entry from and exit to the non-secure state.
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* The Secure payload dispatcher service manages the context(s) corresponding to
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* the secure state. It also uses this library to get access to the non-secure
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* state cpu context pointers.
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* Lastly, this library provides the api to make SP_EL3 point to the cpu context
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* which will used for programming an entry into a lower EL. The same context
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* will used to save state upon exception entry from that EL.
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******************************************************************************/
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void __init cm_init(void)
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/******************************************************************************
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* This function performs initializations that are specific to SECURE state
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* and updates the cpu context specified by 'ctx'.
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*****************************************************************************/
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static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
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{
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u_register_t scr_el3;
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el3_state_t *state;
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state = get_el3state_ctx(ctx);
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scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
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#if defined(IMAGE_BL31) && !defined(SPD_spmd)
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/*
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* The context management library has only global data to intialize, but
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* that will be done when the BSS is zeroed out
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* SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
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* indicated by the interrupt routing model for BL31.
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*/
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scr_el3 |= get_scr_el3_from_routing_model(SECURE);
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#endif
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#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
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/* Get Memory Tagging Extension support level */
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unsigned int mte = get_armv8_5_mte_support();
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#endif
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/*
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* Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS
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* is set, or when MTE is only implemented at EL0.
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*/
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#if CTX_INCLUDE_MTE_REGS
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assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
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scr_el3 |= SCR_ATA_BIT;
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#else
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if (mte == MTE_IMPLEMENTED_EL0) {
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scr_el3 |= SCR_ATA_BIT;
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}
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#endif /* CTX_INCLUDE_MTE_REGS */
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/* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */
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if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) {
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if (GET_RW(ep->spsr) != MODE_RW_64) {
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ERROR("S-EL2 can not be used in AArch32\n.");
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panic();
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}
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scr_el3 |= SCR_EEL2_BIT;
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}
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write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
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manage_extensions_secure(ctx);
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}
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#if ENABLE_RME
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/******************************************************************************
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* This function performs initializations that are specific to REALM state
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* and updates the cpu context specified by 'ctx'.
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*****************************************************************************/
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static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
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{
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u_register_t scr_el3;
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el3_state_t *state;
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state = get_el3state_ctx(ctx);
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scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
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scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT;
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write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
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}
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#endif /* ENABLE_RME */
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/******************************************************************************
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* This function performs initializations that are specific to NON-SECURE state
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* and updates the cpu context specified by 'ctx'.
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*****************************************************************************/
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static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
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{
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u_register_t scr_el3;
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el3_state_t *state;
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state = get_el3state_ctx(ctx);
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scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
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/* SCR_NS: Set the NS bit */
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scr_el3 |= SCR_NS_BIT;
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#if !CTX_INCLUDE_PAUTH_REGS
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/*
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* If the pointer authentication registers aren't saved during world
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* switches the value of the registers can be leaked from the Secure to
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* the Non-secure world. To prevent this, rather than enabling pointer
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* authentication everywhere, we only enable it in the Non-secure world.
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*
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* If the Secure world wants to use pointer authentication,
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* CTX_INCLUDE_PAUTH_REGS must be set to 1.
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*/
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scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
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#endif /* !CTX_INCLUDE_PAUTH_REGS */
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/* Allow access to Allocation Tags when MTE is implemented. */
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scr_el3 |= SCR_ATA_BIT;
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#ifdef IMAGE_BL31
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/*
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* SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
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* indicated by the interrupt routing model for BL31.
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*/
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scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
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#endif
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write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
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}
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/*******************************************************************************
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* The following function initializes the cpu_context 'ctx' for
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* first use, and sets the initial entrypoint state as specified by the
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* entry_point_info structure.
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*
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* The security state to initialize is determined by the SECURE attribute
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* of the entry_point_info.
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* The following function performs initialization of the cpu_context 'ctx'
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* for first use that is common to all security states, and sets the
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* initial entrypoint state as specified by the entry_point_info structure.
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*
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* The EE and ST attributes are used to configure the endianness and secure
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* timer availability for the new execution context.
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*
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* To prepare the register state for entry call cm_prepare_el3_exit() and
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* el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
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* cm_el1_sysregs_context_restore().
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******************************************************************************/
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void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
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{
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unsigned int security_state;
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u_register_t scr_el3;
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el3_state_t *state;
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gp_regs_t *gp_regs;
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u_register_t sctlr_elx, actlr_elx;
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assert(ctx != NULL);
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security_state = GET_SECURITY_STATE(ep->h.attr);
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/* Clear any residual register values from the context */
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zeromem(ctx, sizeof(*ctx));
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@ -93,26 +172,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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*/
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scr_el3 = read_scr();
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scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
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SCR_ST_BIT | SCR_HCE_BIT);
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#if ENABLE_RME
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/* When RME support is enabled, clear the NSE bit as well. */
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scr_el3 &= ~SCR_NSE_BIT;
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#endif /* ENABLE_RME */
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/*
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* SCR_NS: Set the security state of the next EL.
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*/
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if (security_state == NON_SECURE) {
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scr_el3 |= SCR_NS_BIT;
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}
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#if ENABLE_RME
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/* Check for realm state if RME support enabled. */
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if (security_state == REALM) {
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scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT;
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}
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#endif /* ENABLE_RME */
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SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT);
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/*
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* SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
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@ -121,6 +181,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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if (GET_RW(ep->spsr) == MODE_RW_64) {
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scr_el3 |= SCR_RW_BIT;
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}
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/*
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* SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
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* Secure timer registers to EL3, from AArch64 state only, if specified
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@ -149,8 +210,8 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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#if !HANDLE_EA_EL3_FIRST
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/*
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* SCR_EL3.EA: Do not route External Abort and SError Interrupt External
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* to EL3 when executing at a lower EL. When executing at EL3, External
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* Aborts are taken to EL3.
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* to EL3 when executing at a lower EL. When executing at EL3, External
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* Aborts are taken to EL3.
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*/
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scr_el3 &= ~SCR_EA_BIT;
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#endif
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@ -160,68 +221,11 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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scr_el3 |= SCR_FIEN_BIT;
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#endif
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#if !CTX_INCLUDE_PAUTH_REGS
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/*
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* If the pointer authentication registers aren't saved during world
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* switches the value of the registers can be leaked from the Secure to
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* the Non-secure world. To prevent this, rather than enabling pointer
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* authentication everywhere, we only enable it in the Non-secure world.
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*
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* If the Secure world wants to use pointer authentication,
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* CTX_INCLUDE_PAUTH_REGS must be set to 1.
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* CPTR_EL3 was initialized out of reset, copy that value to the
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* context register.
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*/
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if (security_state == NON_SECURE) {
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scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
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}
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#endif /* !CTX_INCLUDE_PAUTH_REGS */
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#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
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/* Get Memory Tagging Extension support level */
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unsigned int mte = get_armv8_5_mte_support();
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#endif
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/*
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* Enable MTE support. Support is enabled unilaterally for the normal
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* world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
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* set.
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*/
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#if CTX_INCLUDE_MTE_REGS
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assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
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scr_el3 |= SCR_ATA_BIT;
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#else
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/*
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* When MTE is only implemented at EL0, it can be enabled
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* across both worlds as no MTE registers are used.
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*/
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if ((mte == MTE_IMPLEMENTED_EL0) ||
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/*
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* When MTE is implemented at all ELs, it can be only enabled
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* in Non-Secure world without register saving.
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*/
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(((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) &&
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(security_state == NON_SECURE))) {
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scr_el3 |= SCR_ATA_BIT;
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}
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#endif /* CTX_INCLUDE_MTE_REGS */
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#ifdef IMAGE_BL31
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/*
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* SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
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* indicated by the interrupt routing model for BL31.
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*
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* TODO: The interrupt routing model code is not updated for REALM
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* state. Use the default values of IRQ = FIQ = 0 for REALM security
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* state for now.
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*/
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if (security_state != REALM) {
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scr_el3 |= get_scr_el3_from_routing_model(security_state);
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}
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#endif
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/* Save the initialized value of CPTR_EL3 register */
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write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3());
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if (security_state == SECURE) {
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manage_extensions_secure(ctx);
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}
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/*
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* SCR_EL3.HCE: Enable HVC instructions if next execution state is
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@ -249,16 +253,6 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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}
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}
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/* Enable S-EL2 if the next EL is EL2 and security state is secure */
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if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) {
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if (GET_RW(ep->spsr) != MODE_RW_64) {
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ERROR("S-EL2 can not be used in AArch32.");
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panic();
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}
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scr_el3 |= SCR_EEL2_BIT;
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}
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/*
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* FEAT_AMUv1p1 virtual offset registers are only accessible from EL3
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* and EL2, when clear, this bit traps accesses from EL2 so we set it
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@ -361,6 +355,66 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
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}
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/*******************************************************************************
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* Context management library initialization routine. This library is used by
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* runtime services to share pointers to 'cpu_context' structures for secure
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* non-secure and realm states. Management of the structures and their associated
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* memory is not done by the context management library e.g. the PSCI service
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* manages the cpu context used for entry from and exit to the non-secure state.
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* The Secure payload dispatcher service manages the context(s) corresponding to
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* the secure state. It also uses this library to get access to the non-secure
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* state cpu context pointers.
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* Lastly, this library provides the API to make SP_EL3 point to the cpu context
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* which will be used for programming an entry into a lower EL. The same context
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* will be used to save state upon exception entry from that EL.
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******************************************************************************/
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void __init cm_init(void)
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{
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/*
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* The context management library has only global data to intialize, but
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* that will be done when the BSS is zeroed out.
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*/
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}
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/*******************************************************************************
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* This is the high-level function used to initialize the cpu_context 'ctx' for
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* first use. It performs initializations that are common to all security states
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* and initializations specific to the security state specified in 'ep'
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******************************************************************************/
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void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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{
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unsigned int security_state;
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assert(ctx != NULL);
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/*
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* Perform initializations that are common
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* to all security states
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*/
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setup_context_common(ctx, ep);
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security_state = GET_SECURITY_STATE(ep->h.attr);
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/* Perform security state specific initializations */
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switch (security_state) {
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case SECURE:
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setup_secure_context(ctx, ep);
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break;
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#if ENABLE_RME
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case REALM:
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setup_realm_context(ctx, ep);
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break;
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#endif
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case NON_SECURE:
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setup_ns_context(ctx, ep);
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break;
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default:
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ERROR("Invalid security state\n");
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panic();
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break;
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}
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}
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/*******************************************************************************
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* Enable architecture extensions on first entry to Non-secure world.
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* When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
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