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Merge "adding support to enable different personality of the same soc." into integration

This commit is contained in:
Manish Pandey 2019-12-10 17:01:48 +00:00 committed by TrustedFirmware Code Review
parent 953dc5410b ab4df50c23
commit 2bcaeab663
3 changed files with 18 additions and 13 deletions
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17
lib/psci/psci_common.c
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@ -43,6 +43,7 @@ const spd_pm_ops_t *psci_spd_pm;
static plat_local_state_t static plat_local_state_t
psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT]; psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
unsigned int psci_plat_core_count;
/******************************************************************************* /*******************************************************************************
* Arrays that hold the platform's power domain tree information for state * Arrays that hold the platform's power domain tree information for state
@ -161,7 +162,7 @@ unsigned int psci_is_last_on_cpu(void)
{ {
unsigned int cpu_idx, my_idx = plat_my_core_pos(); unsigned int cpu_idx, my_idx = plat_my_core_pos();
for (cpu_idx = 0; cpu_idx < (unsigned int)PLATFORM_CORE_COUNT; for (cpu_idx = 0; cpu_idx < psci_plat_core_count;
cpu_idx++) { cpu_idx++) {
if (cpu_idx == my_idx) { if (cpu_idx == my_idx) {
assert(psci_get_aff_info_state() == AFF_STATE_ON); assert(psci_get_aff_info_state() == AFF_STATE_ON);
@ -208,7 +209,7 @@ static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
{ {
assert(pwrlvl > PSCI_CPU_PWR_LVL); assert(pwrlvl > PSCI_CPU_PWR_LVL);
if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
(cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) { (cpu_idx < psci_plat_core_count)) {
psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state; psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
} }
} }
@ -220,10 +221,10 @@ void __init psci_init_req_local_pwr_states(void)
{ {
/* Initialize the requested state of all non CPU power domains as OFF */ /* Initialize the requested state of all non CPU power domains as OFF */
unsigned int pwrlvl; unsigned int pwrlvl;
int core; unsigned int core;
for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) { for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) {
for (core = 0; core < PLATFORM_CORE_COUNT; core++) { for (core = 0; core < psci_plat_core_count; core++) {
psci_req_local_pwr_states[pwrlvl][core] = psci_req_local_pwr_states[pwrlvl][core] =
PLAT_MAX_OFF_STATE; PLAT_MAX_OFF_STATE;
} }
@ -244,7 +245,7 @@ static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl,
assert(pwrlvl > PSCI_CPU_PWR_LVL); assert(pwrlvl > PSCI_CPU_PWR_LVL);
if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
(cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) { (cpu_idx < psci_plat_core_count)) {
return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx]; return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
} else } else
return NULL; return NULL;
@ -888,7 +889,7 @@ int psci_spd_migrate_info(u_register_t *mpidr)
void psci_print_power_domain_map(void) void psci_print_power_domain_map(void)
{ {
#if LOG_LEVEL >= LOG_LEVEL_INFO #if LOG_LEVEL >= LOG_LEVEL_INFO
int idx; unsigned int idx;
plat_local_state_t state; plat_local_state_t state;
plat_local_state_type_t state_type; plat_local_state_type_t state_type;
@ -900,7 +901,7 @@ void psci_print_power_domain_map(void)
}; };
INFO("PSCI Power Domain Map:\n"); INFO("PSCI Power Domain Map:\n");
for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT); for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - psci_plat_core_count);
idx++) { idx++) {
state_type = find_local_state_type( state_type = find_local_state_type(
psci_non_cpu_pd_nodes[idx].local_state); psci_non_cpu_pd_nodes[idx].local_state);
@ -912,7 +913,7 @@ void psci_print_power_domain_map(void)
psci_non_cpu_pd_nodes[idx].local_state); psci_non_cpu_pd_nodes[idx].local_state);
} }
for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) { for (idx = 0; idx < psci_plat_core_count; idx++) {
state = psci_get_cpu_local_state_by_idx(idx); state = psci_get_cpu_local_state_by_idx(idx);
state_type = find_local_state_type(state); state_type = find_local_state_type(state);
INFO(" CPU Node : MPID 0x%llx, parent_node %d," INFO(" CPU Node : MPID 0x%llx, parent_node %d,"

1
lib/psci/psci_private.h
View File

@ -251,6 +251,7 @@ extern const plat_psci_ops_t *psci_plat_pm_ops;
extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
extern unsigned int psci_caps; extern unsigned int psci_caps;
extern unsigned int psci_plat_core_count;
/******************************************************************************* /*******************************************************************************
* SPD's power management hooks registered with PSCI * SPD's power management hooks registered with PSCI

13
lib/psci/psci_setup.c
View File

@ -84,11 +84,12 @@ static void __init psci_init_pwr_domain_node(unsigned char node_idx,
*******************************************************************************/ *******************************************************************************/
static void __init psci_update_pwrlvl_limits(void) static void __init psci_update_pwrlvl_limits(void)
{ {
int j, cpu_idx; unsigned int cpu_idx;
int j;
unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0};
unsigned int temp_index[PLAT_MAX_PWR_LVL]; unsigned int temp_index[PLAT_MAX_PWR_LVL];
for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
psci_get_parent_pwr_domain_nodes(cpu_idx, psci_get_parent_pwr_domain_nodes(cpu_idx,
(unsigned int)PLAT_MAX_PWR_LVL, (unsigned int)PLAT_MAX_PWR_LVL,
temp_index); temp_index);
@ -109,7 +110,8 @@ static void __init psci_update_pwrlvl_limits(void)
* informs the number of root power domains. The parent nodes of the root nodes * informs the number of root power domains. The parent nodes of the root nodes
* will point to an invalid entry(-1). * will point to an invalid entry(-1).
******************************************************************************/ ******************************************************************************/
static void __init populate_power_domain_tree(const unsigned char *topology) static unsigned int __init populate_power_domain_tree(const unsigned char
*topology)
{ {
unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl; unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl;
unsigned int node_index = 0U, num_children; unsigned int node_index = 0U, num_children;
@ -160,7 +162,8 @@ static void __init populate_power_domain_tree(const unsigned char *topology)
} }
/* Validate the sanity of array exported by the platform */ /* Validate the sanity of array exported by the platform */
assert((int) j == PLATFORM_CORE_COUNT); assert(j <= (unsigned int)PLATFORM_CORE_COUNT);
return j;
} }
/******************************************************************************* /*******************************************************************************
@ -199,7 +202,7 @@ int __init psci_setup(const psci_lib_args_t *lib_args)
topology_tree = plat_get_power_domain_tree_desc(); topology_tree = plat_get_power_domain_tree_desc();
/* Populate the power domain arrays using the platform topology map */ /* Populate the power domain arrays using the platform topology map */
populate_power_domain_tree(topology_tree); psci_plat_core_count = populate_power_domain_tree(topology_tree);
/* Update the CPU limits for each node in psci_non_cpu_pd_nodes */ /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */
psci_update_pwrlvl_limits(); psci_update_pwrlvl_limits();