Tegra194: read-modify-write ACTLR_ELx registers
This patch changes direct writes to ACTLR_ELx registers to use read-modify-write instead. Change-Id: I536dce75c01356ce054dd2edee80875e56164439 Signed-off-by: Steven Kao <skao@nvidia.com>
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@ -27,20 +27,6 @@
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 8
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
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#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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/*******************************************************************************
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* Secure IRQ definitions
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******************************************************************************/
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@ -13,6 +13,7 @@
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#include <mce_private.h>
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#include <platform_def.h>
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#include <t194_nvg.h>
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#include <tegra_private.h>
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extern void nvg_set_request_data(uint64_t req, uint64_t data);
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extern void nvg_set_request(uint64_t req);
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@ -342,6 +343,7 @@ int32_t nvg_roc_clean_cache_trbits(void)
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int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
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{
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int32_t ret = 0;
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uint64_t val = 0ULL;
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/* check for allowed power state */
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if ((state != (uint32_t)TEGRA_NVG_CORE_C0) &&
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@ -356,7 +358,8 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
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nvg_set_wake_time(wake_time);
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/* set the core cstate */
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write_actlr_el1(state);
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val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
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write_actlr_el1(val | (uint64_t)state);
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}
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return ret;
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