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plat/arm/board/arm_fpga: Initialize the System Counter 

This sets the frequency of the system counter so that the Delay Timer
driver programs the correct value to CNTCRL. This value depends on
the FPGA image being used, and is 10MHz for the initial test image.
Once configured, the BL31 platform setup sequence then enables the
system counter.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
This commit is contained in:
Oliver Swede 2019-12-02 13:33:40 +00:00
parent 7ee4db6e47
commit 2d696d1811
2 changed files with 11 additions and 6 deletions
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14
plat/arm/board/arm_fpga/fpga_bl31_setup.c
View File

@ -5,6 +5,8 @@
*/
#include <assert.h>
#include <lib/mmio.h>
#include <drivers/generic_delay_timer.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@ -49,7 +51,11 @@ void bl31_plat_arch_setup(void)
void bl31_platform_setup(void)
{
/* TODO: initialize GIC and timer using the specifications of the FPGA image */
/* Write frequency to CNTCRL and initialize timer */
generic_delay_timer_init();
mmio_write_32(FPGA_TIMER_BASE, ((1 << 8) | 1UL));
/* TODO: initialize GIC using the specifications of the FPGA image */
}
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
@ -70,11 +76,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
unsigned int plat_get_syscnt_freq2(void)
{
/*
* TODO: return the frequency of the System Counter as configured by the
* FPGA image
*/
return 0;
return FPGA_TIMER_FREQUENCY;
}
void bl31_plat_enable_mmu(uint32_t flags)

3
plat/arm/board/arm_fpga/fpga_def.h
View File

@ -30,4 +30,7 @@
#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ
#define FPGA_TIMER_FREQUENCY 10000000
#define FPGA_TIMER_BASE 0x2a830000
#endif