fdts: stm32mp1: move FDCAN to PLL4_R
LTDC modifies the clock frequency to adapt it to the display. Such frequency change is not detected by the FDCAN driver that instead caches the value at probe and pretends to use it later. This change fixes the issue by moving the FDCAN to PLL4_R, leaving the LTDC alone on PLL4_Q. Signed-off-by: Antonio Borneo <antonio.borneo@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58
这个提交包含在:
父节点
57f4b6f839
当前提交
2dc9fe70da
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@ -246,7 +246,7 @@
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4Q
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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@ -266,7 +266,7 @@
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4Q
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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@ -272,7 +272,7 @@
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4Q
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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