hikey*: Add LOAD_IMAGE_V2 support
Signed-off-by: Victor Chong <victor.chong@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org>
This commit is contained in:
parent
a87a1fb3ed
commit
2de0c5cc4f
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@ -58,13 +58,35 @@ meminfo_t *bl1_plat_sec_mem_layout(void)
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return &bl1_tzram_layout;
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return &bl1_tzram_layout;
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}
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}
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#if LOAD_IMAGE_V2
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/*******************************************************************************
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* Function that takes a memory layout into which BL2 has been loaded and
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* populates a new memory layout for BL2 that ensures that BL1's data sections
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* resident in secure RAM are not visible to BL2.
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******************************************************************************/
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void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
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meminfo_t *bl2_mem_layout)
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{
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assert(bl1_mem_layout != NULL);
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assert(bl2_mem_layout != NULL);
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/*
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* Cannot remove BL1 RW data from the scope of memory visible to BL2
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* like arm platforms because they overlap in hikey
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*/
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bl2_mem_layout->total_base = BL2_BASE;
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bl2_mem_layout->total_size = BL32_SRAM_LIMIT - BL2_BASE;
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flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
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}
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#endif /* LOAD_IMAGE_V2 */
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/*
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/*
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* Perform any BL1 specific platform actions.
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* Perform any BL1 specific platform actions.
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*/
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*/
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void bl1_early_platform_setup(void)
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void bl1_early_platform_setup(void)
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{
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{
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const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
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/* Initialize the console to provide early debug support */
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/* Initialize the console to provide early debug support */
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console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
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console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
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@ -72,16 +94,18 @@ void bl1_early_platform_setup(void)
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bl1_tzram_layout.total_base = BL1_RW_BASE;
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bl1_tzram_layout.total_base = BL1_RW_BASE;
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bl1_tzram_layout.total_size = BL1_RW_SIZE;
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bl1_tzram_layout.total_size = BL1_RW_SIZE;
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#if !LOAD_IMAGE_V2
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/* Calculate how much RAM BL1 is using and how much remains free */
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/* Calculate how much RAM BL1 is using and how much remains free */
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bl1_tzram_layout.free_base = BL1_RW_BASE;
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bl1_tzram_layout.free_base = BL1_RW_BASE;
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bl1_tzram_layout.free_size = BL1_RW_SIZE;
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bl1_tzram_layout.free_size = BL1_RW_SIZE;
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reserve_mem(&bl1_tzram_layout.free_base,
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reserve_mem(&bl1_tzram_layout.free_base,
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&bl1_tzram_layout.free_size,
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&bl1_tzram_layout.free_size,
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BL1_RAM_BASE,
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BL1_RAM_BASE,
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bl1_size);
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BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
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#endif
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INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
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INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
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bl1_size);
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BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
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}
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}
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/*
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/*
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@ -0,0 +1,128 @@
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/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <bl_common.h>
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#include <desc_image_load.h>
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#include <platform.h>
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#include <platform_def.h>
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/*******************************************************************************
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* Following descriptor provides BL image/ep information that gets used
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* by BL2 to load the images and also subset of this information is
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* passed to next BL image. The image loading sequence is managed by
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* populating the images in required loading order. The image execution
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* sequence is managed by populating the `next_handoff_image_id` with
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* the next executable image id.
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******************************************************************************/
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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#ifdef SCP_BL2_BASE
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/* Fill SCP_BL2 related information if it exists */
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{
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.image_id = SCP_BL2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = SCP_BL2_BASE,
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.image_info.image_max_size = SCP_BL2_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#endif /* SCP_BL2_BASE */
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#ifdef EL3_PAYLOAD_BASE
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/* Fill EL3 payload related information (BL31 is EL3 payload)*/
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = EL3_PAYLOAD_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#else /* EL3_PAYLOAD_BASE */
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/* Fill BL31 related information */
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL31_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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#if DEBUG
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.ep_info.args.arg1 = HIKEY_BL31_PLAT_PARAM_VAL,
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#endif
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = BL31_BASE,
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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# ifdef BL32_BASE
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.next_handoff_image_id = BL32_IMAGE_ID,
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# else
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.next_handoff_image_id = BL33_IMAGE_ID,
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# endif
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},
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# ifdef BL32_BASE
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/* Fill BL32 related information */
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{
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.image_id = BL32_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
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.ep_info.pc = BL32_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = BL32_BASE,
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.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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# endif /* BL32_BASE */
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/* Fill BL33 related information */
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{
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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# ifdef PRELOADED_BL33_BASE
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.ep_info.pc = PRELOADED_BL33_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
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# else
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.ep_info.pc = HIKEY_NS_IMAGE_OFFSET,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = HIKEY_NS_IMAGE_OFFSET,
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.image_info.image_max_size = 0x200000 /* 2MB */,
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# endif /* PRELOADED_BL33_BASE */
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.next_handoff_image_id = INVALID_IMAGE_ID,
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}
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#endif /* EL3_PAYLOAD_BASE */
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
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@ -9,6 +9,7 @@
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#include <bl_common.h>
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#include <bl_common.h>
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#include <console.h>
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#include <console.h>
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#include <debug.h>
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#include <debug.h>
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#include <desc_image_load.h>
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#include <dw_mmc.h>
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#include <dw_mmc.h>
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#include <emmc.h>
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#include <emmc.h>
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#include <errno.h>
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#include <errno.h>
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@ -44,6 +45,13 @@
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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#if !LOAD_IMAGE_V2
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/*******************************************************************************
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* This structure represents the superset of information that is passed to
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* BL31, e.g. while passing control to it from BL2, bl31_params
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* and other platform specific params
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******************************************************************************/
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typedef struct bl2_to_bl31_params_mem {
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typedef struct bl2_to_bl31_params_mem {
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bl31_params_t bl31_params;
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bl31_params_t bl31_params;
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image_info_t bl31_image_info;
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image_info_t bl31_image_info;
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@ -68,8 +76,17 @@ void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
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scp_bl2_meminfo->free_base = SCP_BL2_BASE;
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scp_bl2_meminfo->free_base = SCP_BL2_BASE;
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scp_bl2_meminfo->free_size = SCP_BL2_SIZE;
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scp_bl2_meminfo->free_size = SCP_BL2_SIZE;
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}
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}
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#endif /* LOAD_IMAGE_V2 */
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/*******************************************************************************
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* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
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* Return 0 on success, -1 otherwise.
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******************************************************************************/
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#if LOAD_IMAGE_V2
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int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
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#else
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int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info)
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int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info)
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#endif
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{
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{
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/* Enable MCU SRAM */
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/* Enable MCU SRAM */
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hisi_mcu_enable_sram();
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hisi_mcu_enable_sram();
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@ -87,6 +104,103 @@ int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info)
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return 0;
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return 0;
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}
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}
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/*******************************************************************************
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* Gets SPSR for BL32 entry
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******************************************************************************/
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uint32_t hikey_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL3-2 image.
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*/
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return 0;
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}
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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#ifndef AARCH32
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uint32_t hikey_get_spsr_for_bl33_entry(void)
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{
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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#else
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uint32_t hikey_get_spsr_for_bl33_entry(void)
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{
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unsigned int hyp_status, mode, spsr;
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hyp_status = GET_VIRT_EXT(read_id_pfr1());
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mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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#endif /* AARCH32 */
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#if LOAD_IMAGE_V2
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int hikey_bl2_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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assert(bl_mem_params);
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switch (image_id) {
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#ifdef AARCH64
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case BL32_IMAGE_ID:
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bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry();
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break;
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#endif
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case BL33_IMAGE_ID:
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry();
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break;
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#ifdef SCP_BL2_BASE
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case SCP_BL2_IMAGE_ID:
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/* The subsequent handling of SCP_BL2 is platform specific */
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err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info);
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if (err) {
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WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
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}
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break;
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#endif
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}
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return err;
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}
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/*******************************************************************************
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* This function can be used by the platforms to update/use image
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* information for given `image_id`.
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******************************************************************************/
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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return hikey_bl2_handle_post_image_load(image_id);
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}
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#else /* LOAD_IMAGE_V2 */
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bl31_params_t *bl2_plat_get_bl31_params(void)
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bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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{
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bl31_params_t *bl2_to_bl31_params = NULL;
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bl31_params_t *bl2_to_bl31_params = NULL;
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@ -133,6 +247,10 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
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struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
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struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
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{
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{
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#if DEBUG
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||||||
|
bl31_params_mem.bl31_ep_info.args.arg1 = HIKEY_BL31_PLAT_PARAM_VAL;
|
||||||
|
#endif
|
||||||
|
|
||||||
return &bl31_params_mem.bl31_ep_info;
|
return &bl31_params_mem.bl31_ep_info;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -217,6 +335,7 @@ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
|
||||||
bl33_meminfo->free_base = DDR_BASE;
|
bl33_meminfo->free_base = DDR_BASE;
|
||||||
bl33_meminfo->free_size = DDR_SIZE;
|
bl33_meminfo->free_size = DDR_SIZE;
|
||||||
}
|
}
|
||||||
|
#endif /* LOAD_IMAGE_V2 */
|
||||||
|
|
||||||
static void reset_dwmmc_clk(void)
|
static void reset_dwmmc_clk(void)
|
||||||
{
|
{
|
||||||
|
|
|
@ -81,8 +81,13 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if LOAD_IMAGE_V2
|
||||||
|
void bl31_early_platform_setup(void *from_bl2,
|
||||||
|
void *plat_params_from_bl2)
|
||||||
|
#else
|
||||||
void bl31_early_platform_setup(bl31_params_t *from_bl2,
|
void bl31_early_platform_setup(bl31_params_t *from_bl2,
|
||||||
void *plat_params_from_bl2)
|
void *plat_params_from_bl2)
|
||||||
|
#endif
|
||||||
{
|
{
|
||||||
/* Initialize the console to provide early debug support */
|
/* Initialize the console to provide early debug support */
|
||||||
console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
|
console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
|
||||||
|
@ -91,12 +96,50 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
|
||||||
cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map));
|
cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map));
|
||||||
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
|
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
|
||||||
|
|
||||||
|
#if LOAD_IMAGE_V2
|
||||||
|
/*
|
||||||
|
* Check params passed from BL2 should not be NULL,
|
||||||
|
*/
|
||||||
|
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
|
||||||
|
assert(params_from_bl2 != NULL);
|
||||||
|
assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
|
||||||
|
assert(params_from_bl2->h.version >= VERSION_2);
|
||||||
|
|
||||||
|
bl_params_node_t *bl_params = params_from_bl2->head;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copy BL33 and BL32 (if present), entry point information.
|
||||||
|
* They are stored in Secure RAM, in BL2's address space.
|
||||||
|
*/
|
||||||
|
while (bl_params) {
|
||||||
|
if (bl_params->image_id == BL32_IMAGE_ID)
|
||||||
|
bl32_ep_info = *bl_params->ep_info;
|
||||||
|
|
||||||
|
if (bl_params->image_id == BL33_IMAGE_ID)
|
||||||
|
bl33_ep_info = *bl_params->ep_info;
|
||||||
|
|
||||||
|
bl_params = bl_params->next_params_info;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (bl33_ep_info.pc == 0)
|
||||||
|
panic();
|
||||||
|
|
||||||
|
#else /* LOAD_IMAGE_V2 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check params passed from BL2 should not be NULL,
|
||||||
|
*/
|
||||||
|
assert(from_bl2 != NULL);
|
||||||
|
assert(from_bl2->h.type == PARAM_BL31);
|
||||||
|
assert(from_bl2->h.version >= VERSION_1);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Copy BL3-2 and BL3-3 entry point information.
|
* Copy BL3-2 and BL3-3 entry point information.
|
||||||
* They are stored in Secure RAM, in BL2's address space.
|
* They are stored in Secure RAM, in BL2's address space.
|
||||||
*/
|
*/
|
||||||
bl32_ep_info = *from_bl2->bl32_ep_info;
|
bl32_ep_info = *from_bl2->bl32_ep_info;
|
||||||
bl33_ep_info = *from_bl2->bl33_ep_info;
|
bl33_ep_info = *from_bl2->bl33_ep_info;
|
||||||
|
#endif /* LOAD_IMAGE_V2 */
|
||||||
}
|
}
|
||||||
|
|
||||||
void bl31_plat_arch_setup(void)
|
void bl31_plat_arch_setup(void)
|
||||||
|
|
|
@ -0,0 +1,34 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <bl_common.h>
|
||||||
|
#include <desc_image_load.h>
|
||||||
|
#include <platform.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function flushes the data structures so that they are visible
|
||||||
|
* in memory for the next BL image.
|
||||||
|
******************************************************************************/
|
||||||
|
void plat_flush_next_bl_params(void)
|
||||||
|
{
|
||||||
|
flush_bl_params_desc();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns the list of loadable images.
|
||||||
|
******************************************************************************/
|
||||||
|
bl_load_info_t *plat_get_bl_image_load_info(void)
|
||||||
|
{
|
||||||
|
return get_bl_load_info_from_mem_params_desc();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns the list of executable images.
|
||||||
|
******************************************************************************/
|
||||||
|
bl_params_t *plat_get_next_bl_params(void)
|
||||||
|
{
|
||||||
|
return get_next_bl_params_from_mem_params_desc();
|
||||||
|
}
|
|
@ -10,6 +10,9 @@
|
||||||
#include <arch.h>
|
#include <arch.h>
|
||||||
#include "../hikey_def.h"
|
#include "../hikey_def.h"
|
||||||
|
|
||||||
|
/* Special value used to verify platform parameters from BL2 to BL3-1 */
|
||||||
|
#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Generic platform constants
|
* Generic platform constants
|
||||||
*/
|
*/
|
||||||
|
@ -94,7 +97,7 @@
|
||||||
/*
|
/*
|
||||||
* BL31 specific defines.
|
* BL31 specific defines.
|
||||||
*/
|
*/
|
||||||
#define BL31_BASE BL2_LIMIT
|
#define BL31_BASE BL2_LIMIT /* 0xf985_8000 */
|
||||||
#define BL31_LIMIT 0xF9898000
|
#define BL31_LIMIT 0xF9898000
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -4,6 +4,9 @@
|
||||||
# SPDX-License-Identifier: BSD-3-Clause
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
#
|
#
|
||||||
|
|
||||||
|
# Enable version2 of image loading
|
||||||
|
LOAD_IMAGE_V2 := 1
|
||||||
|
|
||||||
# On Hikey, the TSP can execute from TZC secure area in DRAM (default)
|
# On Hikey, the TSP can execute from TZC secure area in DRAM (default)
|
||||||
# or SRAM.
|
# or SRAM.
|
||||||
HIKEY_TSP_RAM_LOCATION := dram
|
HIKEY_TSP_RAM_LOCATION := dram
|
||||||
|
@ -70,6 +73,12 @@ BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \
|
||||||
plat/hisilicon/hikey/hisi_dvfs.c \
|
plat/hisilicon/hikey/hisi_dvfs.c \
|
||||||
plat/hisilicon/hikey/hisi_mcu.c
|
plat/hisilicon/hikey/hisi_mcu.c
|
||||||
|
|
||||||
|
ifeq (${LOAD_IMAGE_V2},1)
|
||||||
|
BL2_SOURCES += plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c \
|
||||||
|
plat/hisilicon/hikey/hikey_image_load.c \
|
||||||
|
common/desc_image_load.c
|
||||||
|
endif
|
||||||
|
|
||||||
HIKEY_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
HIKEY_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
||||||
drivers/arm/gic/v2/gicv2_main.c \
|
drivers/arm/gic/v2/gicv2_main.c \
|
||||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||||
|
|
|
@ -74,12 +74,35 @@ meminfo_t *bl1_plat_sec_mem_layout(void)
|
||||||
return &bl1_tzram_layout;
|
return &bl1_tzram_layout;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if LOAD_IMAGE_V2
|
||||||
|
/*******************************************************************************
|
||||||
|
* Function that takes a memory layout into which BL2 has been loaded and
|
||||||
|
* populates a new memory layout for BL2 that ensures that BL1's data sections
|
||||||
|
* resident in secure RAM are not visible to BL2.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
|
||||||
|
meminfo_t *bl2_mem_layout)
|
||||||
|
{
|
||||||
|
|
||||||
|
assert(bl1_mem_layout != NULL);
|
||||||
|
assert(bl2_mem_layout != NULL);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Cannot remove BL1 RW data from the scope of memory visible to BL2
|
||||||
|
* like arm platforms because they overlap in hikey960
|
||||||
|
*/
|
||||||
|
bl2_mem_layout->total_base = BL2_BASE;
|
||||||
|
bl2_mem_layout->total_size = NS_BL1U_LIMIT - BL2_BASE;
|
||||||
|
|
||||||
|
flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
|
||||||
|
}
|
||||||
|
#endif /* LOAD_IMAGE_V2 */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Perform any BL1 specific platform actions.
|
* Perform any BL1 specific platform actions.
|
||||||
*/
|
*/
|
||||||
void bl1_early_platform_setup(void)
|
void bl1_early_platform_setup(void)
|
||||||
{
|
{
|
||||||
const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
|
|
||||||
unsigned int id, uart_base;
|
unsigned int id, uart_base;
|
||||||
|
|
||||||
generic_delay_timer_init();
|
generic_delay_timer_init();
|
||||||
|
@ -95,16 +118,18 @@ void bl1_early_platform_setup(void)
|
||||||
bl1_tzram_layout.total_base = BL1_RW_BASE;
|
bl1_tzram_layout.total_base = BL1_RW_BASE;
|
||||||
bl1_tzram_layout.total_size = BL1_RW_SIZE;
|
bl1_tzram_layout.total_size = BL1_RW_SIZE;
|
||||||
|
|
||||||
|
#if !LOAD_IMAGE_V2
|
||||||
/* Calculate how much RAM BL1 is using and how much remains free */
|
/* Calculate how much RAM BL1 is using and how much remains free */
|
||||||
bl1_tzram_layout.free_base = BL1_RW_BASE;
|
bl1_tzram_layout.free_base = BL1_RW_BASE;
|
||||||
bl1_tzram_layout.free_size = BL1_RW_SIZE;
|
bl1_tzram_layout.free_size = BL1_RW_SIZE;
|
||||||
reserve_mem(&bl1_tzram_layout.free_base,
|
reserve_mem(&bl1_tzram_layout.free_base,
|
||||||
&bl1_tzram_layout.free_size,
|
&bl1_tzram_layout.free_size,
|
||||||
BL1_RAM_BASE,
|
BL1_RAM_BASE,
|
||||||
bl1_size);
|
BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
|
||||||
|
#endif /* LOAD_IMAGE_V2 */
|
||||||
|
|
||||||
INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
|
INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
|
||||||
bl1_size);
|
BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -0,0 +1,128 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <bl_common.h>
|
||||||
|
#include <desc_image_load.h>
|
||||||
|
#include <platform.h>
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Following descriptor provides BL image/ep information that gets used
|
||||||
|
* by BL2 to load the images and also subset of this information is
|
||||||
|
* passed to next BL image. The image loading sequence is managed by
|
||||||
|
* populating the images in required loading order. The image execution
|
||||||
|
* sequence is managed by populating the `next_handoff_image_id` with
|
||||||
|
* the next executable image id.
|
||||||
|
******************************************************************************/
|
||||||
|
static bl_mem_params_node_t bl2_mem_params_descs[] = {
|
||||||
|
#ifdef SCP_BL2_BASE
|
||||||
|
/* Fill SCP_BL2 related information if it exists */
|
||||||
|
{
|
||||||
|
.image_id = SCP_BL2_IMAGE_ID,
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
|
||||||
|
VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
|
||||||
|
VERSION_2, image_info_t, 0),
|
||||||
|
.image_info.image_base = SCP_BL2_BASE,
|
||||||
|
.image_info.image_max_size = SCP_BL2_SIZE,
|
||||||
|
|
||||||
|
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||||
|
},
|
||||||
|
#endif /* SCP_BL2_BASE */
|
||||||
|
|
||||||
|
#ifdef EL3_PAYLOAD_BASE
|
||||||
|
/* Fill EL3 payload related information (BL31 is EL3 payload)*/
|
||||||
|
{
|
||||||
|
.image_id = BL31_IMAGE_ID,
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||||
|
VERSION_2, entry_point_info_t,
|
||||||
|
SECURE | EXECUTABLE | EP_FIRST_EXE),
|
||||||
|
.ep_info.pc = EL3_PAYLOAD_BASE,
|
||||||
|
.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
|
||||||
|
DISABLE_ALL_EXCEPTIONS),
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||||
|
VERSION_2, image_info_t,
|
||||||
|
IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
|
||||||
|
|
||||||
|
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||||
|
},
|
||||||
|
|
||||||
|
#else /* EL3_PAYLOAD_BASE */
|
||||||
|
|
||||||
|
/* Fill BL31 related information */
|
||||||
|
{
|
||||||
|
.image_id = BL31_IMAGE_ID,
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||||
|
VERSION_2, entry_point_info_t,
|
||||||
|
SECURE | EXECUTABLE | EP_FIRST_EXE),
|
||||||
|
.ep_info.pc = BL31_BASE,
|
||||||
|
.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
|
||||||
|
DISABLE_ALL_EXCEPTIONS),
|
||||||
|
#if DEBUG
|
||||||
|
.ep_info.args.arg1 = HIKEY960_BL31_PLAT_PARAM_VAL,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||||
|
VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
|
||||||
|
.image_info.image_base = BL31_BASE,
|
||||||
|
.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
|
||||||
|
|
||||||
|
# ifdef BL32_BASE
|
||||||
|
.next_handoff_image_id = BL32_IMAGE_ID,
|
||||||
|
# else
|
||||||
|
.next_handoff_image_id = BL33_IMAGE_ID,
|
||||||
|
# endif
|
||||||
|
},
|
||||||
|
|
||||||
|
# ifdef BL32_BASE
|
||||||
|
/* Fill BL32 related information */
|
||||||
|
{
|
||||||
|
.image_id = BL32_IMAGE_ID,
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||||
|
VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
|
||||||
|
.ep_info.pc = BL32_BASE,
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||||
|
VERSION_2, image_info_t, 0),
|
||||||
|
.image_info.image_base = BL32_BASE,
|
||||||
|
.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
|
||||||
|
|
||||||
|
.next_handoff_image_id = BL33_IMAGE_ID,
|
||||||
|
},
|
||||||
|
# endif /* BL32_BASE */
|
||||||
|
|
||||||
|
/* Fill BL33 related information */
|
||||||
|
{
|
||||||
|
.image_id = BL33_IMAGE_ID,
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||||
|
VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
|
||||||
|
# ifdef PRELOADED_BL33_BASE
|
||||||
|
.ep_info.pc = PRELOADED_BL33_BASE,
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||||
|
VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
|
||||||
|
# else
|
||||||
|
.ep_info.pc = NS_BL1U_BASE,
|
||||||
|
|
||||||
|
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||||
|
VERSION_2, image_info_t, 0),
|
||||||
|
.image_info.image_base = NS_BL1U_BASE,
|
||||||
|
.image_info.image_max_size = 0x200000 /* 2MB */,
|
||||||
|
# endif /* PRELOADED_BL33_BASE */
|
||||||
|
|
||||||
|
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||||
|
}
|
||||||
|
#endif /* EL3_PAYLOAD_BASE */
|
||||||
|
};
|
||||||
|
|
||||||
|
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
|
|
@ -9,6 +9,7 @@
|
||||||
#include <bl_common.h>
|
#include <bl_common.h>
|
||||||
#include <console.h>
|
#include <console.h>
|
||||||
#include <debug.h>
|
#include <debug.h>
|
||||||
|
#include <desc_image_load.h>
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
#include <generic_delay_timer.h>
|
#include <generic_delay_timer.h>
|
||||||
#include <hi3660.h>
|
#include <hi3660.h>
|
||||||
|
@ -41,6 +42,13 @@
|
||||||
|
|
||||||
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
|
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
|
||||||
|
|
||||||
|
#if !LOAD_IMAGE_V2
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This structure represents the superset of information that is passed to
|
||||||
|
* BL31, e.g. while passing control to it from BL2, bl31_params
|
||||||
|
* and other platform specific params
|
||||||
|
******************************************************************************/
|
||||||
typedef struct bl2_to_bl31_params_mem {
|
typedef struct bl2_to_bl31_params_mem {
|
||||||
bl31_params_t bl31_params;
|
bl31_params_t bl31_params;
|
||||||
image_info_t bl31_image_info;
|
image_info_t bl31_image_info;
|
||||||
|
@ -108,28 +116,29 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
|
void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
|
||||||
{
|
{
|
||||||
ufs_params_t ufs_params;
|
hikey960_init_ufs();
|
||||||
|
|
||||||
memset(&ufs_params, 0, sizeof(ufs_params_t));
|
|
||||||
ufs_params.reg_base = UFS_REG_BASE;
|
|
||||||
ufs_params.desc_base = HIKEY960_UFS_DESC_BASE;
|
|
||||||
ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE;
|
|
||||||
ufs_params.flags = UFS_FLAGS_SKIPINIT;
|
|
||||||
ufs_init(NULL, &ufs_params);
|
|
||||||
|
|
||||||
hikey960_io_setup();
|
hikey960_io_setup();
|
||||||
|
|
||||||
*scp_bl2_meminfo = bl2_tzram_layout;
|
*scp_bl2_meminfo = bl2_tzram_layout;
|
||||||
}
|
}
|
||||||
|
#endif /* LOAD_IMAGE_V2 */
|
||||||
|
|
||||||
extern int load_lpm3(void);
|
extern int load_lpm3(void);
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
|
||||||
|
* Return 0 on success, -1 otherwise.
|
||||||
|
******************************************************************************/
|
||||||
|
#if LOAD_IMAGE_V2
|
||||||
|
int plat_hikey960_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
|
||||||
|
#else
|
||||||
int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
|
int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
|
||||||
|
#endif
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
int *buf;
|
int *buf;
|
||||||
|
|
||||||
assert(scp_bl2_image_info->image_size < SCP_MEM_SIZE);
|
assert(scp_bl2_image_info->image_size < SCP_BL2_SIZE);
|
||||||
|
|
||||||
INFO("BL2: Initiating SCP_BL2 transfer to SCP\n");
|
INFO("BL2: Initiating SCP_BL2 transfer to SCP\n");
|
||||||
|
|
||||||
|
@ -152,10 +161,6 @@ int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
|
||||||
INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n",
|
INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n",
|
||||||
buf[i], buf[i+1], buf[i+2], buf[i+3]);
|
buf[i], buf[i+1], buf[i+2], buf[i+3]);
|
||||||
|
|
||||||
memcpy((void *)SCP_MEM_BASE,
|
|
||||||
(void *)scp_bl2_image_info->image_base,
|
|
||||||
scp_bl2_image_info->image_size);
|
|
||||||
|
|
||||||
INFO("BL2: SCP_BL2 transferred to SCP\n");
|
INFO("BL2: SCP_BL2 transferred to SCP\n");
|
||||||
|
|
||||||
load_lpm3();
|
load_lpm3();
|
||||||
|
@ -164,8 +169,121 @@ int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void hikey960_init_ufs(void)
|
||||||
|
{
|
||||||
|
ufs_params_t ufs_params;
|
||||||
|
|
||||||
|
memset(&ufs_params, 0, sizeof(ufs_params_t));
|
||||||
|
ufs_params.reg_base = UFS_REG_BASE;
|
||||||
|
ufs_params.desc_base = HIKEY960_UFS_DESC_BASE;
|
||||||
|
ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE;
|
||||||
|
ufs_params.flags = UFS_FLAGS_SKIPINIT;
|
||||||
|
ufs_init(NULL, &ufs_params);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Gets SPSR for BL32 entry
|
||||||
|
******************************************************************************/
|
||||||
|
uint32_t hikey960_get_spsr_for_bl32_entry(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* The Secure Payload Dispatcher service is responsible for
|
||||||
|
* setting the SPSR prior to entry into the BL3-2 image.
|
||||||
|
*/
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Gets SPSR for BL33 entry
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef AARCH32
|
||||||
|
uint32_t hikey960_get_spsr_for_bl33_entry(void)
|
||||||
|
{
|
||||||
|
unsigned int mode;
|
||||||
|
uint32_t spsr;
|
||||||
|
|
||||||
|
/* Figure out what mode we enter the non-secure world in */
|
||||||
|
mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TODO: Consider the possibility of specifying the SPSR in
|
||||||
|
* the FIP ToC and allowing the platform to have a say as
|
||||||
|
* well.
|
||||||
|
*/
|
||||||
|
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
|
||||||
|
return spsr;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
uint32_t hikey960_get_spsr_for_bl33_entry(void)
|
||||||
|
{
|
||||||
|
unsigned int hyp_status, mode, spsr;
|
||||||
|
|
||||||
|
hyp_status = GET_VIRT_EXT(read_id_pfr1());
|
||||||
|
|
||||||
|
mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TODO: Consider the possibility of specifying the SPSR in
|
||||||
|
* the FIP ToC and allowing the platform to have a say as
|
||||||
|
* well.
|
||||||
|
*/
|
||||||
|
spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
|
||||||
|
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
|
||||||
|
return spsr;
|
||||||
|
}
|
||||||
|
#endif /* AARCH32 */
|
||||||
|
|
||||||
|
#if LOAD_IMAGE_V2
|
||||||
|
int hikey960_bl2_handle_post_image_load(unsigned int image_id)
|
||||||
|
{
|
||||||
|
int err = 0;
|
||||||
|
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
||||||
|
assert(bl_mem_params);
|
||||||
|
|
||||||
|
switch (image_id) {
|
||||||
|
#ifdef AARCH64
|
||||||
|
case BL32_IMAGE_ID:
|
||||||
|
bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl32_entry();
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
case BL33_IMAGE_ID:
|
||||||
|
/* BL33 expects to receive the primary CPU MPID (through r0) */
|
||||||
|
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
|
||||||
|
bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl33_entry();
|
||||||
|
break;
|
||||||
|
|
||||||
|
#ifdef SCP_BL2_BASE
|
||||||
|
case SCP_BL2_IMAGE_ID:
|
||||||
|
/* The subsequent handling of SCP_BL2 is platform specific */
|
||||||
|
err = plat_hikey960_bl2_handle_scp_bl2(&bl_mem_params->image_info);
|
||||||
|
if (err) {
|
||||||
|
WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function can be used by the platforms to update/use image
|
||||||
|
* information for given `image_id`.
|
||||||
|
******************************************************************************/
|
||||||
|
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||||
|
{
|
||||||
|
return hikey960_bl2_handle_post_image_load(image_id);
|
||||||
|
}
|
||||||
|
|
||||||
|
#else /* LOAD_IMAGE_V2 */
|
||||||
|
|
||||||
struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
|
struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
|
||||||
{
|
{
|
||||||
|
#if DEBUG
|
||||||
|
bl31_params_mem.bl31_ep_info.args.arg1 = HIKEY960_BL31_PLAT_PARAM_VAL;
|
||||||
|
#endif
|
||||||
|
|
||||||
return &bl31_params_mem.bl31_ep_info;
|
return &bl31_params_mem.bl31_ep_info;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -250,6 +368,7 @@ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
|
||||||
bl33_meminfo->free_base = DDR_BASE;
|
bl33_meminfo->free_base = DDR_BASE;
|
||||||
bl33_meminfo->free_size = DDR_SIZE;
|
bl33_meminfo->free_size = DDR_SIZE;
|
||||||
}
|
}
|
||||||
|
#endif /* LOAD_IMAGE_V2 */
|
||||||
|
|
||||||
void bl2_early_platform_setup(meminfo_t *mem_layout)
|
void bl2_early_platform_setup(meminfo_t *mem_layout)
|
||||||
{
|
{
|
||||||
|
|
|
@ -76,8 +76,13 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if LOAD_IMAGE_V2
|
||||||
|
void bl31_early_platform_setup(void *from_bl2,
|
||||||
|
void *plat_params_from_bl2)
|
||||||
|
#else
|
||||||
void bl31_early_platform_setup(bl31_params_t *from_bl2,
|
void bl31_early_platform_setup(bl31_params_t *from_bl2,
|
||||||
void *plat_params_from_bl2)
|
void *plat_params_from_bl2)
|
||||||
|
#endif
|
||||||
{
|
{
|
||||||
unsigned int id, uart_base;
|
unsigned int id, uart_base;
|
||||||
|
|
||||||
|
@ -95,12 +100,50 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
|
||||||
cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map));
|
cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map));
|
||||||
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
|
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
|
||||||
|
|
||||||
|
#if LOAD_IMAGE_V2
|
||||||
|
/*
|
||||||
|
* Check params passed from BL2 should not be NULL,
|
||||||
|
*/
|
||||||
|
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
|
||||||
|
assert(params_from_bl2 != NULL);
|
||||||
|
assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
|
||||||
|
assert(params_from_bl2->h.version >= VERSION_2);
|
||||||
|
|
||||||
|
bl_params_node_t *bl_params = params_from_bl2->head;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copy BL33 and BL32 (if present), entry point information.
|
||||||
|
* They are stored in Secure RAM, in BL2's address space.
|
||||||
|
*/
|
||||||
|
while (bl_params) {
|
||||||
|
if (bl_params->image_id == BL32_IMAGE_ID)
|
||||||
|
bl32_ep_info = *bl_params->ep_info;
|
||||||
|
|
||||||
|
if (bl_params->image_id == BL33_IMAGE_ID)
|
||||||
|
bl33_ep_info = *bl_params->ep_info;
|
||||||
|
|
||||||
|
bl_params = bl_params->next_params_info;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (bl33_ep_info.pc == 0)
|
||||||
|
panic();
|
||||||
|
|
||||||
|
#else /* LOAD_IMAGE_V2 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check params passed from BL2 should not be NULL,
|
||||||
|
*/
|
||||||
|
assert(from_bl2 != NULL);
|
||||||
|
assert(from_bl2->h.type == PARAM_BL31);
|
||||||
|
assert(from_bl2->h.version >= VERSION_1);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Copy BL3-2 and BL3-3 entry point information.
|
* Copy BL3-2 and BL3-3 entry point information.
|
||||||
* They are stored in Secure RAM, in BL2's address space.
|
* They are stored in Secure RAM, in BL2's address space.
|
||||||
*/
|
*/
|
||||||
bl32_ep_info = *from_bl2->bl32_ep_info;
|
bl32_ep_info = *from_bl2->bl32_ep_info;
|
||||||
bl33_ep_info = *from_bl2->bl33_ep_info;
|
bl33_ep_info = *from_bl2->bl33_ep_info;
|
||||||
|
#endif /* LOAD_IMAGE_V2 */
|
||||||
}
|
}
|
||||||
|
|
||||||
void bl31_plat_arch_setup(void)
|
void bl31_plat_arch_setup(void)
|
||||||
|
|
|
@ -0,0 +1,40 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <bl_common.h>
|
||||||
|
#include <desc_image_load.h>
|
||||||
|
#include <platform.h>
|
||||||
|
|
||||||
|
#include "hikey960_private.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function flushes the data structures so that they are visible
|
||||||
|
* in memory for the next BL image.
|
||||||
|
******************************************************************************/
|
||||||
|
void plat_flush_next_bl_params(void)
|
||||||
|
{
|
||||||
|
flush_bl_params_desc();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns the list of loadable images.
|
||||||
|
******************************************************************************/
|
||||||
|
bl_load_info_t *plat_get_bl_image_load_info(void)
|
||||||
|
{
|
||||||
|
/* Required before loading scp_bl2 */
|
||||||
|
hikey960_init_ufs();
|
||||||
|
hikey960_io_setup();
|
||||||
|
|
||||||
|
return get_bl_load_info_from_mem_params_desc();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns the list of executable images.
|
||||||
|
******************************************************************************/
|
||||||
|
bl_params_t *plat_get_next_bl_params(void)
|
||||||
|
{
|
||||||
|
return get_next_bl_params_from_mem_params_desc();
|
||||||
|
}
|
|
@ -24,6 +24,7 @@ void hikey960_init_mmu_el3(unsigned long total_base,
|
||||||
unsigned long ro_limit,
|
unsigned long ro_limit,
|
||||||
unsigned long coh_start,
|
unsigned long coh_start,
|
||||||
unsigned long coh_limit);
|
unsigned long coh_limit);
|
||||||
|
void hikey960_init_ufs(void);
|
||||||
void hikey960_io_setup(void);
|
void hikey960_io_setup(void);
|
||||||
int hikey960_read_boardid(unsigned int *id);
|
int hikey960_read_boardid(unsigned int *id);
|
||||||
void set_retention_ticks(unsigned int val);
|
void set_retention_ticks(unsigned int val);
|
||||||
|
|
|
@ -10,6 +10,8 @@
|
||||||
#include <arch.h>
|
#include <arch.h>
|
||||||
#include "../hikey960_def.h"
|
#include "../hikey960_def.h"
|
||||||
|
|
||||||
|
/* Special value used to verify platform parameters from BL2 to BL3-1 */
|
||||||
|
#define HIKEY960_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Generic platform constants
|
* Generic platform constants
|
||||||
|
@ -91,10 +93,8 @@
|
||||||
#define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */
|
#define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */
|
||||||
#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
|
#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
|
||||||
|
|
||||||
#define SCP_BL2_BASE BL31_BASE /* 1AC5_8000 */
|
#define SCP_BL2_BASE (0x89C80000)
|
||||||
|
#define SCP_BL2_SIZE (0x00040000)
|
||||||
#define SCP_MEM_BASE (0x89C80000)
|
|
||||||
#define SCP_MEM_SIZE (0x00040000)
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Platform specific page table and MMU setup constants
|
* Platform specific page table and MMU setup constants
|
||||||
|
|
|
@ -4,6 +4,9 @@
|
||||||
# SPDX-License-Identifier: BSD-3-Clause
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
#
|
#
|
||||||
|
|
||||||
|
# Enable version2 of image loading
|
||||||
|
LOAD_IMAGE_V2 := 1
|
||||||
|
|
||||||
# On Hikey960, the TSP can execute from TZC secure area in DRAM.
|
# On Hikey960, the TSP can execute from TZC secure area in DRAM.
|
||||||
HIKEY960_TSP_RAM_LOCATION := dram
|
HIKEY960_TSP_RAM_LOCATION := dram
|
||||||
ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram)
|
ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram)
|
||||||
|
@ -61,6 +64,12 @@ BL2_SOURCES += drivers/io/io_block.c \
|
||||||
plat/hisilicon/hikey960/hikey960_io_storage.c \
|
plat/hisilicon/hikey960/hikey960_io_storage.c \
|
||||||
plat/hisilicon/hikey960/hikey960_mcu_load.c
|
plat/hisilicon/hikey960/hikey960_mcu_load.c
|
||||||
|
|
||||||
|
ifeq (${LOAD_IMAGE_V2},1)
|
||||||
|
BL2_SOURCES += plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c \
|
||||||
|
plat/hisilicon/hikey960/hikey960_image_load.c \
|
||||||
|
common/desc_image_load.c
|
||||||
|
endif
|
||||||
|
|
||||||
BL31_SOURCES += drivers/arm/cci/cci.c \
|
BL31_SOURCES += drivers/arm/cci/cci.c \
|
||||||
lib/cpus/aarch64/cortex_a53.S \
|
lib/cpus/aarch64/cortex_a53.S \
|
||||||
lib/cpus/aarch64/cortex_a72.S \
|
lib/cpus/aarch64/cortex_a72.S \
|
||||||
|
|
Loading…
Reference in New Issue