From 2ee2c4f0bb5f764cba9f306d1ccd6ef536dd1d59 Mon Sep 17 00:00:00 2001
From: Varun Wadekar <vwadekar@nvidia.com>
Date: Fri, 31 Jul 2015 10:15:41 +0530
Subject: [PATCH] Tegra132: set TZDRAM_BASE to 0xF5C00000

The TZDRAM base on the reference platform has been bumped up due to
some BL2 memory cleanup. Platforms can also use a different TZDRAM
base by setting TZDRAM_BASE=<value> in the build command line.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
---
 docs/plat/nvidia-tegra.md                   | 3 +++
 plat/nvidia/tegra/soc/t132/platform_t132.mk | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md
index 6c76dd109..d8e8ec63e 100644
--- a/docs/plat/nvidia-tegra.md
+++ b/docs/plat/nvidia-tegra.md
@@ -59,6 +59,9 @@ Preparing the BL31 image to run on Tegra SoCs
 'CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
 TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> all'
 
+Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>'
+to the build command line.
+
 Power Management
 ================
 The PSCI implementation expects each platform to expose the 'power state'
diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index 1be13e919..69d62964f 100644
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -31,7 +31,7 @@
 TEGRA_BOOT_UART_BASE		:= 0x70006300
 $(eval $(call add_define,TEGRA_BOOT_UART_BASE))
 
-TZDRAM_BASE			:= 0xF1C00000
+TZDRAM_BASE			:= 0xF5C00000
 $(eval $(call add_define,TZDRAM_BASE))
 
 PLATFORM_CLUSTER_COUNT		:= 1