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Merge pull request #1651 from antonio-nino-diaz-arm/an/rand-misra 

Fix some MISRA defects
This commit is contained in:
Antonio Niño Díaz 2018-10-30 15:48:02 +01:00 committed by GitHub
parent 392b1d591c 195e363f84
commit 2eedba9a55
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
30 changed files with 197 additions and 169 deletions
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12
include/lib/cpus/aarch64/cortex_a75.h
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@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A75_H__
#define __CORTEX_A75_H__
#ifndef CORTEX_A75_H
#define CORTEX_A75_H
#include <utils_def.h>
/* Cortex-A75 MIDR */
#define CORTEX_A75_MIDR 0x410fd0a0
#define CORTEX_A75_MIDR U(0x410fd0a0)
/*******************************************************************************
* CPU Extended Control register specific definitions.
@ -24,7 +26,7 @@
#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (1 << 35)
/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1
#define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1)
#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4)
@ -50,4 +52,4 @@ void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
#endif /* __ASSEMBLY__ */
#endif /* __CORTEX_A75_H__ */
#endif /* CORTEX_A75_H */

12
include/lib/cpus/aarch64/cortex_ares.h
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@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_ARES_H__
#define __CORTEX_ARES_H__
#ifndef CORTEX_ARES_H
#define CORTEX_ARES_H
#include <utils_def.h>
/* Cortex-ARES MIDR for revision 0 */
#define CORTEX_ARES_MIDR 0x410fd0c0
#define CORTEX_ARES_MIDR U(0x410fd0c0)
/*******************************************************************************
* CPU Extended Control register specific definitions.
@ -17,7 +19,7 @@
#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4
/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */
#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1
#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1)
#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4)
@ -30,4 +32,4 @@
#define CPUPOR_EL3 S3_6_C15_C8_2
#define CPUPMR_EL3 S3_6_C15_C8_3
#endif /* __CORTEX_ARES_H__ */
#endif /* CORTEX_ARES_H */

10
include/lib/cpus/aarch64/cpuamu.h
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@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CPUAMU_H__
#define __CPUAMU_H__
#ifndef CPUAMU_H
#define CPUAMU_H
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
@ -32,8 +32,8 @@
#ifndef __ASSEMBLY__
#include <stdint.h>
uint64_t cpuamu_cnt_read(int idx);
void cpuamu_cnt_write(int idx, uint64_t val);
uint64_t cpuamu_cnt_read(unsigned int idx);
void cpuamu_cnt_write(unsigned int idx, uint64_t val);
unsigned int cpuamu_read_cpuamcntenset_el0(void);
unsigned int cpuamu_read_cpuamcntenclr_el0(void);
void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
@ -45,4 +45,4 @@ void cpuamu_context_restore(unsigned int nr_counters);
#endif /* __ASSEMBLY__ */
#endif /* __CPUAMU_H__ */
#endif /* CPUAMU_H */

7
include/lib/cpus/errata_report.h
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@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __ERRATA_H__
#define __ERRATA_H__
#ifndef ERRATA_REPORT_H
#define ERRATA_REPORT_H
#ifndef __ASSEMBLY__
@ -30,5 +30,4 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported);
#define ERRATA_APPLIES 1
#define ERRATA_MISSING 2
#endif /* __ERRATA_H__ */
#endif /* ERRATA_REPORT_H */

6
include/lib/cpus/wa_cve_2017_5715.h
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@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __WA_CVE_2017_5715_H__
#define __WA_CVE_2017_5715_H__
#ifndef WA_CVE_2017_5715_H
#define WA_CVE_2017_5715_H
int check_wa_cve_2017_5715(void);
#endif /* __WA_CVE_2017_5715_H__ */
#endif /* WA_CVE_2017_5715_H */

6
include/lib/cpus/wa_cve_2018_3639.h
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@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __WA_CVE_2018_3639_H__
#define __WA_CVE_2018_3639_H__
#ifndef WA_CVE_2018_3639_H
#define WA_CVE_2018_3639_H
void *wa_cve_2018_3639_get_disable_ptr(void);
#endif /* __WA_CVE_2018_3639_H__ */
#endif /* WA_CVE_2018_3639_H */

6
include/lib/el3_runtime/cpu_data.h
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@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CPU_DATA_H__
#define __CPU_DATA_H__
#ifndef CPU_DATA_H
#define CPU_DATA_H
#include <ehf.h>
#include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */
@ -161,4 +161,4 @@ void init_cpu_ops(void);
#endif /* __ASSEMBLY__ */
#endif /* __CPU_DATA_H__ */
#endif /* CPU_DATA_H */

18
include/lib/extensions/amu.h
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@ -4,33 +4,35 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __AMU_H__
#define __AMU_H__
#ifndef AMU_H
#define AMU_H
#include <cassert.h>
#include <platform_def.h>
#include <stdbool.h>
#include <stdint.h>
#include <utils_def.h>
/* All group 0 counters */
#define AMU_GROUP0_COUNTERS_MASK 0xf
#define AMU_GROUP0_COUNTERS_MASK U(0xf)
#ifdef PLAT_AMU_GROUP1_COUNTERS_MASK
#define AMU_GROUP1_COUNTERS_MASK PLAT_AMU_GROUP1_COUNTERS_MASK
#else
#define AMU_GROUP1_COUNTERS_MASK 0
#define AMU_GROUP1_COUNTERS_MASK U(0)
#endif
#ifdef PLAT_AMU_GROUP1_NR_COUNTERS
#define AMU_GROUP1_NR_COUNTERS PLAT_AMU_GROUP1_NR_COUNTERS
#else
#define AMU_GROUP1_NR_COUNTERS 0
#define AMU_GROUP1_NR_COUNTERS U(0)
#endif
CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask);
CASSERT(AMU_GROUP1_NR_COUNTERS <= 16, invalid_amu_group1_nr_counters);
int amu_supported(void);
void amu_enable(int el2_unused);
bool amu_supported(void);
void amu_enable(bool el2_unused);
/* Group 0 configuration helpers */
uint64_t amu_group0_cnt_read(int idx);
@ -41,4 +43,4 @@ uint64_t amu_group1_cnt_read(int idx);
void amu_group1_cnt_write(int idx, uint64_t val);
void amu_group1_set_evtype(int idx, unsigned int val);
#endif /* __AMU_H__ */
#endif /* AMU_H */

12
include/lib/extensions/amu_private.h
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@ -1,19 +1,19 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __AMU_PRIVATE_H__
#define __AMU_PRIVATE_H__
#ifndef AMU_PRIVATE_H
#define AMU_PRIVATE_H
#include <stdint.h>
uint64_t amu_group0_cnt_read_internal(int idx);
void amu_group0_cnt_write_internal(int idx, uint64_t);
void amu_group0_cnt_write_internal(int idx, uint64_t val);
uint64_t amu_group1_cnt_read_internal(int idx);
void amu_group1_cnt_write_internal(int idx, uint64_t);
void amu_group1_cnt_write_internal(int idx, uint64_t val);
void amu_group1_set_evtype_internal(int idx, unsigned int val);
#endif /* __AMU_PRIVATE_H__ */
#endif /* AMU_PRIVATE_H */

2
include/lib/extensions/mpam.h
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@ -10,6 +10,6 @@
#include <stdbool.h>
bool mpam_supported(void);
void mpam_enable(int el2_unused);
void mpam_enable(bool el2_unused);
#endif /* MPAM_H */

12
include/lib/extensions/spe.h
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@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SPE_H__
#define __SPE_H__
#ifndef SPE_H
#define SPE_H
int spe_supported(void);
void spe_enable(int el2_unused);
#include <stdbool.h>
bool spe_supported(void);
void spe_enable(bool el2_unused);
void spe_disable(void);
#endif /* __SPE_H__ */
#endif /* SPE_H */

12
include/lib/extensions/sve.h
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@ -4,10 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SVE_H__
#define __SVE_H__
#ifndef SVE_H
#define SVE_H
int sve_supported(void);
void sve_enable(int el2_unused);
#include <stdbool.h>
#endif /* __SVE_H__ */
bool sve_supported(void);
void sve_enable(bool el2_unused);
#endif /* SVE_H */

17
include/lib/pmf/pmf.h
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@ -9,17 +9,18 @@
#include <cassert.h>
#include <pmf_helpers.h>
#include <utils_def.h>
/*
* Constants used for/by PMF services.
*/
#define PMF_ARM_TIF_IMPL_ID 0x41
#define PMF_ARM_TIF_IMPL_ID U(0x41)
#define PMF_TID_SHIFT 0
#define PMF_TID_MASK (0xFF << PMF_TID_SHIFT)
#define PMF_TID_MASK (U(0xFF) << PMF_TID_SHIFT)
#define PMF_SVC_ID_SHIFT 10
#define PMF_SVC_ID_MASK (0x3F << PMF_SVC_ID_SHIFT)
#define PMF_SVC_ID_MASK (U(0x3F) << PMF_SVC_ID_SHIFT)
#define PMF_IMPL_ID_SHIFT 24
#define PMF_IMPL_ID_MASK (0xFFU << PMF_IMPL_ID_SHIFT)
#define PMF_IMPL_ID_MASK (U(0xFF) << PMF_IMPL_ID_SHIFT)
/*
* Flags passed to PMF_REGISTER_SERVICE
@ -37,16 +38,16 @@
/*
* Defines for PMF SMC function ids.
*/
#define PMF_SMC_GET_TIMESTAMP_32 0x82000010u
#define PMF_SMC_GET_TIMESTAMP_64 0xC2000010u
#define PMF_SMC_GET_TIMESTAMP_32 U(0x82000010)
#define PMF_SMC_GET_TIMESTAMP_64 U(0xC2000010)
#define PMF_NUM_SMC_CALLS 2
/*
* The macros below are used to identify
* PMF calls from the SMC function ID.
*/
#define PMF_FID_MASK 0xffe0u
#define PMF_FID_VALUE 0u
#define PMF_FID_MASK U(0xffe0)
#define PMF_FID_VALUE U(0)
#define is_pmf_fid(_fid) (((_fid) & PMF_FID_MASK) == PMF_FID_VALUE)
/* Following are the supported PMF service IDs */

1
include/lib/pmf/pmf_helpers.h
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@ -11,7 +11,6 @@
#include <assert.h>
#include <bl_common.h>
#include <platform.h>
#include <pmf.h>
#include <stddef.h>
#include <stdint.h>

24
include/plat/arm/common/arm_sip_svc.h
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@ -1,24 +1,26 @@
/*
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __ARM_SIP_SVC_H__
#define __ARM_SIP_SVC_H__
#ifndef ARM_SIP_SVC_H
#define ARM_SIP_SVC_H
#include <utils_def.h>
/* SMC function IDs for SiP Service queries */
#define ARM_SIP_SVC_CALL_COUNT 0x8200ff00
#define ARM_SIP_SVC_UID 0x8200ff01
/* 0x8200ff02 is reserved */
#define ARM_SIP_SVC_VERSION 0x8200ff03
#define ARM_SIP_SVC_CALL_COUNT U(0x8200ff00)
#define ARM_SIP_SVC_UID U(0x8200ff01)
/* U(0x8200ff02) is reserved */
#define ARM_SIP_SVC_VERSION U(0x8200ff03)
/* Function ID for requesting state switch of lower EL */
#define ARM_SIP_SVC_EXE_STATE_SWITCH 0x82000020
#define ARM_SIP_SVC_EXE_STATE_SWITCH U(0x82000020)
/* ARM SiP Service Calls version numbers */
#define ARM_SIP_SVC_VERSION_MAJOR 0x0
#define ARM_SIP_SVC_VERSION_MINOR 0x2
#define ARM_SIP_SVC_VERSION_MAJOR U(0x0)
#define ARM_SIP_SVC_VERSION_MINOR U(0x2)
#endif /* __ARM_SIP_SVC_H__ */
#endif /* ARM_SIP_SVC_H */

6
include/plat/arm/common/plat_arm.h
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@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __PLAT_ARM_H__
#define __PLAT_ARM_H__
#ifndef PLAT_ARM_H
#define PLAT_ARM_H
#include <bakery_lock.h>
#include <cassert.h>
@ -292,4 +292,4 @@ extern plat_psci_ops_t plat_arm_psci_pm_ops;
extern const mmap_region_t plat_arm_mmap[];
extern const unsigned int arm_pm_idle_states[];
#endif /* __PLAT_ARM_H__ */
#endif /* PLAT_ARM_H */

6
lib/cpus/aarch64/cortex_a75_pubsub.c
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@ -12,14 +12,16 @@ static void *cortex_a75_context_save(const void *arg)
{
if (midr_match(CORTEX_A75_MIDR) != 0)
cpuamu_context_save(CORTEX_A75_AMU_NR_COUNTERS);
return 0;
return (void *)0;
}
static void *cortex_a75_context_restore(const void *arg)
{
if (midr_match(CORTEX_A75_MIDR) != 0)
cpuamu_context_restore(CORTEX_A75_AMU_NR_COUNTERS);
return 0;
return (void *)0;
}
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_a75_context_save);

6
lib/cpus/aarch64/cortex_ares_pubsub.c
View File

@ -12,14 +12,16 @@ static void *cortex_ares_context_save(const void *arg)
{
if (midr_match(CORTEX_ARES_MIDR) != 0)
cpuamu_context_save(CORTEX_ARES_AMU_NR_COUNTERS);
return 0;
return (void *)0;
}
static void *cortex_ares_context_restore(const void *arg)
{
if (midr_match(CORTEX_ARES_MIDR) != 0)
cpuamu_context_restore(CORTEX_ARES_AMU_NR_COUNTERS);
return 0;
return (void *)0;
}
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_ares_context_save);

4
lib/cpus/aarch64/cpuamu_helpers.S
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@ -16,7 +16,7 @@
.globl cpuamu_write_cpuamcntenclr_el0
/*
* uint64_t cpuamu_cnt_read(int idx);
* uint64_t cpuamu_cnt_read(unsigned int idx);
*
* Given `idx`, read the corresponding AMU counter
* and return it in `x0`.
@ -41,7 +41,7 @@ func cpuamu_cnt_read
endfunc cpuamu_cnt_read
/*
* void cpuamu_cnt_write(int idx, uint64_t val);
* void cpuamu_cnt_write(unsigned int idx, uint64_t val);
*
* Given `idx`, write `val` to the corresponding AMU counter.
*/

11
lib/cpus/errata_report.c
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@ -12,6 +12,7 @@
#include <debug.h>
#include <errata_report.h>
#include <spinlock.h>
#include <stdbool.h>
#include <utils.h>
#ifdef IMAGE_BL1
@ -35,10 +36,10 @@
*/
int errata_needs_reporting(spinlock_t *lock, uint32_t *reported)
{
int report_now;
bool report_now;
/* If already reported, return false. */
if (*reported)
if (*reported != 0U)
return 0;
/*
@ -46,7 +47,7 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported)
* report status to true.
*/
spin_lock(lock);
report_now = !(*reported);
report_now = (*reported == 0U);
if (report_now)
*reported = 1;
spin_unlock(lock);
@ -75,8 +76,8 @@ void errata_print_msg(unsigned int status, const char *cpu, const char *id)
assert(status < ARRAY_SIZE(errata_status_str));
assert(cpu);
assert(id);
assert(cpu != NULL);
assert(id != NULL);
msg = errata_status_str[status];

7
lib/el3_runtime/aarch32/context_mgmt.c
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@ -14,6 +14,7 @@
#include <platform.h>
#include <platform_def.h>
#include <smccc_helpers.h>
#include <stdbool.h>
#include <string.h>
#include <utils.h>
@ -129,7 +130,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
* When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
* it is zero.
******************************************************************************/
static void enable_extensions_nonsecure(int el2_unused)
static void enable_extensions_nonsecure(bool el2_unused)
{
#if IMAGE_BL32
#if ENABLE_AMU
@ -175,7 +176,7 @@ void cm_prepare_el3_exit(uint32_t security_state)
{
uint32_t hsctlr, scr;
cpu_context_t *ctx = cm_get_context(security_state);
int el2_unused = 0;
bool el2_unused = false;
assert(ctx);
@ -200,7 +201,7 @@ void cm_prepare_el3_exit(uint32_t security_state)
isb();
} else if (read_id_pfr1() &
(ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) {
el2_unused = 1;
el2_unused = true;
/*
* Set the NS bit to access NS copies of certain banked

7
lib/el3_runtime/aarch64/context_mgmt.c
View File

@ -18,6 +18,7 @@
#include <pubsub_events.h>
#include <smccc_helpers.h>
#include <spe.h>
#include <stdbool.h>
#include <string.h>
#include <sve.h>
#include <utils.h>
@ -231,7 +232,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
* When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
* it is zero.
******************************************************************************/
static void enable_extensions_nonsecure(int el2_unused)
static void enable_extensions_nonsecure(bool el2_unused)
{
#if IMAGE_BL31
#if ENABLE_SPE_FOR_LOWER_ELS
@ -289,7 +290,7 @@ void cm_prepare_el3_exit(uint32_t security_state)
{
uint32_t sctlr_elx, scr_el3, mdcr_el2;
cpu_context_t *ctx = cm_get_context(security_state);
int el2_unused = 0;
bool el2_unused = false;
uint64_t hcr_el2 = 0;
assert(ctx);
@ -304,7 +305,7 @@ void cm_prepare_el3_exit(uint32_t security_state)
sctlr_elx |= SCTLR_EL2_RES1;
write_sctlr_el2(sctlr_elx);
} else if (EL_IMPLEMENTED(2)) {
el2_unused = 1;
el2_unused = true;
/*
* EL2 present but unused, need to disable safely.

39
lib/extensions/amu/aarch32/amu.c
View File

@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <platform.h>
#include <pubsub_events.h>
#include <stdbool.h>
#define AMU_GROUP0_NR_COUNTERS 4
@ -20,17 +21,17 @@ struct amu_ctx {
static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
int amu_supported(void)
bool amu_supported(void)
{
uint64_t features;
features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
return (features & ID_PFR0_AMU_MASK) == 1;
return (features & ID_PFR0_AMU_MASK) == 1U;
}
void amu_enable(int el2_unused)
void amu_enable(bool el2_unused)
{
if (amu_supported() == 0)
if (!amu_supported())
return;
if (el2_unused) {
@ -54,8 +55,8 @@ void amu_enable(int el2_unused)
/* Read the group 0 counter identified by the given `idx`. */
uint64_t amu_group0_cnt_read(int idx)
{
assert(amu_supported() != 0);
assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
return amu_group0_cnt_read_internal(idx);
}
@ -63,8 +64,8 @@ uint64_t amu_group0_cnt_read(int idx)
/* Write the group 0 counter identified by the given `idx` with `val`. */
void amu_group0_cnt_write(int idx, uint64_t val)
{
assert(amu_supported() != 0);
assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
amu_group0_cnt_write_internal(idx, val);
isb();
@ -73,8 +74,8 @@ void amu_group0_cnt_write(int idx, uint64_t val)
/* Read the group 1 counter identified by the given `idx`. */
uint64_t amu_group1_cnt_read(int idx)
{
assert(amu_supported() != 0);
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
return amu_group1_cnt_read_internal(idx);
}
@ -82,8 +83,8 @@ uint64_t amu_group1_cnt_read(int idx)
/* Write the group 1 counter identified by the given `idx` with `val`. */
void amu_group1_cnt_write(int idx, uint64_t val)
{
assert(amu_supported() != 0);
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
amu_group1_cnt_write_internal(idx, val);
isb();
@ -91,8 +92,8 @@ void amu_group1_cnt_write(int idx, uint64_t val)
void amu_group1_set_evtype(int idx, unsigned int val)
{
assert(amu_supported() != 0);
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
amu_group1_set_evtype_internal(idx, val);
isb();
@ -103,7 +104,7 @@ static void *amu_context_save(const void *arg)
struct amu_ctx *ctx;
int i;
if (amu_supported() == 0)
if (!amu_supported())
return (void *)-1;
ctx = &amu_ctxs[plat_my_core_pos()];
@ -126,7 +127,7 @@ static void *amu_context_save(const void *arg)
for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
ctx->group1_cnts[i] = amu_group1_cnt_read(i);
return 0;
return (void *)0;
}
static void *amu_context_restore(const void *arg)
@ -134,13 +135,13 @@ static void *amu_context_restore(const void *arg)
struct amu_ctx *ctx;
int i;
if (amu_supported() == 0)
if (!amu_supported())
return (void *)-1;
ctx = &amu_ctxs[plat_my_core_pos()];
/* Counters were disabled in `amu_context_save()` */
assert(read_amcntenset0() == 0 && read_amcntenset1() == 0);
assert((read_amcntenset0() == 0U) && (read_amcntenset1() == 0U));
/* Restore group 0 counters */
for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
@ -153,7 +154,7 @@ static void *amu_context_restore(const void *arg)
/* Enable group 1 counters */
write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
return 0;
return (void *)0;
}
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save);

51
lib/extensions/amu/aarch64/amu.c
View File

@ -11,6 +11,7 @@
#include <assert.h>
#include <platform.h>
#include <pubsub_events.h>
#include <stdbool.h>
#define AMU_GROUP0_NR_COUNTERS 4
@ -21,23 +22,23 @@ struct amu_ctx {
static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
int amu_supported(void)
bool amu_supported(void)
{
uint64_t features;
features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT;
return (features & ID_AA64PFR0_AMU_MASK) == 1;
return (features & ID_AA64PFR0_AMU_MASK) == 1U;
}
/*
* Enable counters. This function is meant to be invoked
* by the context management library before exiting from EL3.
*/
void amu_enable(int el2_unused)
void amu_enable(bool el2_unused)
{
uint64_t v;
if (amu_supported() == 0)
if (!amu_supported())
return;
if (el2_unused) {
@ -67,8 +68,8 @@ void amu_enable(int el2_unused)
/* Read the group 0 counter identified by the given `idx`. */
uint64_t amu_group0_cnt_read(int idx)
{
assert(amu_supported() != 0);
assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
return amu_group0_cnt_read_internal(idx);
}
@ -76,8 +77,8 @@ uint64_t amu_group0_cnt_read(int idx)
/* Write the group 0 counter identified by the given `idx` with `val`. */
void amu_group0_cnt_write(int idx, uint64_t val)
{
assert(amu_supported() != 0);
assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
amu_group0_cnt_write_internal(idx, val);
isb();
@ -86,8 +87,8 @@ void amu_group0_cnt_write(int idx, uint64_t val)
/* Read the group 1 counter identified by the given `idx`. */
uint64_t amu_group1_cnt_read(int idx)
{
assert(amu_supported() != 0);
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
return amu_group1_cnt_read_internal(idx);
}
@ -95,8 +96,8 @@ uint64_t amu_group1_cnt_read(int idx)
/* Write the group 1 counter identified by the given `idx` with `val`. */
void amu_group1_cnt_write(int idx, uint64_t val)
{
assert(amu_supported() != 0);
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
amu_group1_cnt_write_internal(idx, val);
isb();
@ -108,8 +109,8 @@ void amu_group1_cnt_write(int idx, uint64_t val)
*/
void amu_group1_set_evtype(int idx, unsigned int val)
{
assert(amu_supported() != 0);
assert (idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
assert(amu_supported());
assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
amu_group1_set_evtype_internal(idx, val);
isb();
@ -120,14 +121,14 @@ static void *amu_context_save(const void *arg)
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
int i;
if (amu_supported() == 0)
if (!amu_supported())
return (void *)-1;
/* Assert that group 0/1 counter configuration is what we expect */
assert(read_amcntenset0_el0() == AMU_GROUP0_COUNTERS_MASK &&
read_amcntenset1_el0() == AMU_GROUP1_COUNTERS_MASK);
assert((read_amcntenset0_el0() == AMU_GROUP0_COUNTERS_MASK) &&
(read_amcntenset1_el0() == AMU_GROUP1_COUNTERS_MASK));
assert((sizeof(int) * 8) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK)
assert(((sizeof(int) * 8) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK))
<= AMU_GROUP1_NR_COUNTERS);
/*
@ -146,7 +147,7 @@ static void *amu_context_save(const void *arg)
for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
ctx->group1_cnts[i] = amu_group1_cnt_read(i);
return 0;
return (void *)0;
}
static void *amu_context_restore(const void *arg)
@ -154,30 +155,30 @@ static void *amu_context_restore(const void *arg)
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
int i;
if (amu_supported() == 0)
if (!amu_supported())
return (void *)-1;
/* Counters were disabled in `amu_context_save()` */
assert(read_amcntenset0_el0() == 0 && read_amcntenset1_el0() == 0);
assert((read_amcntenset0_el0() == 0U) && (read_amcntenset1_el0() == 0U));
assert((sizeof(int) * 8) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK)
assert(((sizeof(int) * 8U) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK))
<= AMU_GROUP1_NR_COUNTERS);
/* Restore group 0 counters */
for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
if (AMU_GROUP0_COUNTERS_MASK & (1U << i))
if ((AMU_GROUP0_COUNTERS_MASK & (1U << i)) != 0U)
amu_group0_cnt_write(i, ctx->group0_cnts[i]);
/* Restore group 1 counters */
for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
if (AMU_GROUP1_COUNTERS_MASK & (1U << i))
if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U)
amu_group1_cnt_write(i, ctx->group1_cnts[i]);
/* Restore group 0/1 counter configuration */
write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK);
return 0;
return (void *)0;
}
SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save);

4
lib/extensions/mpam/mpam.c
View File

@ -16,7 +16,7 @@ bool mpam_supported(void)
return ((features & ID_AA64PFR0_MPAM_MASK) != 0U);
}
void mpam_enable(int el2_unused)
void mpam_enable(bool el2_unused)
{
if (!mpam_supported())
return;
@ -31,7 +31,7 @@ void mpam_enable(int el2_unused)
* If EL2 is implemented but unused, disable trapping to EL2 when lower
* ELs access their own MPAM registers.
*/
if (el2_unused != 0) {
if (el2_unused) {
write_mpam2_el2(0);
if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U)

29
lib/extensions/spe/spe.c
View File

@ -8,26 +8,30 @@
#include <arch_helpers.h>
#include <pubsub.h>
#include <spe.h>
#include <stdbool.h>
/*
* The assembler does not yet understand the psb csync mnemonic
* so use the equivalent hint instruction.
*/
#define psb_csync() asm volatile("hint #17")
static inline void psb_csync(void)
{
/*
* The assembler does not yet understand the psb csync mnemonic
* so use the equivalent hint instruction.
*/
__asm__ volatile("hint #17");
}
int spe_supported(void)
bool spe_supported(void)
{
uint64_t features;
features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
return (features & ID_AA64DFR0_PMS_MASK) == 1;
return (features & ID_AA64DFR0_PMS_MASK) == 1U;
}
void spe_enable(int el2_unused)
void spe_enable(bool el2_unused)
{
uint64_t v;
if (spe_supported() == 0)
if (!spe_supported())
return;
if (el2_unused) {
@ -59,7 +63,7 @@ void spe_disable(void)
{
uint64_t v;
if (spe_supported() == 0)
if (!spe_supported())
return;
/* Drain buffered data */
@ -75,13 +79,14 @@ void spe_disable(void)
static void *spe_drain_buffers_hook(const void *arg)
{
if (spe_supported() == 0)
if (!spe_supported())
return (void *)-1;
/* Drain buffered data */
psb_csync();
dsbnsh();
return 0;
return (void *)0;
}
SUBSCRIBE_TO_EVENT(cm_entering_secure_world, spe_drain_buffers_hook);

17
lib/extensions/sve/sve.c
View File

@ -7,21 +7,22 @@
#include <arch.h>
#include <arch_helpers.h>
#include <pubsub.h>
#include <stdbool.h>
#include <sve.h>
int sve_supported(void)
bool sve_supported(void)
{
uint64_t features;
features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
return (features & ID_AA64PFR0_SVE_MASK) == 1;
return (features & ID_AA64PFR0_SVE_MASK) == 1U;
}
static void *disable_sve_hook(const void *arg)
{
uint64_t cptr;
if (sve_supported() == 0)
if (!sve_supported())
return (void *)-1;
/*
@ -39,14 +40,14 @@ static void *disable_sve_hook(const void *arg)
* No explicit ISB required here as ERET to switch to Secure
* world covers it
*/
return 0;
return (void *)0;
}
static void *enable_sve_hook(const void *arg)
{
uint64_t cptr;
if (sve_supported() == 0)
if (!sve_supported())
return (void *)-1;
/*
@ -60,14 +61,14 @@ static void *enable_sve_hook(const void *arg)
* No explicit ISB required here as ERET to switch to Non-secure
* world covers it
*/
return 0;
return (void *)0;
}
void sve_enable(int el2_unused)
void sve_enable(bool el2_unused)
{
uint64_t cptr;
if (sve_supported() == 0)
if (!sve_supported())
return;
#if CTX_INCLUDE_FPREGS

14
lib/pmf/pmf_main.c
View File

@ -26,7 +26,7 @@
IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_START__, PMF_SVC_DESCS_START);
IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_END__, PMF_SVC_DESCS_END);
IMPORT_SYM(uintptr_t, __PMF_PERCPU_TIMESTAMP_END__, PMF_PERCPU_TIMESTAMP_END);
IMPORT_SYM(intptr_t, __PMF_TIMESTAMP_START__, PMF_TIMESTAMP_ARRAY_START);
IMPORT_SYM(uintptr_t, __PMF_TIMESTAMP_START__, PMF_TIMESTAMP_ARRAY_START);
#define PMF_PERCPU_TIMESTAMP_SIZE (PMF_PERCPU_TIMESTAMP_END - PMF_TIMESTAMP_ARRAY_START)
@ -67,15 +67,15 @@ int pmf_setup(void)
pmf_svc_descs = (pmf_svc_desc_t *) PMF_SVC_DESCS_START;
for (ii = 0; ii < pmf_svc_descs_num; ii++) {
assert(pmf_svc_descs[ii].get_ts);
assert(pmf_svc_descs[ii].get_ts != NULL);
/*
* Call the initialization routine for this
* PMF service, if it is defined.
*/
if (pmf_svc_descs[ii].init) {
if (pmf_svc_descs[ii].init != NULL) {
rc = pmf_svc_descs[ii].init();
if (rc) {
if (rc != 0) {
WARN("Could not initialize PMF"
"service %s - skipping \n",
pmf_svc_descs[ii].name);
@ -125,7 +125,7 @@ static pmf_svc_desc_t *get_service(unsigned int tid)
if (pmf_num_services == 0)
return NULL;
assert(pmf_svc_descs);
assert(pmf_svc_descs != NULL);
do {
mid = (low + high) / 2;
@ -158,7 +158,7 @@ int pmf_get_timestamp_smc(unsigned int tid,
unsigned long long *ts_value)
{
pmf_svc_desc_t *svc_desc;
assert(ts_value);
assert(ts_value != NULL);
/* Search for registered service. */
svc_desc = get_service(tid);
@ -247,7 +247,7 @@ unsigned long long __pmf_get_timestamp(uintptr_t base_addr,
unsigned long long *ts_addr = (unsigned long long *)calc_ts_addr(base_addr,
tid, cpuid);
if (flags & PMF_CACHE_MAINT)
if ((flags & PMF_CACHE_MAINT) != 0U)
inv_dcache_range((uintptr_t)ts_addr, sizeof(unsigned long long));
return *ts_addr;

6
lib/pmf/pmf_smc.c
View File

@ -37,7 +37,8 @@ uintptr_t pmf_smc_handler(unsigned int smc_fid,
* x0 --> error code.
* x1 - x2 --> time-stamp value.
*/
rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value);
rc = pmf_get_timestamp_smc((unsigned int)x1, x2,
(unsigned int)x3, &ts_value);
SMC_RET3(handle, rc, (uint32_t)ts_value,
(uint32_t)(ts_value >> 32));
}
@ -49,7 +50,8 @@ uintptr_t pmf_smc_handler(unsigned int smc_fid,
* x0 --> error code.
* x1 --> time-stamp value.
*/
rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value);
rc = pmf_get_timestamp_smc((unsigned int)x1, x2,
(unsigned int)x3, &ts_value);
SMC_RET2(handle, rc, ts_value);
}
}

2
plat/arm/common/arm_sip_svc.c
View File

@ -58,7 +58,7 @@ static uintptr_t arm_sip_handler(unsigned int smc_fid,
/* Validate supplied entry point */
pc = (u_register_t) ((x1 << 32) | (uint32_t) x2);
if (arm_validate_ns_entrypoint(pc))
if (arm_validate_ns_entrypoint(pc) != 0)
SMC_RET1(handle, STATE_SW_E_PARAM);
/*