drivers: renesas: rcar: scif: Fix coding style
Replace TAB with space after #define macros and update comments as per TF-A coding style. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: Iff46838a41f991f7dd9dc6fb043e9e482ea0b11d
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Biju Das
parent
c58633854b
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2f943087b3
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,43 +9,43 @@
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#include <console_macros.S>
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#include <drivers/renesas/rcar/console/console.h>
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#define SCIF_INTERNAL_CLK 0
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#define SCIF_EXTARNAL_CLK 1
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#define SCIF_CLK SCIF_INTERNAL_CLK
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#define SCIF_INTERNAL_CLK 0
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#define SCIF_EXTARNAL_CLK 1
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#define SCIF_CLK SCIF_INTERNAL_CLK
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/* product register */
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#define PRR (0xFFF00044)
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#define PRR_PRODUCT_MASK (0x00007F00)
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#define PRR_CUT_MASK (0x000000FF)
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#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
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#define PRR_PRODUCT_E3 (0x00005700)
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#define PRR_PRODUCT_D3 (0x00005800)
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#define PRR (0xFFF00044)
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#define PRR_PRODUCT_MASK (0x00007F00)
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#define PRR_CUT_MASK (0x000000FF)
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#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
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#define PRR_PRODUCT_E3 (0x00005700)
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#define PRR_PRODUCT_D3 (0x00005800)
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/* module stop */
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#define CPG_BASE (0xE6150000)
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#define CPG_SMSTPCR2 (0x0138)
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#define CPG_SMSTPCR3 (0x013C)
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#define CPG_BASE (0xE6150000)
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#define CPG_SMSTPCR2 (0x0138)
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#define CPG_SMSTPCR3 (0x013C)
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#define CPG_MSTPSR2 (0x0040)
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#define CPG_MSTPSR3 (0x0048)
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#define MSTP207 (1 << 7)
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#define MSTP310 (1 << 10)
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#define CPG_CPGWPR (0x0900)
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#define CPG_MSTPSR3 (0x0048)
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#define MSTP207 (1 << 7)
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#define MSTP310 (1 << 10)
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#define CPG_CPGWPR (0x0900)
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/* scif */
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#define SCIF0_BASE (0xE6E60000)
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#define SCIF2_BASE (0xE6E88000)
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#define SCIF_SCSMR (0x00)
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#define SCIF_SCBRR (0x04)
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#define SCIF_SCSCR (0x08)
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#define SCIF_SCFTDR (0x0C)
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#define SCIF_SCFSR (0x10)
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#define SCIF_SCFRDR (0x14)
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#define SCIF_SCFCR (0x18)
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#define SCIF_SCFDR (0x1C)
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#define SCIF_SCSPTR (0x20)
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#define SCIF_SCLSR (0x24)
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#define SCIF_DL (0x30)
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#define SCIF_CKS (0x34)
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#define SCIF0_BASE (0xE6E60000)
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#define SCIF2_BASE (0xE6E88000)
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#define SCIF_SCSMR (0x00)
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#define SCIF_SCBRR (0x04)
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#define SCIF_SCSCR (0x08)
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#define SCIF_SCFTDR (0x0C)
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#define SCIF_SCFSR (0x10)
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#define SCIF_SCFRDR (0x14)
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#define SCIF_SCFCR (0x18)
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#define SCIF_SCFDR (0x1C)
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#define SCIF_SCSPTR (0x20)
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#define SCIF_SCLSR (0x24)
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#define SCIF_DL (0x30)
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#define SCIF_CKS (0x34)
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#if RCAR_LSI == RCAR_V3M
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#define SCIF_BASE SCIF0_BASE
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@ -60,70 +60,71 @@
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#endif
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/* mode pin */
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#define RST_MODEMR (0xE6160060)
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#define MODEMR_MD12 (0x00001000)
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#define RST_MODEMR (0xE6160060)
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#define MODEMR_MD12 (0x00001000)
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#define SCSMR_CA_MASK (1 << 7)
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#define SCSMR_CA_ASYNC (0x0000)
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#define SCSMR_CHR_MASK (1 << 6)
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#define SCSMR_CHR_8 (0x0000)
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#define SCSMR_PE_MASK (1 << 5)
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#define SCSMR_PE_DIS (0x0000)
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#define SCSMR_STOP_MASK (1 << 3)
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#define SCSMR_STOP_1 (0x0000)
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#define SCSMR_CKS_MASK (3 << 0)
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#define SCSMR_CKS_DIV1 (0x0000)
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#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
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#define SCSMR_CA_MASK (1 << 7)
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#define SCSMR_CA_ASYNC (0x0000)
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#define SCSMR_CHR_MASK (1 << 6)
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#define SCSMR_CHR_8 (0x0000)
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#define SCSMR_PE_MASK (1 << 5)
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#define SCSMR_PE_DIS (0x0000)
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#define SCSMR_STOP_MASK (1 << 3)
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#define SCSMR_STOP_1 (0x0000)
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#define SCSMR_CKS_MASK (3 << 0)
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#define SCSMR_CKS_DIV1 (0x0000)
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#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
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SCSMR_CHR_8 + \
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SCSMR_PE_DIS + \
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SCSMR_STOP_1 + \
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SCSMR_CKS_DIV1)
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#define SCBRR_115200BPS (17)
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#define SCBRR_115200BPSON (16)
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#define SCBRR_115200BPS_E3_SSCG (15)
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#define SCBRR_230400BPS (8)
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#define SCBRR_115200BPS (17)
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#define SCBRR_115200BPSON (16)
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#define SCBRR_115200BPS_E3_SSCG (15)
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#define SCBRR_230400BPS (8)
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#define SCSCR_TE_MASK (1 << 5)
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#define SCSCR_TE_DIS (0x0000)
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#define SCSCR_TE_EN (0x0020)
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#define SCSCR_RE_MASK (1 << 4)
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#define SCSCR_RE_DIS (0x0000)
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#define SCSCR_RE_EN (0x0010)
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#define SCSCR_CKE_MASK (3 << 0)
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#define SCSCR_CKE_INT (0x0000)
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#define SCSCR_CKE_BRG (0x0002)
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#define SCSCR_TE_MASK (1 << 5)
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#define SCSCR_TE_DIS (0x0000)
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#define SCSCR_TE_EN (0x0020)
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#define SCSCR_RE_MASK (1 << 4)
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#define SCSCR_RE_DIS (0x0000)
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#define SCSCR_RE_EN (0x0010)
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#define SCSCR_CKE_MASK (3 << 0)
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#define SCSCR_CKE_INT (0x0000)
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#define SCSCR_CKE_BRG (0x0002)
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#if SCIF_CLK == SCIF_EXTARNAL_CLK
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#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
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#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
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#else
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#define SCFSR_TEND_MASK (1 << 6)
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#define SCFSR_TEND_TRANS_END (0x0040)
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#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
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#define SCFSR_TEND_MASK (1 << 6)
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#define SCFSR_TEND_TRANS_END (0x0040)
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#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
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#endif
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#define SCFSR_INIT_DATA (0x0000)
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#define SCFCR_TTRG_MASK (3 << 4)
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#define SCFCR_TTRG_8 (0x0000)
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#define SCFCR_TTRG_0 (0x0030)
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#define SCFCR_TFRST_MASK (1 << 2)
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#define SCFCR_TFRST_DIS (0x0000)
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#define SCFCR_TFRST_EN (0x0004)
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#define SCFCR_RFRS_MASK (1 << 1)
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#define SCFCR_RFRS_DIS (0x0000)
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#define SCFCR_RFRS_EN (0x0002)
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#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
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#define SCFDR_T_MASK (0x1f << 8)
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#define DL_INIT_DATA (8)
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#define CKS_CKS_DIV_MASK (1 << 15)
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#define CKS_CKS_DIV_CLK (0x0000)
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#define CKS_XIN_MASK (1 << 14)
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#define CKS_XIN_SCIF_CLK (0x0000)
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#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
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#define SCFSR_INIT_DATA (0x0000)
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#define SCFCR_TTRG_MASK (3 << 4)
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#define SCFCR_TTRG_8 (0x0000)
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#define SCFCR_TTRG_0 (0x0030)
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#define SCFCR_TFRST_MASK (1 << 2)
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#define SCFCR_TFRST_DIS (0x0000)
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#define SCFCR_TFRST_EN (0x0004)
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#define SCFCR_RFRS_MASK (1 << 1)
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#define SCFCR_RFRS_DIS (0x0000)
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#define SCFCR_RFRS_EN (0x0002)
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#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
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#define SCFDR_T_MASK (0x1f << 8)
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#define DL_INIT_DATA (8)
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#define CKS_CKS_DIV_MASK (1 << 15)
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#define CKS_CKS_DIV_CLK (0x0000)
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#define CKS_XIN_MASK (1 << 14)
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#define CKS_XIN_SCIF_CLK (0x0000)
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#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
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.globl console_rcar_register
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.globl console_rcar_init
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.globl console_rcar_putc
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.globl console_rcar_flush
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/* -----------------------------------------------
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/*
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* -----------------------------------------------
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* int console_rcar_register(
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* uintptr_t base, uint32_t clk, uint32_t baud,
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* console_t *console)
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@ -154,7 +155,7 @@ register_fail:
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ret x7
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endfunc console_rcar_register
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/* -----------------------------------------------
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/*
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* int console_rcar_init(unsigned long base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the console without a
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@ -166,7 +167,6 @@ endfunc console_rcar_register
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* w2 - Baud rate
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* Out: return 1 on success
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* Clobber list : x1, x2
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* -----------------------------------------------
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*/
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func console_rcar_init
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ldr x0, =CPG_BASE
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@ -188,8 +188,10 @@ func console_rcar_init
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ldrh w1, [x0, #SCIF_SCFCR]
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orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN)
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strh w1, [x0, #SCIF_SCFCR]
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/* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
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in SCLSR, then clear them to 0 */
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/*
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* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
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* in SCLSR, then clear them to 0
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*/
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mov w1, #SCFSR_INIT_DATA
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strh w1, [x0, #SCIF_SCFSR]
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mov w1, #0
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@ -265,7 +267,7 @@ func console_rcar_init
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ret
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endfunc console_rcar_init
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/* --------------------------------------------------------
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/*
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* int console_rcar_putc(int c, unsigned int base_addr)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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@ -273,7 +275,6 @@ endfunc console_rcar_init
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* x1 - pointer to console_t structure
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* Out : return -1 on error else return character.
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* Clobber list : x2
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* --------------------------------------------------------
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*/
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func console_rcar_putc
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ldr x1, =SCIF_BASE
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@ -304,12 +305,11 @@ func console_rcar_putc
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ret
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endfunc console_rcar_putc
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/* ---------------------------------------------
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/*
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* void console_rcar_flush(void)
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* Function to force a write of all buffered
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* data that hasn't been output. It returns void
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_rcar_flush
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ldr x0, =SCIF_BASE
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