plat: ti: k3: board: lite: Increase SRAM size to account for additional table
We actually have additional table entries than what we accounted for in our size. MAX_XLAT_TABLES is 8, but really we could be using upto 10 depending on the platform. So, we need an extra 8K space in. This gets exposed with DEBUG=1 and assert checks trigger, which for some reason completely escaped testing previously. ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97 BACKTRACE: START: assert Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I5c5d04440ef1fccfaf2317066f3abbc0ec645903
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@ -22,7 +22,7 @@
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* a single cluster of 4 processor.
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*/
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#define SEC_SRAM_BASE 0x70000000 /* Base of SRAM */
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#define SEC_SRAM_SIZE 0x0001a000 /* 104k */
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#define SEC_SRAM_SIZE 0x0001c000 /* 112k */
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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