diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst index cefc21f12..7ae98b1d2 100644 --- a/docs/plat/stm32mp1.rst +++ b/docs/plat/stm32mp1.rst @@ -2,15 +2,34 @@ STMicroelectronics STM32MP1 =========================== STM32MP1 is a microprocessor designed by STMicroelectronics -based on a dual Arm Cortex-A7. +based on Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A. -The STM32MP1 chip also embeds a Cortex-M4. More information can be found on `STM32MP1 Series`_ page. STM32MP1 Versions ----------------- -The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: + +There are 2 variants for STM32MP1: STM32MP13 and STM32MP15 + +STM32MP13 Versions +~~~~~~~~~~~~~~~~~~ +The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible: + +- STM32MP131: Single Cortex-A7 core +- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1 +- STM32MP135: STM32MP133 + DCMIPP, LTDC + +Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: + +- A Cortex-A7 @ 650 MHz +- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz +- D Cortex-A7 @ 900 MHz +- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz + +STM32MP15 Versions +~~~~~~~~~~~~~~~~~~ +The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD @@ -131,6 +150,10 @@ Other configuration flags: | Default: 115200 - | ``STM32_TF_VERSION``: to manage BL2 monotonic counter. | Default: 0 +- | ``STM32MP13``: to select STM32MP13 variant configuration. + | Default: 0 +- | ``STM32MP15``: to select STM32MP15 variant configuration. + | Default: 1 Boot with FIP diff --git a/drivers/st/clk/clk-stm32-core.c b/drivers/st/clk/clk-stm32-core.c new file mode 100644 index 000000000..355c9dab2 --- /dev/null +++ b/drivers/st/clk/clk-stm32-core.c @@ -0,0 +1,1097 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#include +#include + +#include "clk-stm32-core.h" +#include +#include +#include +#include +#include +#include +#include + +static struct spinlock reg_lock; +static struct spinlock refcount_lock; + +static struct stm32_clk_priv *stm32_clock_data; + +const struct stm32_clk_ops clk_mux_ops; + +struct stm32_clk_priv *clk_stm32_get_priv(void) +{ + return stm32_clock_data; +} + +static void stm32mp1_clk_lock(struct spinlock *lock) +{ + if (stm32mp_lock_available()) { + /* Assume interrupts are masked */ + spin_lock(lock); + } +} + +static void stm32mp1_clk_unlock(struct spinlock *lock) +{ + if (stm32mp_lock_available()) { + spin_unlock(lock); + } +} + +void stm32mp1_clk_rcc_regs_lock(void) +{ + stm32mp1_clk_lock(®_lock); +} + +void stm32mp1_clk_rcc_regs_unlock(void) +{ + stm32mp1_clk_unlock(®_lock); +} + +#define TIMEOUT_US_1S U(1000000) +#define OSCRDY_TIMEOUT TIMEOUT_US_1S + +struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_osc_cfg *osc_cfg = clk->clock_cfg; + int osc_id = osc_cfg->osc_id; + + return &priv->osci_data[osc_id]; +} + +void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, bool digbyp, bool bypass) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + struct stm32_clk_bypass *bypass_data = osc_data->bypass; + uintptr_t address; + + if (bypass_data == NULL) { + return; + } + + address = priv->base + bypass_data->offset; + + if (digbyp) { + mmio_setbits_32(address, BIT(bypass_data->bit_digbyp)); + } + + if (bypass || digbyp) { + mmio_setbits_32(address, BIT(bypass_data->bit_byp)); + } +} + +void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, bool css) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + struct stm32_clk_css *css_data = osc_data->css; + uintptr_t address; + + if (css_data == NULL) { + return; + } + + address = priv->base + css_data->offset; + + if (css) { + mmio_setbits_32(address, BIT(css_data->bit_css)); + } +} + +void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, uint8_t lsedrv) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + struct stm32_clk_drive *drive_data = osc_data->drive; + uintptr_t address; + uint32_t mask; + uint32_t value; + + if (drive_data == NULL) { + return; + } + + address = priv->base + drive_data->offset; + + mask = (BIT(drive_data->drv_width) - 1U) << drive_data->drv_shift; + + /* + * Warning: not recommended to switch directly from "high drive" + * to "medium low drive", and vice-versa. + */ + value = (mmio_read_32(address) & mask) >> drive_data->drv_shift; + + while (value != lsedrv) { + if (value > lsedrv) { + value--; + } else { + value++; + } + + mmio_clrsetbits_32(address, mask, value << drive_data->drv_shift); + } +} + +int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + return _clk_stm32_gate_wait_ready(priv, osc_data->gate_id, ready_on); +} + +int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id) +{ + return clk_oscillator_wait_ready(priv, id, true); +} + +int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id) +{ + return clk_oscillator_wait_ready(priv, id, false); +} + +static int clk_gate_enable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_gate_cfg *cfg = clk->clock_cfg; + + mmio_setbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); + + return 0; +} + +static void clk_gate_disable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_gate_cfg *cfg = clk->clock_cfg; + + mmio_clrbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); +} + +static bool clk_gate_is_enabled(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_gate_cfg *cfg = clk->clock_cfg; + + return ((mmio_read_32(priv->base + cfg->offset) & BIT(cfg->bit_idx)) != 0U); +} + +const struct stm32_clk_ops clk_gate_ops = { + .enable = clk_gate_enable, + .disable = clk_gate_disable, + .is_enabled = clk_gate_is_enabled, +}; + +void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id) +{ + const struct gate_cfg *gate = &priv->gates[gate_id]; + uintptr_t addr = priv->base + gate->offset; + + if (gate->set_clr != 0U) { + mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT(gate->bit_idx)); + } else { + mmio_clrbits_32(addr, BIT(gate->bit_idx)); + } +} + +int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id) +{ + const struct gate_cfg *gate = &priv->gates[gate_id]; + uintptr_t addr = priv->base + gate->offset; + + if (gate->set_clr != 0U) { + mmio_write_32(addr, BIT(gate->bit_idx)); + + } else { + mmio_setbits_32(addr, BIT(gate->bit_idx)); + } + + return 0; +} + +const char *_clk_stm32_get_name(struct stm32_clk_priv *priv, int id) +{ + return priv->clks[id].name; +} + +const char *clk_stm32_get_name(struct stm32_clk_priv *priv, + unsigned long binding_id) +{ + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return NULL; + } + + return _clk_stm32_get_name(priv, id); +} + +const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id) +{ + if ((unsigned int)id < priv->num) { + return &priv->clks[id]; + } + + return NULL; +} + +#define clk_div_mask(_width) GENMASK(((_width) - 1U), 0U) + +static unsigned int _get_table_div(const struct clk_div_table *table, + unsigned int val) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) { + if (clkt->val == val) { + return clkt->div; + } + } + + return 0; +} + +static unsigned int _get_div(const struct clk_div_table *table, + unsigned int val, unsigned long flags, + uint8_t width) +{ + if ((flags & CLK_DIVIDER_ONE_BASED) != 0UL) { + return val; + } + + if ((flags & CLK_DIVIDER_POWER_OF_TWO) != 0UL) { + return BIT(val); + } + + if ((flags & CLK_DIVIDER_MAX_AT_ZERO) != 0UL) { + return (val != 0U) ? val : BIT(width); + } + + if (table != NULL) { + return _get_table_div(table, val); + } + + return val + 1U; +} + +#define TIMEOUT_US_200MS U(200000) +#define CLKSRC_TIMEOUT TIMEOUT_US_200MS + +int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel) +{ + const struct parent_cfg *parents = &priv->parents[pid & MUX_PARENT_MASK]; + const struct mux_cfg *mux = parents->mux; + uintptr_t address = priv->base + mux->offset; + uint32_t mask; + uint64_t timeout; + + mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); + + mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask); + + if (mux->bitrdy == MUX_NO_BIT_RDY) { + return 0; + } + + timeout = timeout_init_us(CLKSRC_TIMEOUT); + + mask = BIT(mux->bitrdy); + + while ((mmio_read_32(address) & mask) == 0U) { + if (timeout_elapsed(timeout)) { + return -ETIMEDOUT; + } + } + + return 0; +} + +int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int clk, int clkp) +{ + const struct parent_cfg *parents; + uint16_t pid; + uint8_t sel; + int old_parent; + + pid = priv->clks[clk].parent; + + if ((pid == CLK_IS_ROOT) || (pid < MUX_MAX_PARENTS)) { + return -EINVAL; + } + + old_parent = _clk_stm32_get_parent(priv, clk); + if (old_parent == clkp) { + return 0; + } + + parents = &priv->parents[pid & MUX_PARENT_MASK]; + + for (sel = 0; sel < parents->num_parents; sel++) { + if (parents->id_parents[sel] == (uint16_t)clkp) { + bool clk_was_enabled = _clk_stm32_is_enabled(priv, clk); + int err = 0; + + /* Enable the parents (for glitch free mux) */ + _clk_stm32_enable(priv, clkp); + _clk_stm32_enable(priv, old_parent); + + err = clk_mux_set_parent(priv, pid, sel); + + _clk_stm32_disable(priv, old_parent); + + if (clk_was_enabled) { + _clk_stm32_disable(priv, old_parent); + } else { + _clk_stm32_disable(priv, clkp); + } + + return err; + } + } + + return -EINVAL; +} + +int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id) +{ + const struct parent_cfg *parent; + const struct mux_cfg *mux; + uint32_t mask; + + if (mux_id >= priv->nb_parents) { + panic(); + } + + parent = &priv->parents[mux_id]; + mux = parent->mux; + + mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); + + return (mmio_read_32(priv->base + mux->offset) & mask) >> mux->shift; +} + +int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel) +{ + uint16_t pid; + + pid = priv->clks[clk].parent; + + if ((pid == CLK_IS_ROOT) || (pid < MUX_MAX_PARENTS)) { + return -EINVAL; + } + + return clk_mux_set_parent(priv, pid, sel); +} + +int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int clk_id) +{ + const struct clk_stm32 *clk = _clk_get(priv, clk_id); + const struct parent_cfg *parent; + uint16_t mux_id; + int sel; + + mux_id = priv->clks[clk_id].parent; + if (mux_id == CLK_IS_ROOT) { + return CLK_IS_ROOT; + } + + if (mux_id < MUX_MAX_PARENTS) { + return mux_id & MUX_PARENT_MASK; + } + + mux_id &= MUX_PARENT_MASK; + parent = &priv->parents[mux_id]; + + if (clk->ops->get_parent != NULL) { + sel = clk->ops->get_parent(priv, clk_id); + } else { + sel = clk_mux_get_parent(priv, mux_id); + } + + if (sel < parent->num_parents) { + return parent->id_parents[sel]; + } + + return -EINVAL; +} + +int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id) +{ + uint16_t mux_id; + + mux_id = priv->clks[clk_id].parent; + if (mux_id == CLK_IS_ROOT) { + return CLK_IS_ROOT; + } + + if (mux_id < MUX_MAX_PARENTS) { + return mux_id & MUX_PARENT_MASK; + } + + mux_id &= MUX_PARENT_MASK; + + return clk_mux_get_parent(priv, mux_id); +} + +int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx) +{ + const struct parent_cfg *parent; + uint16_t mux_id; + + mux_id = priv->clks[clk_id].parent; + if (mux_id == CLK_IS_ROOT) { + return CLK_IS_ROOT; + } + + if (mux_id < MUX_MAX_PARENTS) { + return mux_id & MUX_PARENT_MASK; + } + + mux_id &= MUX_PARENT_MASK; + parent = &priv->parents[mux_id]; + + if (idx < parent->num_parents) { + return parent->id_parents[idx]; + } + + return -EINVAL; +} + +int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id) +{ + unsigned int i; + + for (i = 0U; i < priv->num; i++) { + if (binding_id == priv->clks[i].binding) { + return (int)i; + } + } + + return -EINVAL; +} + +unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + int parent; + unsigned long rate = 0UL; + + if ((unsigned int)id >= priv->num) { + return rate; + } + + parent = _clk_stm32_get_parent(priv, id); + + if (clk->ops->recalc_rate != NULL) { + unsigned long prate = 0UL; + + if (parent != CLK_IS_ROOT) { + prate = _clk_stm32_get_rate(priv, parent); + } + + rate = clk->ops->recalc_rate(priv, id, prate); + + return rate; + } + + switch (parent) { + case CLK_IS_ROOT: + panic(); + + default: + rate = _clk_stm32_get_rate(priv, parent); + break; + } + return rate; + +} + +unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id) +{ + int parent_id = _clk_stm32_get_parent(priv, id); + + return _clk_stm32_get_rate(priv, parent_id); +} + +static uint8_t _stm32_clk_get_flags(struct stm32_clk_priv *priv, int id) +{ + return priv->clks[id].flags; +} + +bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag) +{ + if (_stm32_clk_get_flags(priv, id) & flag) { + return true; + } + + return false; +} + +int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + + if (clk->ops->enable != NULL) { + clk->ops->enable(priv, id); + } + + return 0; +} + +static int _clk_stm32_enable_core(struct stm32_clk_priv *priv, int id) +{ + int parent; + int ret = 0; + + if (priv->gate_refcounts[id] == 0U) { + parent = _clk_stm32_get_parent(priv, id); + if (parent != CLK_IS_ROOT) { + ret = _clk_stm32_enable_core(priv, parent); + if (ret) { + return ret; + } + } + clk_stm32_enable_call_ops(priv, id); + } + + priv->gate_refcounts[id]++; + + if (priv->gate_refcounts[id] == UINT_MAX) { + ERROR("%s: %d max enable count !", __func__, id); + panic(); + } + + return 0; +} + +int _clk_stm32_enable(struct stm32_clk_priv *priv, int id) +{ + int ret; + + stm32mp1_clk_lock(&refcount_lock); + ret = _clk_stm32_enable_core(priv, id); + stm32mp1_clk_unlock(&refcount_lock); + + return ret; +} + +void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + + if (clk->ops->disable != NULL) { + clk->ops->disable(priv, id); + } +} + +static void _clk_stm32_disable_core(struct stm32_clk_priv *priv, int id) +{ + int parent; + + if ((priv->gate_refcounts[id] == 1U) && _stm32_clk_is_flags(priv, id, CLK_IS_CRITICAL)) { + return; + } + + if (priv->gate_refcounts[id] == 0U) { + /* case of clock ignore unused */ + if (_clk_stm32_is_enabled(priv, id)) { + clk_stm32_disable_call_ops(priv, id); + return; + } + VERBOSE("%s: %d already disabled !\n\n", __func__, id); + return; + } + + if (--priv->gate_refcounts[id] > 0U) { + return; + } + + clk_stm32_disable_call_ops(priv, id); + + parent = _clk_stm32_get_parent(priv, id); + if (parent != CLK_IS_ROOT) { + _clk_stm32_disable_core(priv, parent); + } +} + +void _clk_stm32_disable(struct stm32_clk_priv *priv, int id) +{ + stm32mp1_clk_lock(&refcount_lock); + + _clk_stm32_disable_core(priv, id); + + stm32mp1_clk_unlock(&refcount_lock); +} + +bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + + if (clk->ops->is_enabled != NULL) { + return clk->ops->is_enabled(priv, id); + } + + return priv->gate_refcounts[id]; +} + +static int clk_stm32_enable(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return id; + } + + return _clk_stm32_enable(priv, id); +} + +static void clk_stm32_disable(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id != -EINVAL) { + _clk_stm32_disable(priv, id); + } +} + +static bool clk_stm32_is_enabled(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return false; + } + + return _clk_stm32_is_enabled(priv, id); +} + +static unsigned long clk_stm32_get_rate(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return 0UL; + } + + return _clk_stm32_get_rate(priv, id); +} + +static int clk_stm32_get_parent(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return id; + } + + return _clk_stm32_get_parent(priv, id); +} + +static const struct clk_ops stm32mp_clk_ops = { + .enable = clk_stm32_enable, + .disable = clk_stm32_disable, + .is_enabled = clk_stm32_is_enabled, + .get_rate = clk_stm32_get_rate, + .get_parent = clk_stm32_get_parent, +}; + +void clk_stm32_enable_critical_clocks(void) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + unsigned int i; + + for (i = 0U; i < priv->num; i++) { + if (_stm32_clk_is_flags(priv, i, CLK_IS_CRITICAL)) { + _clk_stm32_enable(priv, i); + } + } +} + +static void stm32_clk_register(void) +{ + clk_register(&stm32mp_clk_ops); +} + +uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id) +{ + const struct div_cfg *divider = &priv->div[div_id]; + uint32_t val = 0; + + val = mmio_read_32(priv->base + divider->offset) >> divider->shift; + val &= clk_div_mask(divider->width); + + return val; +} + +unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv, + int div_id, + unsigned long prate) +{ + const struct div_cfg *divider = &priv->div[div_id]; + uint32_t val = clk_stm32_div_get_value(priv, div_id); + unsigned int div = 0U; + + div = _get_div(divider->table, val, divider->flags, divider->width); + if (div == 0U) { + return prate; + } + + return div_round_up((uint64_t)prate, div); +} + +unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int id, + unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_div_cfg *div_cfg = clk->clock_cfg; + + return _clk_stm32_divider_recalc(priv, div_cfg->id, prate); +} + +const struct stm32_clk_ops clk_stm32_divider_ops = { + .recalc_rate = clk_stm32_divider_recalc, +}; + +int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value) +{ + const struct div_cfg *divider; + uintptr_t address; + uint64_t timeout; + uint32_t mask; + + if (div_id >= priv->nb_div) { + panic(); + } + + divider = &priv->div[div_id]; + address = priv->base + divider->offset; + + mask = MASK_WIDTH_SHIFT(divider->width, divider->shift); + mmio_clrsetbits_32(address, mask, (value << divider->shift) & mask); + + if (divider->bitrdy == DIV_NO_BIT_RDY) { + return 0; + } + + timeout = timeout_init_us(CLKSRC_TIMEOUT); + mask = BIT(divider->bitrdy); + + while ((mmio_read_32(address) & mask) == 0U) { + if (timeout_elapsed(timeout)) { + return -ETIMEDOUT; + } + } + + return 0; +} + +int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, + bool ready_on) +{ + const struct gate_cfg *gate = &priv->gates[gate_id]; + uintptr_t address = priv->base + gate->offset; + uint32_t mask_rdy = BIT(gate->bit_idx); + uint64_t timeout; + uint32_t mask_test; + + if (ready_on) { + mask_test = BIT(gate->bit_idx); + } else { + mask_test = 0U; + } + + timeout = timeout_init_us(OSCRDY_TIMEOUT); + + while ((mmio_read_32(address) & mask_rdy) != mask_test) { + if (timeout_elapsed(timeout)) { + break; + } + } + + if ((mmio_read_32(address) & mask_rdy) != mask_test) + return -ETIMEDOUT; + + return 0; +} + +int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_gate_cfg *cfg = clk->clock_cfg; + const struct gate_cfg *gate = &priv->gates[cfg->id]; + uintptr_t addr = priv->base + gate->offset; + + if (gate->set_clr != 0U) { + mmio_write_32(addr, BIT(gate->bit_idx)); + + } else { + mmio_setbits_32(addr, BIT(gate->bit_idx)); + } + + return 0; +} + +void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_gate_cfg *cfg = clk->clock_cfg; + const struct gate_cfg *gate = &priv->gates[cfg->id]; + uintptr_t addr = priv->base + gate->offset; + + if (gate->set_clr != 0U) { + mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT(gate->bit_idx)); + } else { + mmio_clrbits_32(addr, BIT(gate->bit_idx)); + } +} + +bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id) +{ + const struct gate_cfg *gate; + uint32_t addr; + + gate = &priv->gates[gate_id]; + addr = priv->base + gate->offset; + + return ((mmio_read_32(addr) & BIT(gate->bit_idx)) != 0U); +} + +bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_gate_cfg *cfg = clk->clock_cfg; + + return _clk_stm32_gate_is_enabled(priv, cfg->id); +} + +const struct stm32_clk_ops clk_stm32_gate_ops = { + .enable = clk_stm32_gate_enable, + .disable = clk_stm32_gate_disable, + .is_enabled = clk_stm32_gate_is_enabled, +}; + +const struct stm32_clk_ops clk_fixed_factor_ops = { + .recalc_rate = fixed_factor_recalc_rate, +}; + +unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, + int id, unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + const struct fixed_factor_cfg *cfg = clk->clock_cfg; + unsigned long long rate; + + rate = (unsigned long long)prate * cfg->mult; + + if (cfg->div == 0U) { + ERROR("division by zero\n"); + panic(); + } + + return (unsigned long)(rate / cfg->div); +}; + +#define APB_DIV_MASK GENMASK(2, 0) +#define TIM_PRE_MASK BIT(0) + +static unsigned long timer_recalc_rate(struct stm32_clk_priv *priv, + int id, unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + const struct clk_timer_cfg *cfg = clk->clock_cfg; + uint32_t prescaler, timpre; + uintptr_t rcc_base = priv->base; + + prescaler = mmio_read_32(rcc_base + cfg->apbdiv) & + APB_DIV_MASK; + + timpre = mmio_read_32(rcc_base + cfg->timpre) & + TIM_PRE_MASK; + + if (prescaler == 0U) { + return prate; + } + + return prate * (timpre + 1U) * 2U; +}; + +const struct stm32_clk_ops clk_timer_ops = { + .recalc_rate = timer_recalc_rate, +}; + +static unsigned long clk_fixed_rate_recalc(struct stm32_clk_priv *priv, int id, + unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_fixed_rate_cfg *cfg = clk->clock_cfg; + + return cfg->rate; +} + +const struct stm32_clk_ops clk_stm32_fixed_rate_ops = { + .recalc_rate = clk_fixed_rate_recalc, +}; + +static unsigned long clk_stm32_osc_recalc_rate(struct stm32_clk_priv *priv, + int id, unsigned long prate) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + return osc_data->frequency; +}; + +bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + return _clk_stm32_gate_is_enabled(priv, osc_data->gate_id); + +} + +int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + _clk_stm32_gate_enable(priv, osc_data->gate_id); + + if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, true) != 0U) { + ERROR("%s: %s (%d)\n", __func__, osc_data->name, __LINE__); + panic(); + } + + return 0; +} + +void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + _clk_stm32_gate_disable(priv, osc_data->gate_id); + + if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, false) != 0U) { + ERROR("%s: %s (%d)\n", __func__, osc_data->name, __LINE__); + panic(); + } +} + +static unsigned long clk_stm32_get_dt_oscillator_frequency(const char *name) +{ + void *fdt = NULL; + int node = 0; + int subnode = 0; + + if (fdt_get_address(&fdt) == 0) { + panic(); + } + + node = fdt_path_offset(fdt, "/clocks"); + if (node < 0) { + return 0UL; + } + + fdt_for_each_subnode(subnode, fdt, node) { + const char *cchar = NULL; + const fdt32_t *cuint = NULL; + int ret = 0; + + cchar = fdt_get_name(fdt, subnode, &ret); + if (cchar == NULL) { + continue; + } + + if (strncmp(cchar, name, (size_t)ret) || + fdt_get_status(subnode) == DT_DISABLED) { + continue; + } + + cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); + if (cuint == NULL) { + return 0UL; + } + + return fdt32_to_cpu(*cuint); + } + + return 0UL; +} + +void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + const char *name = osc_data->name; + + osc_data->frequency = clk_stm32_get_dt_oscillator_frequency(name); +} + +const struct stm32_clk_ops clk_stm32_osc_ops = { + .recalc_rate = clk_stm32_osc_recalc_rate, + .is_enabled = clk_stm32_osc_gate_is_enabled, + .enable = clk_stm32_osc_gate_enable, + .disable = clk_stm32_osc_gate_disable, + .init = clk_stm32_osc_init, +}; + +const struct stm32_clk_ops clk_stm32_osc_nogate_ops = { + .recalc_rate = clk_stm32_osc_recalc_rate, + .init = clk_stm32_osc_init, +}; + +int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, uint32_t *tab, uint32_t *nb) +{ + const fdt32_t *cell; + int len = 0; + uint32_t i; + + cell = fdt_getprop(fdt, node, name, &len); + if (cell != NULL) { + for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { + uint32_t val = fdt32_to_cpu(cell[i]); + + tab[i] = val; + } + } + + *nb = (uint32_t)len / sizeof(uint32_t); + + return 0; +} + +int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base) +{ + unsigned int i; + + stm32_clock_data = priv; + + priv->base = base; + + for (i = 0U; i < priv->num; i++) { + const struct clk_stm32 *clk = _clk_get(priv, i); + + assert(clk->ops != NULL); + + if (clk->ops->init != NULL) { + clk->ops->init(priv, i); + } + } + + stm32_clk_register(); + + return 0; +} diff --git a/drivers/st/clk/clk-stm32-core.h b/drivers/st/clk/clk-stm32-core.h new file mode 100644 index 000000000..809d05f70 --- /dev/null +++ b/drivers/st/clk/clk-stm32-core.h @@ -0,0 +1,405 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef CLK_STM32_CORE_H +#define CLK_STM32_CORE_H + +struct mux_cfg { + uint16_t offset; + uint8_t shift; + uint8_t width; + uint8_t bitrdy; +}; + +struct gate_cfg { + uint16_t offset; + uint8_t bit_idx; + uint8_t set_clr; +}; + +struct clk_div_table { + unsigned int val; + unsigned int div; +}; + +struct div_cfg { + uint16_t offset; + uint8_t shift; + uint8_t width; + uint8_t flags; + uint8_t bitrdy; + const struct clk_div_table *table; +}; + +struct parent_cfg { + uint8_t num_parents; + const uint16_t *id_parents; + struct mux_cfg *mux; +}; + +struct stm32_clk_priv; + +struct stm32_clk_ops { + unsigned long (*recalc_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate); + int (*get_parent)(struct stm32_clk_priv *priv, int id); + int (*set_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate, + unsigned long prate); + int (*enable)(struct stm32_clk_priv *priv, int id); + void (*disable)(struct stm32_clk_priv *priv, int id); + bool (*is_enabled)(struct stm32_clk_priv *priv, int id); + void (*init)(struct stm32_clk_priv *priv, int id); +}; + +struct clk_stm32 { + const char *name; + uint16_t binding; + uint16_t parent; + uint8_t flags; + void *clock_cfg; + const struct stm32_clk_ops *ops; +}; + +struct stm32_clk_priv { + uintptr_t base; + const uint32_t num; + const struct clk_stm32 *clks; + const struct parent_cfg *parents; + const uint32_t nb_parents; + const struct gate_cfg *gates; + const uint32_t nb_gates; + const struct div_cfg *div; + const uint32_t nb_div; + struct clk_oscillator_data *osci_data; + const uint32_t nb_osci_data; + uint32_t *gate_refcounts; + void *pdata; +}; + +struct stm32_clk_bypass { + uint16_t offset; + uint8_t bit_byp; + uint8_t bit_digbyp; +}; + +struct stm32_clk_css { + uint16_t offset; + uint8_t bit_css; +}; + +struct stm32_clk_drive { + uint16_t offset; + uint8_t drv_shift; + uint8_t drv_width; + uint8_t drv_default; +}; + +struct clk_oscillator_data { + const char *name; + uint16_t id_clk; + unsigned long frequency; + uint16_t gate_id; + uint16_t gate_rdy_id; + struct stm32_clk_bypass *bypass; + struct stm32_clk_css *css; + struct stm32_clk_drive *drive; +}; + +struct clk_fixed_rate { + const char *name; + unsigned long fixed_rate; +}; + +struct clk_gate_cfg { + uint32_t offset; + uint8_t bit_idx; +}; + +/* CLOCK FLAGS */ +#define CLK_IS_CRITICAL BIT(0) +#define CLK_IGNORE_UNUSED BIT(1) +#define CLK_SET_RATE_PARENT BIT(2) + +#define CLK_DIVIDER_ONE_BASED BIT(0) +#define CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) +#define CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define CLK_DIVIDER_READ_ONLY BIT(5) +#define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_DIVIDER_BIG_ENDIAN BIT(7) + +#define MUX_MAX_PARENTS U(0x8000) +#define MUX_PARENT_MASK GENMASK(14, 0) +#define MUX_FLAG U(0x8000) +#define MUX(mux) ((mux) | MUX_FLAG) + +#define NO_GATE 0 +#define _NO_ID UINT16_MAX +#define CLK_IS_ROOT UINT16_MAX +#define MUX_NO_BIT_RDY UINT8_MAX +#define DIV_NO_BIT_RDY UINT8_MAX + +#define MASK_WIDTH_SHIFT(_width, _shift) \ + GENMASK(((_width) + (_shift) - 1U), (_shift)) + +int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base); +void clk_stm32_enable_critical_clocks(void); + +struct stm32_clk_priv *clk_stm32_get_priv(void); + +int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id); +const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id); + +void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, bool digbyp, bool bypass); +void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, uint8_t lsedrv); +void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, bool css); + +int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, bool ready_on); + +int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on); +int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id); +int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id); + +const char *_clk_stm32_get_name(struct stm32_clk_priv *priv, int id); +const char *clk_stm32_get_name(struct stm32_clk_priv *priv, unsigned long binding_id); +int clk_stm32_get_counter(unsigned long binding_id); + +void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id); +int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id); + +int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int id, int src_id); +int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel); + +int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int id); +int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx); +int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id); + +unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id); +unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id); + +bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag); + +int _clk_stm32_enable(struct stm32_clk_priv *priv, int id); +void _clk_stm32_disable(struct stm32_clk_priv *priv, int id); + +int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id); +void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id); + +bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id); + +int _clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int div_id, + unsigned long rate, unsigned long parent_rate); + +int clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate, + unsigned long prate); + +unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv, + int div_id, + unsigned long prate); + +unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int idx, + unsigned long prate); + +int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int idx); +void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int idx); + +bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id); +bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int idx); + +uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id); +int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value); +int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel); +int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id); + +int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, uint32_t *tab, uint32_t *nb); + +#ifdef CFG_STM32_CLK_DEBUG +void clk_stm32_display_clock_info(void); +#endif + +struct clk_stm32_div_cfg { + int id; +}; + +#define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (_parent),\ + .flags = (_flags),\ + .clock_cfg = &(struct clk_stm32_div_cfg){\ + .id = (_div_id),\ + },\ + .ops = &clk_stm32_divider_ops,\ + } + +struct clk_stm32_gate_cfg { + int id; +}; + +#define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (_parent),\ + .flags = (_flags),\ + .clock_cfg = &(struct clk_stm32_gate_cfg){\ + .id = (_gate_id),\ + },\ + .ops = &clk_stm32_gate_ops,\ + } + +struct fixed_factor_cfg { + unsigned int mult; + unsigned int div; +}; + +unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, + int _idx, unsigned long prate); + +#define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_idx),\ + .parent = (_parent),\ + .clock_cfg = &(struct fixed_factor_cfg){\ + .mult = (_mult),\ + .div = (_div),\ + },\ + .ops = &clk_fixed_factor_ops,\ + } + +#define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (_parent),\ + .flags = (_flags),\ + .clock_cfg = &(struct clk_gate_cfg){\ + .offset = (_offset),\ + .bit_idx = (_bit_idx),\ + },\ + .ops = &clk_gate_ops,\ + } + +#define STM32_MUX(idx, _binding, _mux_id, _flags) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (MUX(_mux_id)),\ + .flags = (_flags),\ + .clock_cfg = NULL,\ + .ops = (&clk_mux_ops),\ + } + +struct clk_timer_cfg { + uint32_t apbdiv; + uint32_t timpre; +}; + +#define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_idx),\ + .parent = (_parent),\ + .flags = (CLK_SET_RATE_PARENT | (_flags)),\ + .clock_cfg = &(struct clk_timer_cfg){\ + .apbdiv = (_apbdiv),\ + .timpre = (_timpre),\ + },\ + .ops = &clk_timer_ops,\ + } + +struct clk_stm32_fixed_rate_cfg { + unsigned long rate; +}; + +#define CLK_FIXED_RATE(idx, _binding, _rate) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (CLK_IS_ROOT),\ + .clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\ + .rate = (_rate),\ + },\ + .ops = &clk_stm32_fixed_rate_ops,\ + } + +#define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\ + .offset = (_offset),\ + .bit_byp = (_bit_byp),\ + .bit_digbyp = (_bit_digbyp),\ +} + +#define CSS(_offset, _bit_css) &(struct stm32_clk_css){\ + .offset = (_offset),\ + .bit_css = (_bit_css),\ +} + +#define DRIVE(_offset, _shift, _width, _default) &(struct stm32_clk_drive){\ + .offset = (_offset),\ + .drv_shift = (_shift),\ + .drv_width = (_width),\ + .drv_default = (_default),\ +} + +#define OSCILLATOR(idx_osc, _id, _name, _gate_id, _gate_rdy_id, _bypass, _css, _drive) \ + [(idx_osc)] = (struct clk_oscillator_data){\ + .name = (_name),\ + .id_clk = (_id),\ + .gate_id = (_gate_id),\ + .gate_rdy_id = (_gate_rdy_id),\ + .bypass = (_bypass),\ + .css = (_css),\ + .drive = (_drive),\ + } + +struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id); + +void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id); +bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id); +int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id); +void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id); + +struct stm32_osc_cfg { + int osc_id; +}; + +#define CLK_OSC(idx, _idx, _parent, _osc_id) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_idx),\ + .parent = (_parent),\ + .flags = CLK_IS_CRITICAL,\ + .clock_cfg = &(struct stm32_osc_cfg){\ + .osc_id = (_osc_id),\ + },\ + .ops = &clk_stm32_osc_ops,\ + } + +#define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_idx),\ + .parent = (_parent),\ + .flags = CLK_IS_CRITICAL,\ + .clock_cfg = &(struct stm32_osc_cfg){\ + .osc_id = (_osc_id),\ + },\ + .ops = &clk_stm32_osc_nogate_ops,\ + } + +extern const struct stm32_clk_ops clk_mux_ops; +extern const struct stm32_clk_ops clk_stm32_divider_ops; +extern const struct stm32_clk_ops clk_stm32_gate_ops; +extern const struct stm32_clk_ops clk_fixed_factor_ops; +extern const struct stm32_clk_ops clk_gate_ops; +extern const struct stm32_clk_ops clk_timer_ops; +extern const struct stm32_clk_ops clk_stm32_fixed_rate_ops; +extern const struct stm32_clk_ops clk_stm32_osc_ops; +extern const struct stm32_clk_ops clk_stm32_osc_nogate_ops; + +#endif /* CLK_STM32_CORE_H */ diff --git a/drivers/st/clk/clk-stm32mp13.c b/drivers/st/clk/clk-stm32mp13.c new file mode 100644 index 000000000..d3607672b --- /dev/null +++ b/drivers/st/clk/clk-stm32mp13.c @@ -0,0 +1,2334 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#include +#include +#include "clk-stm32-core.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct stm32_osci_dt_cfg { + unsigned long freq; + bool bypass; + bool digbyp; + bool css; + uint32_t drive; +}; + +enum pll_mn { + PLL_CFG_M, + PLL_CFG_N, + PLL_DIV_MN_NB +}; + +enum pll_pqr { + PLL_CFG_P, + PLL_CFG_Q, + PLL_CFG_R, + PLL_DIV_PQR_NB +}; + +enum pll_csg { + PLL_CSG_MOD_PER, + PLL_CSG_INC_STEP, + PLL_CSG_SSCG_MODE, + PLL_CSG_NB +}; + +struct stm32_pll_vco { + uint32_t status; + uint32_t src; + uint32_t div_mn[PLL_DIV_MN_NB]; + uint32_t frac; + bool csg_enabled; + uint32_t csg[PLL_CSG_NB]; +}; + +struct stm32_pll_output { + uint32_t output[PLL_DIV_PQR_NB]; +}; + +struct stm32_pll_dt_cfg { + struct stm32_pll_vco vco; + struct stm32_pll_output output; +}; + +struct stm32_clk_platdata { + uint32_t nosci; + struct stm32_osci_dt_cfg *osci; + uint32_t npll; + struct stm32_pll_dt_cfg *pll; + uint32_t nclksrc; + uint32_t *clksrc; + uint32_t nclkdiv; + uint32_t *clkdiv; +}; + +enum stm32_clock { + /* ROOT CLOCKS */ + _CK_OFF, + _CK_HSI, + _CK_HSE, + _CK_CSI, + _CK_LSI, + _CK_LSE, + _I2SCKIN, + _CSI_DIV122, + _HSE_DIV, + _HSE_DIV2, + _CK_PLL1, + _CK_PLL2, + _CK_PLL3, + _CK_PLL4, + _PLL1P, + _PLL1P_DIV, + _PLL2P, + _PLL2Q, + _PLL2R, + _PLL3P, + _PLL3Q, + _PLL3R, + _PLL4P, + _PLL4Q, + _PLL4R, + _PCLK1, + _PCLK2, + _PCLK3, + _PCLK4, + _PCLK5, + _PCLK6, + _CKMPU, + _CKAXI, + _CKMLAHB, + _CKPER, + _CKTIMG1, + _CKTIMG2, + _CKTIMG3, + _USB_PHY_48, + _MCO1_K, + _MCO2_K, + _TRACECK, + /* BUS and KERNEL CLOCKS */ + _DDRC1, + _DDRC1LP, + _DDRPHYC, + _DDRPHYCLP, + _DDRCAPB, + _DDRCAPBLP, + _AXIDCG, + _DDRPHYCAPB, + _DDRPHYCAPBLP, + _SYSCFG, + _DDRPERFM, + _IWDG2APB, + _USBPHY_K, + _USBO_K, + _RTCAPB, + _TZC, + _ETZPC, + _IWDG1APB, + _BSEC, + _STGENC, + _USART1_K, + _USART2_K, + _I2C3_K, + _I2C4_K, + _I2C5_K, + _TIM12, + _TIM15, + _RTCCK, + _GPIOA, + _GPIOB, + _GPIOC, + _GPIOD, + _GPIOE, + _GPIOF, + _GPIOG, + _GPIOH, + _GPIOI, + _PKA, + _SAES_K, + _CRYP1, + _HASH1, + _RNG1_K, + _BKPSRAM, + _SDMMC1_K, + _SDMMC2_K, + _DBGCK, + _USART3_K, + _UART4_K, + _UART5_K, + _UART7_K, + _UART8_K, + _USART6_K, + _MCE, + _FMC_K, + _QSPI_K, +#if defined(IMAGE_BL32) + _LTDC, + _DMA1, + _DMA2, + _MDMA, + _ETH1MAC, + _USBH, + _TIM2, + _TIM3, + _TIM4, + _TIM5, + _TIM6, + _TIM7, + _LPTIM1_K, + _SPI2_K, + _SPI3_K, + _SPDIF_K, + _TIM1, + _TIM8, + _SPI1_K, + _SAI1_K, + _SAI2_K, + _DFSDM, + _FDCAN_K, + _TIM13, + _TIM14, + _TIM16, + _TIM17, + _SPI4_K, + _SPI5_K, + _I2C1_K, + _I2C2_K, + _ADFSDM, + _LPTIM2_K, + _LPTIM3_K, + _LPTIM4_K, + _LPTIM5_K, + _VREF, + _DTS, + _PMBCTRL, + _HDP, + _STGENRO, + _DCMIPP_K, + _DMAMUX1, + _DMAMUX2, + _DMA3, + _ADC1_K, + _ADC2_K, + _TSC, + _AXIMC, + _ETH1CK, + _ETH1TX, + _ETH1RX, + _CRC1, + _ETH2CK, + _ETH2TX, + _ETH2RX, + _ETH2MAC, +#endif + CK_LAST +}; + +/* PARENT CONFIG */ +static const uint16_t RTC_src[] = { + _CK_OFF, _CK_LSE, _CK_LSI, _CK_HSE +}; + +static const uint16_t MCO1_src[] = { + _CK_HSI, _CK_HSE, _CK_CSI, _CK_LSI, _CK_LSE +}; + +static const uint16_t MCO2_src[] = { + _CKMPU, _CKAXI, _CKMLAHB, _PLL4P, _CK_HSE, _CK_HSI +}; + +static const uint16_t PLL12_src[] = { + _CK_HSI, _CK_HSE +}; + +static const uint16_t PLL3_src[] = { + _CK_HSI, _CK_HSE, _CK_CSI +}; + +static const uint16_t PLL4_src[] = { + _CK_HSI, _CK_HSE, _CK_CSI, _I2SCKIN +}; + +static const uint16_t MPU_src[] = { + _CK_HSI, _CK_HSE, _PLL1P, _PLL1P_DIV +}; + +static const uint16_t AXI_src[] = { + _CK_HSI, _CK_HSE, _PLL2P +}; + +static const uint16_t MLAHBS_src[] = { + _CK_HSI, _CK_HSE, _CK_CSI, _PLL3P +}; + +static const uint16_t CKPER_src[] = { + _CK_HSI, _CK_CSI, _CK_HSE, _CK_OFF +}; + +static const uint16_t I2C12_src[] = { + _PCLK1, _PLL4R, _CK_HSI, _CK_CSI +}; + +static const uint16_t I2C3_src[] = { + _PCLK6, _PLL4R, _CK_HSI, _CK_CSI +}; + +static const uint16_t I2C4_src[] = { + _PCLK6, _PLL4R, _CK_HSI, _CK_CSI +}; + +static const uint16_t I2C5_src[] = { + _PCLK6, _PLL4R, _CK_HSI, _CK_CSI +}; + +static const uint16_t SPI1_src[] = { + _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R +}; + +static const uint16_t SPI23_src[] = { + _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R +}; + +static const uint16_t SPI4_src[] = { + _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE, _I2SCKIN +}; + +static const uint16_t SPI5_src[] = { + _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t UART1_src[] = { + _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE +}; + +static const uint16_t UART2_src[] = { + _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE +}; + +static const uint16_t UART35_src[] = { + _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t UART4_src[] = { + _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t UART6_src[] = { + _PCLK2, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t UART78_src[] = { + _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t LPTIM1_src[] = { + _PCLK1, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER +}; + +static const uint16_t LPTIM2_src[] = { + _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI +}; + +static const uint16_t LPTIM3_src[] = { + _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI +}; + +static const uint16_t LPTIM45_src[] = { + _PCLK3, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER +}; + +static const uint16_t SAI1_src[] = { + _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R +}; + +static const uint16_t SAI2_src[] = { + _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _NO_ID, _PLL3R +}; + +static const uint16_t FDCAN_src[] = { + _CK_HSE, _PLL3Q, _PLL4Q, _PLL4R +}; + +static const uint16_t SPDIF_src[] = { + _PLL4P, _PLL3Q, _CK_HSI +}; + +static const uint16_t ADC1_src[] = { + _PLL4R, _CKPER, _PLL3Q +}; + +static const uint16_t ADC2_src[] = { + _PLL4R, _CKPER, _PLL3Q +}; + +static const uint16_t SDMMC1_src[] = { + _CKAXI, _PLL3R, _PLL4P, _CK_HSI +}; + +static const uint16_t SDMMC2_src[] = { + _CKAXI, _PLL3R, _PLL4P, _CK_HSI +}; + +static const uint16_t ETH1_src[] = { + _PLL4P, _PLL3Q +}; + +static const uint16_t ETH2_src[] = { + _PLL4P, _PLL3Q +}; + +static const uint16_t USBPHY_src[] = { + _CK_HSE, _PLL4R, _HSE_DIV2 +}; + +static const uint16_t USBO_src[] = { + _PLL4R, _USB_PHY_48 +}; + +static const uint16_t QSPI_src[] = { + _CKAXI, _PLL3R, _PLL4P, _CKPER +}; + +static const uint16_t FMC_src[] = { + _CKAXI, _PLL3R, _PLL4P, _CKPER +}; + +/* Position 2 of RNG1 mux is reserved */ +static const uint16_t RNG1_src[] = { + _CK_CSI, _PLL4R, _CK_OFF, _CK_LSI +}; + +static const uint16_t STGEN_src[] = { + _CK_HSI, _CK_HSE +}; + +static const uint16_t DCMIPP_src[] = { + _CKAXI, _PLL2Q, _PLL4P, _CKPER +}; + +static const uint16_t SAES_src[] = { + _CKAXI, _CKPER, _PLL4R, _CK_LSI +}; + +#define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\ + .id_parents = src,\ + .num_parents = ARRAY_SIZE(src),\ + .mux = &(struct mux_cfg) {\ + .offset = (_offset),\ + .shift = (_shift),\ + .width = (_witdh),\ + .bitrdy = MUX_NO_BIT_RDY,\ + },\ +} + +#define MUX_RDY_CFG(id, src, _offset, _shift, _witdh)[id] = {\ + .id_parents = src,\ + .num_parents = ARRAY_SIZE(src),\ + .mux = &(struct mux_cfg) {\ + .offset = (_offset),\ + .shift = (_shift),\ + .width = (_witdh),\ + .bitrdy = 31,\ + },\ +} + +static const struct parent_cfg parent_mp13[] = { + MUX_CFG(MUX_ADC1, ADC1_src, RCC_ADC12CKSELR, 0, 2), + MUX_CFG(MUX_ADC2, ADC2_src, RCC_ADC12CKSELR, 2, 2), + MUX_RDY_CFG(MUX_AXI, AXI_src, RCC_ASSCKSELR, 0, 3), + MUX_CFG(MUX_CKPER, CKPER_src, RCC_CPERCKSELR, 0, 2), + MUX_CFG(MUX_DCMIPP, DCMIPP_src, RCC_DCMIPPCKSELR, 0, 2), + MUX_CFG(MUX_ETH1, ETH1_src, RCC_ETH12CKSELR, 0, 2), + MUX_CFG(MUX_ETH2, ETH2_src, RCC_ETH12CKSELR, 8, 2), + MUX_CFG(MUX_FDCAN, FDCAN_src, RCC_FDCANCKSELR, 0, 2), + MUX_CFG(MUX_FMC, FMC_src, RCC_FMCCKSELR, 0, 2), + MUX_CFG(MUX_I2C12, I2C12_src, RCC_I2C12CKSELR, 0, 3), + MUX_CFG(MUX_I2C3, I2C3_src, RCC_I2C345CKSELR, 0, 3), + MUX_CFG(MUX_I2C4, I2C4_src, RCC_I2C345CKSELR, 3, 3), + MUX_CFG(MUX_I2C5, I2C5_src, RCC_I2C345CKSELR, 6, 3), + MUX_CFG(MUX_LPTIM1, LPTIM1_src, RCC_LPTIM1CKSELR, 0, 3), + MUX_CFG(MUX_LPTIM2, LPTIM2_src, RCC_LPTIM23CKSELR, 0, 3), + MUX_CFG(MUX_LPTIM3, LPTIM3_src, RCC_LPTIM23CKSELR, 3, 3), + MUX_CFG(MUX_LPTIM45, LPTIM45_src, RCC_LPTIM45CKSELR, 0, 3), + MUX_CFG(MUX_MCO1, MCO1_src, RCC_MCO1CFGR, 0, 3), + MUX_CFG(MUX_MCO2, MCO2_src, RCC_MCO2CFGR, 0, 3), + MUX_RDY_CFG(MUX_MLAHB, MLAHBS_src, RCC_MSSCKSELR, 0, 2), + MUX_RDY_CFG(MUX_MPU, MPU_src, RCC_MPCKSELR, 0, 2), + MUX_RDY_CFG(MUX_PLL12, PLL12_src, RCC_RCK12SELR, 0, 2), + MUX_RDY_CFG(MUX_PLL3, PLL3_src, RCC_RCK3SELR, 0, 2), + MUX_RDY_CFG(MUX_PLL4, PLL4_src, RCC_RCK4SELR, 0, 2), + MUX_CFG(MUX_QSPI, QSPI_src, RCC_QSPICKSELR, 0, 2), + MUX_CFG(MUX_RNG1, RNG1_src, RCC_RNG1CKSELR, 0, 2), + MUX_CFG(MUX_RTC, RTC_src, RCC_BDCR, 16, 2), + MUX_CFG(MUX_SAES, SAES_src, RCC_SAESCKSELR, 0, 2), + MUX_CFG(MUX_SAI1, SAI1_src, RCC_SAI1CKSELR, 0, 3), + MUX_CFG(MUX_SAI2, SAI2_src, RCC_SAI2CKSELR, 0, 3), + MUX_CFG(MUX_SDMMC1, SDMMC1_src, RCC_SDMMC12CKSELR, 0, 3), + MUX_CFG(MUX_SDMMC2, SDMMC2_src, RCC_SDMMC12CKSELR, 3, 3), + MUX_CFG(MUX_SPDIF, SPDIF_src, RCC_SPDIFCKSELR, 0, 2), + MUX_CFG(MUX_SPI1, SPI1_src, RCC_SPI2S1CKSELR, 0, 3), + MUX_CFG(MUX_SPI23, SPI23_src, RCC_SPI2S23CKSELR, 0, 3), + MUX_CFG(MUX_SPI4, SPI4_src, RCC_SPI45CKSELR, 0, 3), + MUX_CFG(MUX_SPI5, SPI5_src, RCC_SPI45CKSELR, 3, 3), + MUX_CFG(MUX_STGEN, STGEN_src, RCC_STGENCKSELR, 0, 2), + MUX_CFG(MUX_UART1, UART1_src, RCC_UART12CKSELR, 0, 3), + MUX_CFG(MUX_UART2, UART2_src, RCC_UART12CKSELR, 3, 3), + MUX_CFG(MUX_UART35, UART35_src, RCC_UART35CKSELR, 0, 3), + MUX_CFG(MUX_UART4, UART4_src, RCC_UART4CKSELR, 0, 3), + MUX_CFG(MUX_UART6, UART6_src, RCC_UART6CKSELR, 0, 3), + MUX_CFG(MUX_UART78, UART78_src, RCC_UART78CKSELR, 0, 3), + MUX_CFG(MUX_USBO, USBO_src, RCC_USBCKSELR, 4, 1), + MUX_CFG(MUX_USBPHY, USBPHY_src, RCC_USBCKSELR, 0, 2), +}; + +/* + * GATE CONFIG + */ + +enum enum_gate_cfg { + GATE_ZERO, /* reserved for no gate */ + GATE_LSE, + GATE_RTCCK, + GATE_LSI, + GATE_HSI, + GATE_CSI, + GATE_HSE, + GATE_LSI_RDY, + GATE_CSI_RDY, + GATE_LSE_RDY, + GATE_HSE_RDY, + GATE_HSI_RDY, + GATE_MCO1, + GATE_MCO2, + GATE_DBGCK, + GATE_TRACECK, + GATE_PLL1, + GATE_PLL1_DIVP, + GATE_PLL1_DIVQ, + GATE_PLL1_DIVR, + GATE_PLL2, + GATE_PLL2_DIVP, + GATE_PLL2_DIVQ, + GATE_PLL2_DIVR, + GATE_PLL3, + GATE_PLL3_DIVP, + GATE_PLL3_DIVQ, + GATE_PLL3_DIVR, + GATE_PLL4, + GATE_PLL4_DIVP, + GATE_PLL4_DIVQ, + GATE_PLL4_DIVR, + GATE_DDRC1, + GATE_DDRC1LP, + GATE_DDRPHYC, + GATE_DDRPHYCLP, + GATE_DDRCAPB, + GATE_DDRCAPBLP, + GATE_AXIDCG, + GATE_DDRPHYCAPB, + GATE_DDRPHYCAPBLP, + GATE_TIM2, + GATE_TIM3, + GATE_TIM4, + GATE_TIM5, + GATE_TIM6, + GATE_TIM7, + GATE_LPTIM1, + GATE_SPI2, + GATE_SPI3, + GATE_USART3, + GATE_UART4, + GATE_UART5, + GATE_UART7, + GATE_UART8, + GATE_I2C1, + GATE_I2C2, + GATE_SPDIF, + GATE_TIM1, + GATE_TIM8, + GATE_SPI1, + GATE_USART6, + GATE_SAI1, + GATE_SAI2, + GATE_DFSDM, + GATE_ADFSDM, + GATE_FDCAN, + GATE_LPTIM2, + GATE_LPTIM3, + GATE_LPTIM4, + GATE_LPTIM5, + GATE_VREF, + GATE_DTS, + GATE_PMBCTRL, + GATE_HDP, + GATE_SYSCFG, + GATE_DCMIPP, + GATE_DDRPERFM, + GATE_IWDG2APB, + GATE_USBPHY, + GATE_STGENRO, + GATE_LTDC, + GATE_RTCAPB, + GATE_TZC, + GATE_ETZPC, + GATE_IWDG1APB, + GATE_BSEC, + GATE_STGENC, + GATE_USART1, + GATE_USART2, + GATE_SPI4, + GATE_SPI5, + GATE_I2C3, + GATE_I2C4, + GATE_I2C5, + GATE_TIM12, + GATE_TIM13, + GATE_TIM14, + GATE_TIM15, + GATE_TIM16, + GATE_TIM17, + GATE_DMA1, + GATE_DMA2, + GATE_DMAMUX1, + GATE_DMA3, + GATE_DMAMUX2, + GATE_ADC1, + GATE_ADC2, + GATE_USBO, + GATE_TSC, + GATE_GPIOA, + GATE_GPIOB, + GATE_GPIOC, + GATE_GPIOD, + GATE_GPIOE, + GATE_GPIOF, + GATE_GPIOG, + GATE_GPIOH, + GATE_GPIOI, + GATE_PKA, + GATE_SAES, + GATE_CRYP1, + GATE_HASH1, + GATE_RNG1, + GATE_BKPSRAM, + GATE_AXIMC, + GATE_MCE, + GATE_ETH1CK, + GATE_ETH1TX, + GATE_ETH1RX, + GATE_ETH1MAC, + GATE_FMC, + GATE_QSPI, + GATE_SDMMC1, + GATE_SDMMC2, + GATE_CRC1, + GATE_USBH, + GATE_ETH2CK, + GATE_ETH2TX, + GATE_ETH2RX, + GATE_ETH2MAC, + GATE_MDMA, + + LAST_GATE +}; + +#define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ + .offset = (_offset),\ + .bit_idx = (_bit_idx),\ + .set_clr = (_offset_clr),\ +} + +static const struct gate_cfg gates_mp13[LAST_GATE] = { + GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0), + GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0), + GATE_CFG(GATE_LSI, RCC_RDLSICR, 0, 0), + GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1), + GATE_CFG(GATE_CSI, RCC_OCENSETR, 4, 1), + GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1), + GATE_CFG(GATE_LSI_RDY, RCC_RDLSICR, 1, 0), + GATE_CFG(GATE_CSI_RDY, RCC_OCRDYR, 4, 0), + GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0), + GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0), + GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0), + GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 12, 0), + GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 12, 0), + GATE_CFG(GATE_DBGCK, RCC_DBGCFGR, 8, 0), + GATE_CFG(GATE_TRACECK, RCC_DBGCFGR, 9, 0), + GATE_CFG(GATE_PLL1, RCC_PLL1CR, 0, 0), + GATE_CFG(GATE_PLL1_DIVP, RCC_PLL1CR, 4, 0), + GATE_CFG(GATE_PLL1_DIVQ, RCC_PLL1CR, 5, 0), + GATE_CFG(GATE_PLL1_DIVR, RCC_PLL1CR, 6, 0), + GATE_CFG(GATE_PLL2, RCC_PLL2CR, 0, 0), + GATE_CFG(GATE_PLL2_DIVP, RCC_PLL2CR, 4, 0), + GATE_CFG(GATE_PLL2_DIVQ, RCC_PLL2CR, 5, 0), + GATE_CFG(GATE_PLL2_DIVR, RCC_PLL2CR, 6, 0), + GATE_CFG(GATE_PLL3, RCC_PLL3CR, 0, 0), + GATE_CFG(GATE_PLL3_DIVP, RCC_PLL3CR, 4, 0), + GATE_CFG(GATE_PLL3_DIVQ, RCC_PLL3CR, 5, 0), + GATE_CFG(GATE_PLL3_DIVR, RCC_PLL3CR, 6, 0), + GATE_CFG(GATE_PLL4, RCC_PLL4CR, 0, 0), + GATE_CFG(GATE_PLL4_DIVP, RCC_PLL4CR, 4, 0), + GATE_CFG(GATE_PLL4_DIVQ, RCC_PLL4CR, 5, 0), + GATE_CFG(GATE_PLL4_DIVR, RCC_PLL4CR, 6, 0), + GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0), + GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0), + GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0), + GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0), + GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0), + GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0), + GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0), + GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0), + GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0), + GATE_CFG(GATE_TIM2, RCC_MP_APB1ENSETR, 0, 1), + GATE_CFG(GATE_TIM3, RCC_MP_APB1ENSETR, 1, 1), + GATE_CFG(GATE_TIM4, RCC_MP_APB1ENSETR, 2, 1), + GATE_CFG(GATE_TIM5, RCC_MP_APB1ENSETR, 3, 1), + GATE_CFG(GATE_TIM6, RCC_MP_APB1ENSETR, 4, 1), + GATE_CFG(GATE_TIM7, RCC_MP_APB1ENSETR, 5, 1), + GATE_CFG(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9, 1), + GATE_CFG(GATE_SPI2, RCC_MP_APB1ENSETR, 11, 1), + GATE_CFG(GATE_SPI3, RCC_MP_APB1ENSETR, 12, 1), + GATE_CFG(GATE_USART3, RCC_MP_APB1ENSETR, 15, 1), + GATE_CFG(GATE_UART4, RCC_MP_APB1ENSETR, 16, 1), + GATE_CFG(GATE_UART5, RCC_MP_APB1ENSETR, 17, 1), + GATE_CFG(GATE_UART7, RCC_MP_APB1ENSETR, 18, 1), + GATE_CFG(GATE_UART8, RCC_MP_APB1ENSETR, 19, 1), + GATE_CFG(GATE_I2C1, RCC_MP_APB1ENSETR, 21, 1), + GATE_CFG(GATE_I2C2, RCC_MP_APB1ENSETR, 22, 1), + GATE_CFG(GATE_SPDIF, RCC_MP_APB1ENSETR, 26, 1), + GATE_CFG(GATE_TIM1, RCC_MP_APB2ENSETR, 0, 1), + GATE_CFG(GATE_TIM8, RCC_MP_APB2ENSETR, 1, 1), + GATE_CFG(GATE_SPI1, RCC_MP_APB2ENSETR, 8, 1), + GATE_CFG(GATE_USART6, RCC_MP_APB2ENSETR, 13, 1), + GATE_CFG(GATE_SAI1, RCC_MP_APB2ENSETR, 16, 1), + GATE_CFG(GATE_SAI2, RCC_MP_APB2ENSETR, 17, 1), + GATE_CFG(GATE_DFSDM, RCC_MP_APB2ENSETR, 20, 1), + GATE_CFG(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21, 1), + GATE_CFG(GATE_FDCAN, RCC_MP_APB2ENSETR, 24, 1), + GATE_CFG(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0, 1), + GATE_CFG(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1, 1), + GATE_CFG(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2, 1), + GATE_CFG(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3, 1), + GATE_CFG(GATE_VREF, RCC_MP_APB3ENSETR, 13, 1), + GATE_CFG(GATE_DTS, RCC_MP_APB3ENSETR, 16, 1), + GATE_CFG(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17, 1), + GATE_CFG(GATE_HDP, RCC_MP_APB3ENSETR, 20, 1), + GATE_CFG(GATE_SYSCFG, RCC_MP_S_APB3ENSETR, 0, 1), + GATE_CFG(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1, 1), + GATE_CFG(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8, 1), + GATE_CFG(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15, 1), + GATE_CFG(GATE_USBPHY, RCC_MP_APB4ENSETR, 16, 1), + GATE_CFG(GATE_STGENRO, RCC_MP_APB4ENSETR, 20, 1), + GATE_CFG(GATE_LTDC, RCC_MP_S_APB4ENSETR, 0, 1), + GATE_CFG(GATE_RTCAPB, RCC_MP_APB5ENSETR, 8, 1), + GATE_CFG(GATE_TZC, RCC_MP_APB5ENSETR, 11, 1), + GATE_CFG(GATE_ETZPC, RCC_MP_APB5ENSETR, 13, 1), + GATE_CFG(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15, 1), + GATE_CFG(GATE_BSEC, RCC_MP_APB5ENSETR, 16, 1), + GATE_CFG(GATE_STGENC, RCC_MP_APB5ENSETR, 20, 1), + GATE_CFG(GATE_USART1, RCC_MP_APB6ENSETR, 0, 1), + GATE_CFG(GATE_USART2, RCC_MP_APB6ENSETR, 1, 1), + GATE_CFG(GATE_SPI4, RCC_MP_APB6ENSETR, 2, 1), + GATE_CFG(GATE_SPI5, RCC_MP_APB6ENSETR, 3, 1), + GATE_CFG(GATE_I2C3, RCC_MP_APB6ENSETR, 4, 1), + GATE_CFG(GATE_I2C4, RCC_MP_APB6ENSETR, 5, 1), + GATE_CFG(GATE_I2C5, RCC_MP_APB6ENSETR, 6, 1), + GATE_CFG(GATE_TIM12, RCC_MP_APB6ENSETR, 7, 1), + GATE_CFG(GATE_TIM13, RCC_MP_APB6ENSETR, 8, 1), + GATE_CFG(GATE_TIM14, RCC_MP_APB6ENSETR, 9, 1), + GATE_CFG(GATE_TIM15, RCC_MP_APB6ENSETR, 10, 1), + GATE_CFG(GATE_TIM16, RCC_MP_APB6ENSETR, 11, 1), + GATE_CFG(GATE_TIM17, RCC_MP_APB6ENSETR, 12, 1), + GATE_CFG(GATE_DMA1, RCC_MP_AHB2ENSETR, 0, 1), + GATE_CFG(GATE_DMA2, RCC_MP_AHB2ENSETR, 1, 1), + GATE_CFG(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2, 1), + GATE_CFG(GATE_DMA3, RCC_MP_AHB2ENSETR, 3, 1), + GATE_CFG(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4, 1), + GATE_CFG(GATE_ADC1, RCC_MP_AHB2ENSETR, 5, 1), + GATE_CFG(GATE_ADC2, RCC_MP_AHB2ENSETR, 6, 1), + GATE_CFG(GATE_USBO, RCC_MP_AHB2ENSETR, 8, 1), + GATE_CFG(GATE_TSC, RCC_MP_AHB4ENSETR, 15, 1), + + GATE_CFG(GATE_GPIOA, RCC_MP_S_AHB4ENSETR, 0, 1), + GATE_CFG(GATE_GPIOB, RCC_MP_S_AHB4ENSETR, 1, 1), + GATE_CFG(GATE_GPIOC, RCC_MP_S_AHB4ENSETR, 2, 1), + GATE_CFG(GATE_GPIOD, RCC_MP_S_AHB4ENSETR, 3, 1), + GATE_CFG(GATE_GPIOE, RCC_MP_S_AHB4ENSETR, 4, 1), + GATE_CFG(GATE_GPIOF, RCC_MP_S_AHB4ENSETR, 5, 1), + GATE_CFG(GATE_GPIOG, RCC_MP_S_AHB4ENSETR, 6, 1), + GATE_CFG(GATE_GPIOH, RCC_MP_S_AHB4ENSETR, 7, 1), + GATE_CFG(GATE_GPIOI, RCC_MP_S_AHB4ENSETR, 8, 1), + + GATE_CFG(GATE_PKA, RCC_MP_AHB5ENSETR, 2, 1), + GATE_CFG(GATE_SAES, RCC_MP_AHB5ENSETR, 3, 1), + GATE_CFG(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4, 1), + GATE_CFG(GATE_HASH1, RCC_MP_AHB5ENSETR, 5, 1), + GATE_CFG(GATE_RNG1, RCC_MP_AHB5ENSETR, 6, 1), + GATE_CFG(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8, 1), + GATE_CFG(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16, 1), + GATE_CFG(GATE_MCE, RCC_MP_AHB6ENSETR, 1, 1), + GATE_CFG(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7, 1), + GATE_CFG(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8, 1), + GATE_CFG(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9, 1), + GATE_CFG(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10, 1), + GATE_CFG(GATE_FMC, RCC_MP_AHB6ENSETR, 12, 1), + GATE_CFG(GATE_QSPI, RCC_MP_AHB6ENSETR, 14, 1), + GATE_CFG(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16, 1), + GATE_CFG(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17, 1), + GATE_CFG(GATE_CRC1, RCC_MP_AHB6ENSETR, 20, 1), + GATE_CFG(GATE_USBH, RCC_MP_AHB6ENSETR, 24, 1), + GATE_CFG(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27, 1), + GATE_CFG(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28, 1), + GATE_CFG(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29, 1), + GATE_CFG(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30, 1), + GATE_CFG(GATE_MDMA, RCC_MP_S_AHB6ENSETR, 0, 1), +}; + +/* + * DIV CONFIG + */ + +static const struct clk_div_table axi_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, + { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 }, + { 0 }, +}; + +static const struct clk_div_table mlahb_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, + { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 }, + { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 }, + { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 }, + { 0 }, +}; + +static const struct clk_div_table apb_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, + { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 }, + { 0 }, +}; + +#define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ + .offset = _offset,\ + .shift = _shift,\ + .width = _width,\ + .flags = _flags,\ + .table = _table,\ + .bitrdy = _bitrdy,\ +} + +static const struct div_cfg dividers_mp13[] = { + DIV_CFG(DIV_PLL1DIVP, RCC_PLL1CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL2DIVP, RCC_PLL2CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL2DIVQ, RCC_PLL2CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL2DIVR, RCC_PLL2CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL3DIVP, RCC_PLL3CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL3DIVQ, RCC_PLL3CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL3DIVR, RCC_PLL3CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL4DIVP, RCC_PLL4CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL4DIVQ, RCC_PLL4CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL4DIVR, RCC_PLL4CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 0, axi_div_table, 31), + DIV_CFG(DIV_MLAHB, RCC_MLAHBDIVR, 0, 4, 0, mlahb_div_table, 31), + DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB6, RCC_APB6DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY), + + DIV_CFG(DIV_HSI, RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY), + + DIV_CFG(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_BIT_RDY), +}; + +#define MAX_HSI_HZ 64000000 +#define USB_PHY_48_MHZ 48000000 + +#define TIMEOUT_US_200MS U(200000) +#define TIMEOUT_US_1S U(1000000) + +#define PLLRDY_TIMEOUT TIMEOUT_US_200MS +#define CLKSRC_TIMEOUT TIMEOUT_US_200MS +#define CLKDIV_TIMEOUT TIMEOUT_US_200MS +#define HSIDIV_TIMEOUT TIMEOUT_US_200MS +#define OSCRDY_TIMEOUT TIMEOUT_US_1S + +enum stm32_osc { + OSC_HSI, + OSC_HSE, + OSC_CSI, + OSC_LSI, + OSC_LSE, + OSC_I2SCKIN, + NB_OSCILLATOR +}; + +enum stm32mp1_pll_id { + _PLL1, + _PLL2, + _PLL3, + _PLL4, + _PLL_NB +}; + +enum stm32mp1_plltype { + PLL_800, + PLL_1600, + PLL_2000, + PLL_TYPE_NB +}; + +#define RCC_OFFSET_PLLXCR 0 +#define RCC_OFFSET_PLLXCFGR1 4 +#define RCC_OFFSET_PLLXCFGR2 8 +#define RCC_OFFSET_PLLXFRACR 12 +#define RCC_OFFSET_PLLXCSGR 16 + +struct stm32_clk_pll { + enum stm32mp1_plltype plltype; + uint16_t clk_id; + uint16_t reg_pllxcr; +}; + +struct stm32mp1_pll { + uint8_t refclk_min; + uint8_t refclk_max; +}; + +/* Define characteristic of PLL according type */ +static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { + [PLL_800] = { + .refclk_min = 4, + .refclk_max = 16, + }, + [PLL_1600] = { + .refclk_min = 8, + .refclk_max = 16, + }, + [PLL_2000] = { + .refclk_min = 8, + .refclk_max = 16, + }, +}; + +#if STM32MP_USB_PROGRAMMER +static bool pll4_bootrom; +#endif + +/* RCC clock device driver private */ +static unsigned int refcounts_mp13[CK_LAST]; + +static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx); + +#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER +static void clk_oscillator_check_bypass(struct stm32_clk_priv *priv, int idx, + bool digbyp, bool bypass) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, idx); + struct stm32_clk_bypass *bypass_data = osc_data->bypass; + uintptr_t address; + + if (bypass_data == NULL) { + return; + } + + address = priv->base + bypass_data->offset; + if ((mmio_read_32(address) & RCC_OCENR_HSEBYP) && + (!(digbyp || bypass))) { + panic(); + } +} +#endif + +static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv) +{ + struct stm32_clk_platdata *pdata = priv->pdata; + struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE]; + bool digbyp = osci->digbyp; + bool bypass = osci->bypass; + bool css = osci->css; + + if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) { + return; + } + + clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass); + + _clk_stm32_enable(priv, _CK_HSE); + +#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER + clk_oscillator_check_bypass(priv, _CK_HSE, digbyp, bypass); +#endif + + clk_oscillator_set_css(priv, _CK_HSE, css); +} + +static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE); + struct stm32_clk_platdata *pdata = priv->pdata; + struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; + bool digbyp = osci->digbyp; + bool bypass = osci->bypass; + uint8_t drive = osci->drive; + + if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) { + return; + } + + clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass); + + clk_oscillator_set_drive(priv, _CK_LSE, drive); + + _clk_stm32_gate_enable(priv, osc_data->gate_id); +} + +static int stm32mp1_set_hsidiv(uint8_t hsidiv) +{ + uint64_t timeout; + uintptr_t rcc_base = stm32mp_rcc_base(); + uintptr_t address = rcc_base + RCC_OCRDYR; + + mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, + RCC_HSICFGR_HSIDIV_MASK, + RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); + + timeout = timeout_init_us(HSIDIV_TIMEOUT); + while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { + if (timeout_elapsed(timeout)) { + ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", + address, mmio_read_32(address)); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int stm32mp1_hsidiv(unsigned long hsifreq) +{ + uint8_t hsidiv; + uint32_t hsidivfreq = MAX_HSI_HZ; + + for (hsidiv = 0; hsidiv < 4U; hsidiv++) { + if (hsidivfreq == hsifreq) { + break; + } + + hsidivfreq /= 2U; + } + + if (hsidiv == 4U) { + ERROR("Invalid clk-hsi frequency\n"); + return -EINVAL; + } + + if (hsidiv != 0U) { + return stm32mp1_set_hsidiv(hsidiv); + } + + return 0; +} + +static int stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv *priv) +{ + struct stm32_clk_platdata *pdata = priv->pdata; + struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; + + clk_oscillator_set_css(priv, _CK_LSE, osci->css); + + return 0; +} + +static int stm32mp1_come_back_to_hsi(void) +{ + int ret; + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + + /* Come back to HSI */ + ret = _clk_stm32_set_parent(priv, _CKMPU, _CK_HSI); + if (ret != 0) { + return ret; + } + + ret = _clk_stm32_set_parent(priv, _CKAXI, _CK_HSI); + if (ret != 0) { + return ret; + } + + ret = _clk_stm32_set_parent(priv, _CKMLAHB, _CK_HSI); + if (ret != 0) { + return ret; + } + + return 0; +} + +static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data) +{ + unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT; + + return clk_get_index(priv, binding_id); +} + +static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data) +{ + int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; + int enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT; + int clk_id; + int ret; + + clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); + if (clk_id < 0) { + return clk_id; + } + + ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); + if (ret != 0) { + return ret; + } + + if (enable) { + clk_stm32_enable_call_ops(priv, clk_id); + } else { + clk_stm32_disable_call_ops(priv, clk_id); + } + + return 0; +} + +static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data) +{ + int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; + int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; + + return clk_mux_set_parent(priv, mux, sel); +} + +static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv) +{ + struct stm32_clk_platdata *pdata = priv->pdata; + uint32_t i; + + for (i = 0; i < pdata->nclkdiv; i++) { + int div_id, div_n; + int val; + int ret; + + val = pdata->clkdiv[i] & CMD_DATA_MASK; + div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT; + div_n = (val & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; + + ret = clk_stm32_set_div(priv, div_id, div_n); + if (ret != 0) { + return ret; + } + } + + return 0; +} + +static int stm32_clk_source_configure(struct stm32_clk_priv *priv) +{ + struct stm32_clk_platdata *pdata = priv->pdata; + bool ckper_disabled = false; + int clk_id; + int ret; + uint32_t i; + + for (i = 0; i < pdata->nclksrc; i++) { + uint32_t val = pdata->clksrc[i]; + uint32_t cmd, cmd_data; + + if (val == (uint32_t)CLK_CKPER_DISABLED) { + ckper_disabled = true; + continue; + } + + if (val == (uint32_t)CLK_RTC_DISABLED) { + continue; + } + + cmd = (val & CMD_MASK) >> CMD_SHIFT; + cmd_data = val & ~CMD_MASK; + + switch (cmd) { + case CMD_MUX: + ret = stm32_clk_configure_mux(priv, cmd_data); + break; + + case CMD_CLK: + clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data); + + if (clk_id == _RTCCK) { + if ((_clk_stm32_is_enabled(priv, _RTCCK) == true)) { + continue; + } + } + + ret = stm32_clk_configure_clk(priv, cmd_data); + break; + default: + ret = -EINVAL; + break; + } + + if (ret != 0) { + return ret; + } + } + + /* + * CKPER is source for some peripheral clocks + * (FMC-NAND / QPSI-NOR) and switching source is allowed + * only if previous clock is still ON + * => deactivate CKPER only after switching clock + */ + if (ckper_disabled) { + ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED & CMD_MASK); + if (ret != 0) { + return ret; + } + } + + return 0; +} + +static int stm32_clk_stgen_configure(struct stm32_clk_priv *priv, int id) +{ + unsigned long stgen_freq; + + stgen_freq = _clk_stm32_get_rate(priv, id); + + stm32mp_stgen_config(stgen_freq); + + return 0; +} + +#define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ + [(_idx)] = {\ + .clk_id = (_clk_id),\ + .plltype = (_type),\ + .reg_pllxcr = (_reg),\ + } + +static int clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll, + struct stm32_pll_vco *vco, + uint32_t *value) +{ + uint32_t divm = vco->div_mn[PLL_CFG_M]; + uint32_t divn = vco->div_mn[PLL_CFG_N]; + unsigned long prate = 0UL; + unsigned long refclk = 0UL; + + prate = _clk_stm32_get_parent_rate(priv, pll->clk_id); + refclk = prate / (divm + 1U); + + if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) || + (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) { + return -EINVAL; + } + + *value = 0; + + if ((pll->plltype == PLL_800) && (refclk >= 8000000U)) { + *value = 1U << RCC_PLLNCFGR1_IFRGE_SHIFT; + } + + *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK; + *value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK; + + return 0; +} + +static uint32_t clk_stm32_pll_compute_cfgr2(struct stm32_pll_output *out) +{ + uint32_t value = 0; + + value |= (out->output[PLL_CFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & RCC_PLLNCFGR2_DIVP_MASK; + value |= (out->output[PLL_CFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & RCC_PLLNCFGR2_DIVQ_MASK; + value |= (out->output[PLL_CFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & RCC_PLLNCFGR2_DIVR_MASK; + + return value; +} + +static void clk_stm32_pll_config_vco(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll, + struct stm32_pll_vco *vco) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint32_t value = 0; + + if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) { + ERROR("Invalid Vref clock !\n"); + panic(); + } + + /* Write N / M / IFREGE fields */ + mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR1, value); + + /* Fractional configuration */ + mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, 0); + + /* Frac must be enabled only once its configuration is loaded */ + mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, vco->frac << RCC_PLLNFRACR_FRACV_SHIFT); + mmio_setbits_32(pll_base + RCC_OFFSET_PLLXFRACR, RCC_PLLNFRACR_FRACLE); +} + +static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll, + struct stm32_pll_vco *vco) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint32_t mod_per = 0; + uint32_t inc_step = 0; + uint32_t sscg_mode = 0; + uint32_t value = 0; + + if (!vco->csg_enabled) { + return; + } + + mod_per = vco->csg[PLL_CSG_MOD_PER]; + inc_step = vco->csg[PLL_CSG_INC_STEP]; + sscg_mode = vco->csg[PLL_CSG_SSCG_MODE]; + + value |= (mod_per << RCC_PLLNCSGR_MOD_PER_SHIFT) & RCC_PLLNCSGR_MOD_PER_MASK; + value |= (inc_step << RCC_PLLNCSGR_INC_STEP_SHIFT) & RCC_PLLNCSGR_INC_STEP_MASK; + value |= (sscg_mode << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & RCC_PLLNCSGR_SSCG_MODE_MASK; + + mmio_write_32(pll_base + RCC_OFFSET_PLLXCSGR, value); + mmio_setbits_32(pll_base + RCC_OFFSET_PLLXCR, RCC_PLLNCR_SSCG_CTRL); +} + +static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll, + struct stm32_pll_output *out) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint32_t value = 0; + + value = clk_stm32_pll_compute_cfgr2(out); + + mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR2, value); +} + +static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + struct stm32_clk_platdata *pdata = priv->pdata; + + return &pdata->pll[pll_idx]; +} + +static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + + return ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLON) != 0U); +} + +static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + + /* Preserve RCC_PLLNCR_SSCG_CTRL value */ + mmio_clrsetbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN, + RCC_PLLNCR_PLLON); +} + +static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + + /* Stop all output */ + mmio_clrbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); + + /* Stop PLL */ + mmio_clrbits_32(pll_base, RCC_PLLNCR_PLLON); +} + +static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); + + /* Wait PLL lock */ + while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) == 0U) { + if (timeout_elapsed(timeout)) { + ERROR("%d clock start failed @ 0x%x: 0x%x\n", + pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base)); + return -EINVAL; + } + } + + return 0; +} + +static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); + + /* Wait PLL lock */ + while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) != 0U) { + if (timeout_elapsed(timeout)) { + ERROR("%d clock stop failed @ 0x%x: 0x%x\n", + pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base)); + return -EINVAL; + } + } + + return 0; +} + +static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + if (_clk_stm32_pll_is_enabled(priv, pll)) { + return 0; + } + + /* Preserve RCC_PLLNCR_SSCG_CTRL value */ + _clk_stm32_pll_set_on(priv, pll); + + /* Wait PLL lock */ + return _clk_stm32_pll_wait_ready_on(priv, pll); +} + +static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + if (!_clk_stm32_pll_is_enabled(priv, pll)) { + return; + } + + /* Stop all outputs and the PLL */ + _clk_stm32_pll_set_off(priv, pll); + + /* Wait PLL stopped */ + _clk_stm32_pll_wait_ready_off(priv, pll); +} + +static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx, + struct stm32_pll_dt_cfg *pll_conf) +{ + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_idx); + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + int ret = 0; + + /* Configure PLLs source */ + ret = stm32_clk_configure_mux(priv, pll_conf->vco.src); + if (ret) { + return ret; + } + +#if STM32MP_USB_PROGRAMMER + if ((pll_idx == _PLL4) && pll4_bootrom) { + clk_stm32_pll_config_out(priv, pll, &pll_conf->output); + + mmio_setbits_32(pll_base, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); + + return 0; + } +#endif + /* Stop the PLL before */ + _clk_stm32_pll_disable(priv, pll); + + clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco); + clk_stm32_pll_config_out(priv, pll, &pll_conf->output); + clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco); + + ret = _clk_stm32_pll_enable(priv, pll); + if (ret != 0) { + return ret; + } + + mmio_setbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); + + return 0; +} + +static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx) +{ + struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx); + + if (pll_conf->vco.status) { + return _clk_stm32_pll_init(priv, pll_idx, pll_conf); + } + + return 0; +} + +static int stm32_clk_pll_configure(struct stm32_clk_priv *priv) +{ + int err = 0; + + err = clk_stm32_pll_init(priv, _PLL1); + if (err) { + return err; + } + + err = clk_stm32_pll_init(priv, _PLL2); + if (err) { + return err; + } + + err = clk_stm32_pll_init(priv, _PLL3); + if (err) { + return err; + } + + err = clk_stm32_pll_init(priv, _PLL4); + if (err) { + return err; + } + + return 0; +} + +static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv) +{ + int ret = 0; + + if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) { + ret = clk_oscillator_wait_ready_on(priv, _CK_LSE); + } + + return ret; +} + +static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv) +{ + stm32_enable_oscillator_hse(priv); + stm32_enable_oscillator_lse(priv); + _clk_stm32_enable(priv, _CK_LSI); + _clk_stm32_enable(priv, _CK_CSI); +} + +static int stm32_clk_hsidiv_configure(struct stm32_clk_priv *priv) +{ + return stm32mp1_hsidiv(_clk_stm32_get_rate(priv, _CK_HSI)); +} + +#if STM32MP_USB_PROGRAMMER +static bool stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv *priv, int usbphy_p) +{ + /* Don't initialize PLL4, when used by BOOTROM */ + if ((stm32mp_get_boot_itf_selected() == + BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && + (usbphy_p == _PLL4R)) { + return true; + } + + return false; +} + +static int stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv *priv, int usbphy_p, int usbo_p) +{ + int _usbo_p; + int _usbphy_p; + + if (!pll4_bootrom) { + return 0; + } + + _usbo_p = _clk_stm32_get_parent(priv, _USBO_K); + _usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K); + + if ((_usbo_p != usbo_p) || (_usbphy_p != usbphy_p)) { + return -FDT_ERR_BADVALUE; + } + + return 0; +} +#endif + +static struct clk_oscillator_data stm32mp13_osc_data[NB_OSCILLATOR] = { + OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY, + NULL, NULL, NULL), + + OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY, + NULL, NULL, NULL), + + OSCILLATOR(OSC_CSI, _CK_CSI, "clk-csi", GATE_CSI, GATE_CSI_RDY, + NULL, NULL, NULL), + + OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY, + BYPASS(RCC_BDCR, 1, 3), + CSS(RCC_BDCR, 8), + DRIVE(RCC_BDCR, 4, 2, 2)), + + OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY, + BYPASS(RCC_OCENSETR, 10, 7), + CSS(RCC_OCENSETR, 11), + NULL), + + OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE, + NULL, NULL, NULL), +}; + +static const char *clk_stm32_get_oscillator_name(enum stm32_osc id) +{ + if (id < NB_OSCILLATOR) { + return stm32mp13_osc_data[id].name; + } + + return NULL; +} + +#define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ + [(_idx)] = {\ + .clk_id = (_clk_id),\ + .plltype = (_type),\ + .reg_pllxcr = (_reg),\ + } + +static const struct stm32_clk_pll stm32_mp13_clk_pll[_PLL_NB] = { + CLK_PLL_CFG(_PLL1, _CK_PLL1, PLL_2000, RCC_PLL1CR), + CLK_PLL_CFG(_PLL2, _CK_PLL2, PLL_1600, RCC_PLL2CR), + CLK_PLL_CFG(_PLL3, _CK_PLL3, PLL_800, RCC_PLL3CR), + CLK_PLL_CFG(_PLL4, _CK_PLL4, PLL_800, RCC_PLL4CR), +}; + +static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx) +{ + return &stm32_mp13_clk_pll[idx]; +} + +struct stm32_pll_cfg { + int pll_id; +}; + +static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id, + unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint32_t cfgr1, fracr, divm, divn; + unsigned long fvco; + + cfgr1 = mmio_read_32(pll_base + RCC_OFFSET_PLLXCFGR1); + fracr = mmio_read_32(pll_base + RCC_OFFSET_PLLXFRACR); + + divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; + divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; + + /* + * With FRACV : + * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) + * Without FRACV + * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) + */ + if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { + uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> + RCC_PLLNFRACR_FRACV_SHIFT; + unsigned long long numerator, denominator; + + numerator = (((unsigned long long)divn + 1U) << 13) + fracv; + numerator = prate * numerator; + denominator = ((unsigned long long)divm + 1U) << 13; + fvco = (unsigned long)(numerator / denominator); + } else { + fvco = (unsigned long)(prate * (divn + 1U) / (divm + 1U)); + } + + return fvco; +}; + +static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); + + return _clk_stm32_pll_is_enabled(priv, pll); +} + +static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); + + return _clk_stm32_pll_enable(priv, pll); +} + +static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); + + _clk_stm32_pll_disable(priv, pll); +} + +static const struct stm32_clk_ops clk_stm32_pll_ops = { + .recalc_rate = clk_stm32_pll_recalc_rate, + .enable = clk_stm32_pll_enable, + .disable = clk_stm32_pll_disable, + .is_enabled = clk_stm32_pll_is_enabled, +}; + +#define CLK_PLL(idx, _idx, _parent, _gate, _pll_id, _flags)[idx] = {\ + .name = #idx,\ + .binding = _idx,\ + .parent = _parent,\ + .flags = (_flags),\ + .clock_cfg = &(struct stm32_pll_cfg) {\ + .pll_id = _pll_id,\ + },\ + .ops = &clk_stm32_pll_ops,\ +} + +struct clk_stm32_composite_cfg { + int gate_id; + int div_id; +}; + +static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv, + int idx, unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, idx); + struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; + + return _clk_stm32_divider_recalc(priv, composite_cfg->div_id, prate); +}; + +static bool clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv *priv, int idx) +{ + const struct clk_stm32 *clk = _clk_get(priv, idx); + struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; + + return _clk_stm32_gate_is_enabled(priv, composite_cfg->gate_id); +} + +static int clk_stm32_composite_gate_enable(struct stm32_clk_priv *priv, int idx) +{ + const struct clk_stm32 *clk = _clk_get(priv, idx); + struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; + + return _clk_stm32_gate_enable(priv, composite_cfg->gate_id); +} + +static void clk_stm32_composite_gate_disable(struct stm32_clk_priv *priv, int idx) +{ + const struct clk_stm32 *clk = _clk_get(priv, idx); + struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; + + _clk_stm32_gate_disable(priv, composite_cfg->gate_id); +} + +static const struct stm32_clk_ops clk_stm32_composite_ops = { + .recalc_rate = clk_stm32_composite_recalc_rate, + .is_enabled = clk_stm32_composite_gate_is_enabled, + .enable = clk_stm32_composite_gate_enable, + .disable = clk_stm32_composite_gate_disable, +}; + +#define STM32_COMPOSITE(idx, _binding, _parent, _flags, _gate_id,\ + _div_id)[idx] = {\ + .name = #idx,\ + .binding = (_binding),\ + .parent = (_parent),\ + .flags = (_flags),\ + .clock_cfg = &(struct clk_stm32_composite_cfg) {\ + .gate_id = (_gate_id),\ + .div_id = (_div_id),\ + },\ + .ops = &clk_stm32_composite_ops,\ +} + +static const struct clk_stm32 stm32mp13_clk[CK_LAST] = { + /* ROOT CLOCKS */ + CLK_FIXED_RATE(_CK_OFF, _NO_ID, 0), + CLK_OSC(_CK_HSE, CK_HSE, CLK_IS_ROOT, OSC_HSE), + CLK_OSC(_CK_HSI, CK_HSI, CLK_IS_ROOT, OSC_HSI), + CLK_OSC(_CK_CSI, CK_CSI, CLK_IS_ROOT, OSC_CSI), + CLK_OSC(_CK_LSI, CK_LSI, CLK_IS_ROOT, OSC_LSI), + CLK_OSC(_CK_LSE, CK_LSE, CLK_IS_ROOT, OSC_LSE), + + CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN), + + CLK_FIXED_RATE(_USB_PHY_48, _NO_ID, USB_PHY_48_MHZ), + + STM32_DIV(_HSE_DIV, _NO_ID, _CK_HSE, 0, DIV_RTC), + + FIXED_FACTOR(_HSE_DIV2, CK_HSE_DIV2, _CK_HSE, 1, 2), + FIXED_FACTOR(_CSI_DIV122, _NO_ID, _CK_CSI, 1, 122), + + CLK_PLL(_CK_PLL1, PLL1, MUX(MUX_PLL12), GATE_PLL1, _PLL1, 0), + CLK_PLL(_CK_PLL2, PLL2, MUX(MUX_PLL12), GATE_PLL2, _PLL2, 0), + CLK_PLL(_CK_PLL3, PLL3, MUX(MUX_PLL3), GATE_PLL3, _PLL3, 0), + CLK_PLL(_CK_PLL4, PLL4, MUX(MUX_PLL4), GATE_PLL4, _PLL4, 0), + + STM32_COMPOSITE(_PLL1P, PLL1_P, _CK_PLL1, CLK_IS_CRITICAL, GATE_PLL1_DIVP, DIV_PLL1DIVP), + STM32_DIV(_PLL1P_DIV, _NO_ID, _CK_PLL1, 0, DIV_MPU), + + STM32_COMPOSITE(_PLL2P, PLL2_P, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVP, DIV_PLL2DIVP), + STM32_COMPOSITE(_PLL2Q, PLL2_Q, _CK_PLL2, 0, GATE_PLL2_DIVQ, DIV_PLL2DIVQ), + STM32_COMPOSITE(_PLL2R, PLL2_R, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVR, DIV_PLL2DIVR), + + STM32_COMPOSITE(_PLL3P, PLL3_P, _CK_PLL3, 0, GATE_PLL3_DIVP, DIV_PLL3DIVP), + STM32_COMPOSITE(_PLL3Q, PLL3_Q, _CK_PLL3, 0, GATE_PLL3_DIVQ, DIV_PLL3DIVQ), + STM32_COMPOSITE(_PLL3R, PLL3_R, _CK_PLL3, 0, GATE_PLL3_DIVR, DIV_PLL3DIVR), + + STM32_COMPOSITE(_PLL4P, PLL4_P, _CK_PLL4, 0, GATE_PLL4_DIVP, DIV_PLL4DIVP), + STM32_COMPOSITE(_PLL4Q, PLL4_Q, _CK_PLL4, 0, GATE_PLL4_DIVQ, DIV_PLL4DIVQ), + STM32_COMPOSITE(_PLL4R, PLL4_R, _CK_PLL4, 0, GATE_PLL4_DIVR, DIV_PLL4DIVR), + + STM32_MUX(_CKMPU, CK_MPU, MUX_MPU, 0), + STM32_DIV(_CKAXI, CK_AXI, MUX(MUX_AXI), 0, DIV_AXI), + STM32_DIV(_CKMLAHB, CK_MLAHB, MUX(MUX_MLAHB), CLK_IS_CRITICAL, DIV_MLAHB), + STM32_MUX(_CKPER, CK_PER, MUX(MUX_CKPER), 0), + + STM32_DIV(_PCLK1, PCLK1, _CKMLAHB, 0, DIV_APB1), + STM32_DIV(_PCLK2, PCLK2, _CKMLAHB, 0, DIV_APB2), + STM32_DIV(_PCLK3, PCLK3, _CKMLAHB, 0, DIV_APB3), + STM32_DIV(_PCLK4, PCLK4, _CKAXI, 0, DIV_APB4), + STM32_DIV(_PCLK5, PCLK5, _CKAXI, 0, DIV_APB5), + STM32_DIV(_PCLK6, PCLK6, _CKMLAHB, 0, DIV_APB6), + + CK_TIMER(_CKTIMG1, CK_TIMG1, _PCLK1, 0, RCC_APB1DIVR, RCC_TIMG1PRER), + CK_TIMER(_CKTIMG2, CK_TIMG2, _PCLK2, 0, RCC_APB2DIVR, RCC_TIMG2PRER), + CK_TIMER(_CKTIMG3, CK_TIMG3, _PCLK6, 0, RCC_APB6DIVR, RCC_TIMG3PRER), + + /* END ROOT CLOCKS */ + + STM32_GATE(_DDRC1, DDRC1, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1), + STM32_GATE(_DDRC1LP, DDRC1LP, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1LP), + STM32_GATE(_DDRPHYC, DDRPHYC, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYC), + STM32_GATE(_DDRPHYCLP, DDRPHYCLP, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYCLP), + STM32_GATE(_DDRCAPB, DDRCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPB), + STM32_GATE(_DDRCAPBLP, DDRCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPBLP), + STM32_GATE(_AXIDCG, AXIDCG, _CKAXI, CLK_IS_CRITICAL, GATE_AXIDCG), + STM32_GATE(_DDRPHYCAPB, DDRPHYCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPB), + STM32_GATE(_DDRPHYCAPBLP, DDRPHYCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPBLP), + + STM32_GATE(_SYSCFG, SYSCFG, _PCLK3, 0, GATE_SYSCFG), + STM32_GATE(_DDRPERFM, DDRPERFM, _PCLK4, 0, GATE_DDRPERFM), + STM32_GATE(_IWDG2APB, IWDG2, _PCLK4, 0, GATE_IWDG2APB), + STM32_GATE(_USBPHY_K, USBPHY_K, MUX(MUX_USBPHY), 0, GATE_USBPHY), + STM32_GATE(_USBO_K, USBO_K, MUX(MUX_USBO), 0, GATE_USBO), + + STM32_GATE(_RTCAPB, RTCAPB, _PCLK5, CLK_IS_CRITICAL, GATE_RTCAPB), + STM32_GATE(_TZC, TZC, _PCLK5, CLK_IS_CRITICAL, GATE_TZC), + STM32_GATE(_ETZPC, TZPC, _PCLK5, CLK_IS_CRITICAL, GATE_ETZPC), + STM32_GATE(_IWDG1APB, IWDG1, _PCLK5, 0, GATE_IWDG1APB), + STM32_GATE(_BSEC, BSEC, _PCLK5, CLK_IS_CRITICAL, GATE_BSEC), + STM32_GATE(_STGENC, STGEN_K, MUX(MUX_STGEN), CLK_IS_CRITICAL, GATE_STGENC), + + STM32_GATE(_USART1_K, USART1_K, MUX(MUX_UART1), 0, GATE_USART1), + STM32_GATE(_USART2_K, USART2_K, MUX(MUX_UART2), 0, GATE_USART2), + STM32_GATE(_I2C3_K, I2C3_K, MUX(MUX_I2C3), 0, GATE_I2C3), + STM32_GATE(_I2C4_K, I2C4_K, MUX(MUX_I2C4), 0, GATE_I2C4), + STM32_GATE(_I2C5_K, I2C5_K, MUX(MUX_I2C5), 0, GATE_I2C5), + STM32_GATE(_TIM12, TIM12_K, _CKTIMG3, 0, GATE_TIM12), + STM32_GATE(_TIM15, TIM15_K, _CKTIMG3, 0, GATE_TIM15), + + STM32_GATE(_RTCCK, RTC, MUX(MUX_RTC), 0, GATE_RTCCK), + + STM32_GATE(_GPIOA, GPIOA, _CKMLAHB, 0, GATE_GPIOA), + STM32_GATE(_GPIOB, GPIOB, _CKMLAHB, 0, GATE_GPIOB), + STM32_GATE(_GPIOC, GPIOC, _CKMLAHB, 0, GATE_GPIOC), + STM32_GATE(_GPIOD, GPIOD, _CKMLAHB, 0, GATE_GPIOD), + STM32_GATE(_GPIOE, GPIOE, _CKMLAHB, 0, GATE_GPIOE), + STM32_GATE(_GPIOF, GPIOF, _CKMLAHB, 0, GATE_GPIOF), + STM32_GATE(_GPIOG, GPIOG, _CKMLAHB, 0, GATE_GPIOG), + STM32_GATE(_GPIOH, GPIOH, _CKMLAHB, 0, GATE_GPIOH), + STM32_GATE(_GPIOI, GPIOI, _CKMLAHB, 0, GATE_GPIOI), + + STM32_GATE(_PKA, PKA, _CKAXI, 0, GATE_PKA), + STM32_GATE(_SAES_K, SAES_K, MUX(MUX_SAES), 0, GATE_SAES), + STM32_GATE(_CRYP1, CRYP1, _PCLK5, 0, GATE_CRYP1), + STM32_GATE(_HASH1, HASH1, _PCLK5, 0, GATE_HASH1), + + STM32_GATE(_RNG1_K, RNG1_K, MUX(MUX_RNG1), 0, GATE_RNG1), + STM32_GATE(_BKPSRAM, BKPSRAM, _PCLK5, CLK_IS_CRITICAL, GATE_BKPSRAM), + + STM32_GATE(_SDMMC1_K, SDMMC1_K, MUX(MUX_SDMMC1), 0, GATE_SDMMC1), + STM32_GATE(_SDMMC2_K, SDMMC2_K, MUX(MUX_SDMMC2), 0, GATE_SDMMC2), + STM32_GATE(_DBGCK, CK_DBG, _CKAXI, 0, GATE_DBGCK), + +/* TODO: CHECK CLOCK FOR BL2/BL32 AND IF ONLY FOR TEST OR NOT */ + STM32_GATE(_USART3_K, USART3_K, MUX(MUX_UART35), 0, GATE_USART3), + STM32_GATE(_UART4_K, UART4_K, MUX(MUX_UART4), 0, GATE_UART4), + STM32_GATE(_UART5_K, UART5_K, MUX(MUX_UART35), 0, GATE_UART5), + STM32_GATE(_UART7_K, UART7_K, MUX(MUX_UART78), 0, GATE_UART7), + STM32_GATE(_UART8_K, UART8_K, MUX(MUX_UART78), 0, GATE_UART8), + STM32_GATE(_USART6_K, USART6_K, MUX(MUX_UART6), 0, GATE_USART6), + STM32_GATE(_MCE, MCE, _CKAXI, CLK_IS_CRITICAL, GATE_MCE), + STM32_GATE(_FMC_K, FMC_K, MUX(MUX_FMC), 0, GATE_FMC), + STM32_GATE(_QSPI_K, QSPI_K, MUX(MUX_QSPI), 0, GATE_QSPI), + + STM32_COMPOSITE(_MCO1_K, CK_MCO1, MUX(MUX_MCO1), 0, GATE_MCO1, DIV_MCO1), + STM32_COMPOSITE(_MCO2_K, CK_MCO2, MUX(MUX_MCO2), 0, GATE_MCO2, DIV_MCO2), + STM32_COMPOSITE(_TRACECK, CK_TRACE, _CKAXI, 0, GATE_TRACECK, DIV_TRACE), + +#if defined(IMAGE_BL32) + STM32_GATE(_TIM2, TIM2_K, _CKTIMG1, 0, GATE_TIM2), + STM32_GATE(_TIM3, TIM3_K, _CKTIMG1, 0, GATE_TIM3), + STM32_GATE(_TIM4, TIM4_K, _CKTIMG1, 0, GATE_TIM4), + STM32_GATE(_TIM5, TIM5_K, _CKTIMG1, 0, GATE_TIM5), + STM32_GATE(_TIM6, TIM6_K, _CKTIMG1, 0, GATE_TIM6), + STM32_GATE(_TIM7, TIM7_K, _CKTIMG1, 0, GATE_TIM7), + STM32_GATE(_TIM13, TIM13_K, _CKTIMG3, 0, GATE_TIM13), + STM32_GATE(_TIM14, TIM14_K, _CKTIMG3, 0, GATE_TIM14), + STM32_GATE(_LPTIM1_K, LPTIM1_K, MUX(MUX_LPTIM1), 0, GATE_LPTIM1), + STM32_GATE(_SPI2_K, SPI2_K, MUX(MUX_SPI23), 0, GATE_SPI2), + STM32_GATE(_SPI3_K, SPI3_K, MUX(MUX_SPI23), 0, GATE_SPI3), + STM32_GATE(_SPDIF_K, SPDIF_K, MUX(MUX_SPDIF), 0, GATE_SPDIF), + STM32_GATE(_TIM1, TIM1_K, _CKTIMG2, 0, GATE_TIM1), + STM32_GATE(_TIM8, TIM8_K, _CKTIMG2, 0, GATE_TIM8), + STM32_GATE(_TIM16, TIM16_K, _CKTIMG3, 0, GATE_TIM16), + STM32_GATE(_TIM17, TIM17_K, _CKTIMG3, 0, GATE_TIM17), + STM32_GATE(_SPI1_K, SPI1_K, MUX(MUX_SPI1), 0, GATE_SPI1), + STM32_GATE(_SPI4_K, SPI4_K, MUX(MUX_SPI4), 0, GATE_SPI4), + STM32_GATE(_SPI5_K, SPI5_K, MUX(MUX_SPI5), 0, GATE_SPI5), + STM32_GATE(_SAI1_K, SAI1_K, MUX(MUX_SAI1), 0, GATE_SAI1), + STM32_GATE(_SAI2_K, SAI2_K, MUX(MUX_SAI2), 0, GATE_SAI2), + STM32_GATE(_DFSDM, DFSDM_K, MUX(MUX_SAI1), 0, GATE_DFSDM), + STM32_GATE(_FDCAN_K, FDCAN_K, MUX(MUX_FDCAN), 0, GATE_FDCAN), + STM32_GATE(_USBH, USBH, _CKAXI, 0, GATE_USBH), + STM32_GATE(_I2C1_K, I2C1_K, MUX(MUX_I2C12), 0, GATE_I2C1), + STM32_GATE(_I2C2_K, I2C2_K, MUX(MUX_I2C12), 0, GATE_I2C2), + STM32_GATE(_ADFSDM, ADFSDM_K, MUX(MUX_SAI1), 0, GATE_ADFSDM), + STM32_GATE(_LPTIM2_K, LPTIM2_K, MUX(MUX_LPTIM2), 0, GATE_LPTIM2), + STM32_GATE(_LPTIM3_K, LPTIM3_K, MUX(MUX_LPTIM3), 0, GATE_LPTIM3), + STM32_GATE(_LPTIM4_K, LPTIM4_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM4), + STM32_GATE(_LPTIM5_K, LPTIM5_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM5), + STM32_GATE(_VREF, VREF, _PCLK3, 0, GATE_VREF), + STM32_GATE(_DTS, TMPSENS, _PCLK3, 0, GATE_DTS), + STM32_GATE(_PMBCTRL, PMBCTRL, _PCLK3, 0, GATE_HDP), + STM32_GATE(_HDP, HDP, _PCLK3, 0, GATE_PMBCTRL), + STM32_GATE(_STGENRO, STGENRO, _PCLK4, 0, GATE_DCMIPP), + STM32_GATE(_DCMIPP_K, DCMIPP_K, MUX(MUX_DCMIPP), 0, GATE_DCMIPP), + STM32_GATE(_DMAMUX1, DMAMUX1, _CKAXI, 0, GATE_DMAMUX1), + STM32_GATE(_DMAMUX2, DMAMUX2, _CKAXI, 0, GATE_DMAMUX2), + STM32_GATE(_DMA3, DMA3, _CKAXI, 0, GATE_DMAMUX2), + STM32_GATE(_ADC1_K, ADC1_K, MUX(MUX_ADC1), 0, GATE_ADC1), + STM32_GATE(_ADC2_K, ADC2_K, MUX(MUX_ADC2), 0, GATE_ADC2), + STM32_GATE(_TSC, TSC, _CKAXI, 0, GATE_TSC), + STM32_GATE(_AXIMC, AXIMC, _CKAXI, 0, GATE_AXIMC), + STM32_GATE(_CRC1, CRC1, _CKAXI, 0, GATE_ETH1TX), + STM32_GATE(_ETH1CK, ETH1CK_K, MUX(MUX_ETH1), 0, GATE_ETH1CK), + STM32_GATE(_ETH1TX, ETH1TX, _CKAXI, 0, GATE_ETH1TX), + STM32_GATE(_ETH1RX, ETH1RX, _CKAXI, 0, GATE_ETH1RX), + STM32_GATE(_ETH2CK, ETH2CK_K, MUX(MUX_ETH2), 0, GATE_ETH2CK), + STM32_GATE(_ETH2TX, ETH2TX, _CKAXI, 0, GATE_ETH2TX), + STM32_GATE(_ETH2RX, ETH2RX, _CKAXI, 0, GATE_ETH2RX), + STM32_GATE(_ETH2MAC, ETH2MAC, _CKAXI, 0, GATE_ETH2MAC), +#endif +}; + +static struct stm32_pll_dt_cfg mp13_pll[_PLL_NB]; + +static struct stm32_osci_dt_cfg mp13_osci[NB_OSCILLATOR]; + +static uint32_t mp13_clksrc[MUX_MAX]; + +static uint32_t mp13_clkdiv[DIV_MAX]; + +static struct stm32_clk_platdata stm32mp13_clock_pdata = { + .osci = mp13_osci, + .nosci = NB_OSCILLATOR, + .pll = mp13_pll, + .npll = _PLL_NB, + .clksrc = mp13_clksrc, + .nclksrc = MUX_MAX, + .clkdiv = mp13_clkdiv, + .nclkdiv = DIV_MAX, +}; + +static struct stm32_clk_priv stm32mp13_clock_data = { + .base = RCC_BASE, + .num = ARRAY_SIZE(stm32mp13_clk), + .clks = stm32mp13_clk, + .parents = parent_mp13, + .nb_parents = ARRAY_SIZE(parent_mp13), + .gates = gates_mp13, + .nb_gates = ARRAY_SIZE(gates_mp13), + .div = dividers_mp13, + .nb_div = ARRAY_SIZE(dividers_mp13), + .osci_data = stm32mp13_osc_data, + .nb_osci_data = ARRAY_SIZE(stm32mp13_osc_data), + .gate_refcounts = refcounts_mp13, + .pdata = &stm32mp13_clock_pdata, +}; + +static int stm32mp1_init_clock_tree(void) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int ret; + +#if STM32MP_USB_PROGRAMMER + int usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K); + int usbo_p = _clk_stm32_get_parent(priv, _USBO_K); + + /* Don't initialize PLL4, when used by BOOTROM */ + pll4_bootrom = stm32mp1_clk_is_pll4_used_by_bootrom(priv, usbphy_p); +#endif + + /* + * Switch ON oscillators found in device-tree. + * Note: HSI already ON after BootROM stage. + */ + stm32_clk_oscillators_enable(priv); + + /* Come back to HSI */ + ret = stm32mp1_come_back_to_hsi(); + if (ret != 0) { + return ret; + } + + ret = stm32_clk_hsidiv_configure(priv); + if (ret != 0) { + return ret; + } + + ret = stm32_clk_stgen_configure(priv, _STGENC); + if (ret != 0) { + panic(); + } + + ret = stm32_clk_dividers_configure(priv); + if (ret != 0) { + panic(); + } + + ret = stm32_clk_pll_configure(priv); + if (ret != 0) { + panic(); + } + + /* Wait LSE ready before to use it */ + ret = stm32_clk_oscillators_wait_lse_ready(priv); + if (ret != 0) { + panic(); + } + + /* Configure with expected clock source */ + ret = stm32_clk_source_configure(priv); + if (ret != 0) { + panic(); + } + + /* Configure LSE css after RTC source configuration */ + ret = stm32_clk_oscillators_lse_set_css(priv); + if (ret != 0) { + panic(); + } + +#if STM32MP_USB_PROGRAMMER + ret = stm32mp1_clk_check_usb_conflict(priv, usbphy_p, usbo_p); + if (ret != 0) { + return ret; + } +#endif + /* reconfigure STGEN with DT config */ + ret = stm32_clk_stgen_configure(priv, _STGENC); + if (ret != 0) { + panic(); + } + + /* Software Self-Refresh mode (SSR) during DDR initilialization */ + mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, + RCC_DDRITFCR_DDRCKMOD_MASK, + RCC_DDRITFCR_DDRCKMOD_SSR << + RCC_DDRITFCR_DDRCKMOD_SHIFT); + + return 0; +} + +#define LSEDRV_MEDIUM_HIGH 2 + +static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name, + struct stm32_osci_dt_cfg *osci) +{ + int subnode = 0; + + /* default value oscillator not found, freq=0 */ + osci->freq = 0; + + fdt_for_each_subnode(subnode, fdt, node) { + const char *cchar = NULL; + const fdt32_t *cuint = NULL; + int ret = 0; + + cchar = fdt_get_name(fdt, subnode, &ret); + if (cchar == NULL) { + return ret; + } + + if (strncmp(cchar, name, (size_t)ret) || + fdt_get_status(subnode) == DT_DISABLED) { + continue; + } + + cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); + if (cuint == NULL) { + return ret; + } + + osci->freq = fdt32_to_cpu(*cuint); + + if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) { + osci->bypass = true; + } + + if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) { + osci->digbyp = true; + } + + if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) { + osci->css = true; + } + + osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH); + + return 0; + } + + return 0; +} + +static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata) +{ + int fdt_err = 0; + uint32_t i = 0; + int node = 0; + + node = fdt_path_offset(fdt, "/clocks"); + if (node < 0) { + return -FDT_ERR_NOTFOUND; + } + + for (i = 0; i < pdata->nosci; i++) { + const char *name = NULL; + + name = clk_stm32_get_oscillator_name((enum stm32_osc)i); + if (name == NULL) { + continue; + } + + fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]); + if (fdt_err < 0) { + panic(); + } + } + + return 0; +} + +#define RCC_PLL_NAME_SIZE 12 + +static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_vco *vco) +{ + int err = 0; + + err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, vco->div_mn); + if (err != 0) { + return err; + } + + err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLL_CSG_NB, vco->csg); + + vco->csg_enabled = (err == 0); + + if (err == -FDT_ERR_NOTFOUND) { + err = 0; + } + + if (err != 0) { + return err; + } + + vco->status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN | RCC_PLLNCR_PLLON; + + vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0); + + vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX); + + return 0; +} + +static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_output *output) +{ + int err = 0; + + err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB, + output->output); + if (err != 0) { + return err; + } + + return 0; +} + +static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) +{ + const fdt32_t *cuint = NULL; + int subnode_pll = 0; + int subnode_vco = 0; + int err = 0; + + cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); + if (!cuint) { + return -FDT_ERR_NOTFOUND; + } + + subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); + if (subnode_pll < 0) { + return -FDT_ERR_NOTFOUND; + } + + cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL); + if (!cuint) { + return -FDT_ERR_NOTFOUND; + } + + subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); + if (subnode_vco < 0) { + return -FDT_ERR_NOTFOUND; + } + + err = clk_stm32_load_vco_config(fdt, subnode_vco, &pll->vco); + if (err != 0) { + return err; + } + + err = clk_stm32_load_output_config(fdt, subnode_pll, &pll->output); + if (err != 0) { + return err; + } + + return 0; +} + +static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata) +{ + size_t i = 0U; + + for (i = _PLL1; i < pdata->npll; i++) { + struct stm32_pll_dt_cfg *pll = pdata->pll + i; + char name[RCC_PLL_NAME_SIZE]; + int subnode = 0; + int err = 0; + + snprintf(name, sizeof(name), "st,pll@%u", i); + + subnode = fdt_subnode_offset(fdt, node, name); + if (!fdt_check_node(subnode)) { + continue; + } + + err = clk_stm32_parse_pll_fdt(fdt, subnode, pll); + if (err != 0) { + panic(); + } + } + + return 0; +} + +static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata) +{ + void *fdt = NULL; + int node; + uint32_t err; + + if (fdt_get_address(&fdt) == 0) { + return -ENOENT; + } + + node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); + if (node < 0) { + panic(); + } + + err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata); + if (err != 0) { + return err; + } + + err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); + if (err != 0) { + return err; + } + + err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, &pdata->nclkdiv); + if (err != 0) { + return err; + } + + err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, &pdata->nclksrc); + if (err != 0) { + return err; + } + + return 0; +} + +int stm32mp1_clk_init(void) +{ + return 0; +} + +int stm32mp1_clk_probe(void) +{ + uintptr_t base = RCC_BASE; + int ret; + + ret = stm32_clk_parse_fdt(&stm32mp13_clock_pdata); + if (ret != 0) { + return ret; + } + + ret = clk_stm32_init(&stm32mp13_clock_data, base); + if (ret != 0) { + return ret; + } + + ret = stm32mp1_init_clock_tree(); + if (ret != 0) { + return ret; + } + + clk_stm32_enable_critical_clocks(); + + return 0; +} diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c index 3f709a763..40641b5a8 100644 --- a/drivers/st/mmc/stm32_sdmmc2.c +++ b/drivers/st/mmc/stm32_sdmmc2.c @@ -125,7 +125,9 @@ #define POWER_OFF_DELAY 2 #define POWER_ON_DELAY 1 +#ifndef DT_SDMMC2_COMPAT #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" +#endif static void stm32_sdmmc2_init(void); static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c index 7030cf5ce..5b4376041 100644 --- a/drivers/st/pmic/stm32mp_pmic.c +++ b/drivers/st/pmic/stm32mp_pmic.c @@ -219,17 +219,20 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) { int status; uint16_t buck3_min_mv; - struct rdev *buck2, *buck3, *ldo3, *vref; + struct rdev *buck2, *buck3, *vref; + struct rdev *ldo3 __unused; buck2 = regulator_get_by_name("buck2"); if (buck2 == NULL) { return -ENOENT; } +#if STM32MP15 ldo3 = regulator_get_by_name("ldo3"); if (ldo3 == NULL) { return -ENOENT; } +#endif vref = regulator_get_by_name("vref_ddr"); if (vref == NULL) { @@ -238,10 +241,12 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) switch (ddr_type) { case STM32MP_DDR3: +#if STM32MP15 status = regulator_set_flag(ldo3, REGUL_SINK_SOURCE); if (status != 0) { return status; } +#endif status = regulator_set_min_voltage(buck2); if (status != 0) { @@ -258,10 +263,12 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) return status; } +#if STM32MP15 status = regulator_enable(ldo3); if (status != 0) { return status; } +#endif break; case STM32MP_LPDDR2: @@ -278,6 +285,7 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) regulator_get_range(buck3, &buck3_min_mv, NULL); +#if STM32MP15 if (buck3_min_mv != 1800) { status = regulator_set_min_voltage(ldo3); if (status != 0) { @@ -289,16 +297,19 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) return status; } } +#endif status = regulator_set_min_voltage(buck2); if (status != 0) { return status; } +#if STM32MP15 status = regulator_enable(ldo3); if (status != 0) { return status; } +#endif status = regulator_enable(buck2); if (status != 0) { @@ -318,6 +329,36 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) return 0; } +int pmic_voltages_init(void) +{ +#if STM32MP13 + struct rdev *buck1, *buck4; + int status; + + buck1 = regulator_get_by_name("buck1"); + if (buck1 == NULL) { + return -ENOENT; + } + + buck4 = regulator_get_by_name("buck4"); + if (buck4 == NULL) { + return -ENOENT; + } + + status = regulator_set_min_voltage(buck1); + if (status != 0) { + return status; + } + + status = regulator_set_min_voltage(buck4); + if (status != 0) { + return status; + } +#endif + + return 0; +} + enum { STPMIC1_BUCK1 = 0, STPMIC1_BUCK2, diff --git a/fdts/stm32mp13-bl2.dtsi b/fdts/stm32mp13-bl2.dtsi new file mode 100644 index 000000000..41d6e2e88 --- /dev/null +++ b/fdts/stm32mp13-bl2.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + */ + +/ { + aliases { +#if !STM32MP_EMMC && !STM32MP_SDMMC + /delete-property/ mmc0; + /delete-property/ mmc1; +#endif + /delete-property/ ethernet0; + /delete-property/ ethernet1; + }; + + cpus { + cpu@0 { + /delete-property/ operating-points-v2; + }; + }; + + /delete-node/ cpu0-opp-table; + /delete-node/ psci; + + soc { + /delete-node/ sram@30000000; + /delete-node/ timer@40000000; + /delete-node/ timer@40001000; + /delete-node/ timer@40002000; + /delete-node/ timer@40003000; + /delete-node/ timer@40004000; + /delete-node/ timer@40005000; + /delete-node/ timer@40009000; + /delete-node/ spi@4000b000; + /delete-node/ audio-controller@4000b000; + /delete-node/ spi@4000c000; + /delete-node/ audio-controller@4000c000; + /delete-node/ audio-controller@4000d000; + /delete-node/ i2c@40012000; + /delete-node/ i2c@40013000; + /delete-node/ timer@44000000; + /delete-node/ timer@44001000; + /delete-node/ spi@44004000; + /delete-node/ audio-controller@44004000; + /delete-node/ sai@4400a000; + /delete-node/ sai@4400b000; + /delete-node/ dfsdm@4400d000; + /delete-node/ can@4400e000; + /delete-node/ can@4400f000; + /delete-node/ dma-controller@48000000; + /delete-node/ dma-controller@48001000; + /delete-node/ dma-router@48002000; + /delete-node/ adc@48003000; + /delete-node/ adc@48004000; + /delete-node/ dma@48005000; + /delete-node/ dma-router@48006000; +#if !STM32MP_USB_PROGRAMMER + /delete-node/ usb-otg@49000000; +#endif + /delete-node/ spi@4c002000; + /delete-node/ spi@4c003000; + /delete-node/ timer@4c007000; + /delete-node/ timer@4c008000; + /delete-node/ timer@4c009000; + /delete-node/ timer@4c00a000; + /delete-node/ timer@4c00b000; + /delete-node/ timer@4c00c000; + /delete-node/ timer@50021000; + /delete-node/ timer@50022000; + /delete-node/ timer@50023000; + /delete-node/ timer@50024000; + /delete-node/ vrefbuf@50025000; + /delete-node/ thermal@50028000; + /delete-node/ hdp@5002a000; + /delete-node/ dma-controller@58000000; +#if !STM32MP_RAW_NAND + /delete-node/ memory-controller@58002000; +#endif +#if !STM32MP_SPI_NAND && !STM32MP_SPI_NOR + /delete-node/ spi@58003000; +#endif +#if !STM32MP_EMMC && !STM32MP_SDMMC + /delete-node/ mmc@58005000; + /delete-node/ mmc@58007000; +#endif + /delete-node/ crc@58009000; + /delete-node/ stmmac-axi-config; + /delete-node/ eth1@5800a000; +#if !STM32MP_USB_PROGRAMMER + /delete-node/ usbh-ohci@5800c000; + /delete-node/ usbh-ehci@5800d000; +#endif + /delete-node/ eth2@5800e000; + /delete-node/ dcmipp@5a000000; + /delete-node/ display-controller@5a001000; +#if !STM32MP_USB_PROGRAMMER + /delete-node/ usbphyc@5a006000; +#endif + /delete-node/ perf@5a007000; + /delete-node/ rtc@5c004000; + /delete-node/ tamp@5c00a000; + /delete-node/ stgen@5c008000; + + pin-controller@50002000 { +#if !STM32MP_EMMC && !STM32MP_SDMMC + /delete-node/ sdmmc1-b4-0; + /delete-node/ sdmmc2-b4-0; +#endif + }; + }; + + /* + * UUID's here are UUID RFC 4122 compliant meaning fieds are stored in + * network order (big endian) + */ + + st-io_policies { + fip-handles { + compatible = "st,io-fip-handle"; + fw_cfg_uuid = "5807e16a-8459-47be-8ed5-648e8dddab0e"; + bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38"; + bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288"; + bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9"; + bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4"; + hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc"; + tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021"; + nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9"; + }; + }; +}; diff --git a/fdts/stm32mp13-ddr.dtsi b/fdts/stm32mp13-ddr.dtsi new file mode 100644 index 000000000..56eb36e86 --- /dev/null +++ b/fdts/stm32mp13-ddr.dtsi @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +&ddr { + st,mem-name = DDR_MEM_NAME; + st,mem-speed = ; + st,mem-size = ; + + st,ctl-reg = < + DDR_MSTR + DDR_MRCTRL0 + DDR_MRCTRL1 + DDR_DERATEEN + DDR_DERATEINT + DDR_PWRCTL + DDR_PWRTMG + DDR_HWLPCTL + DDR_RFSHCTL0 + DDR_RFSHCTL3 + DDR_CRCPARCTL0 + DDR_ZQCTL0 + DDR_DFITMG0 + DDR_DFITMG1 + DDR_DFILPCFG0 + DDR_DFIUPD0 + DDR_DFIUPD1 + DDR_DFIUPD2 + DDR_DFIPHYMSTR + DDR_ODTMAP + DDR_DBG0 + DDR_DBG1 + DDR_DBGCMD + DDR_POISONCFG + DDR_PCCFG + >; + + st,ctl-timing = < + DDR_RFSHTMG + DDR_DRAMTMG0 + DDR_DRAMTMG1 + DDR_DRAMTMG2 + DDR_DRAMTMG3 + DDR_DRAMTMG4 + DDR_DRAMTMG5 + DDR_DRAMTMG6 + DDR_DRAMTMG7 + DDR_DRAMTMG8 + DDR_DRAMTMG14 + DDR_ODTCFG + >; + + st,ctl-map = < + DDR_ADDRMAP1 + DDR_ADDRMAP2 + DDR_ADDRMAP3 + DDR_ADDRMAP4 + DDR_ADDRMAP5 + DDR_ADDRMAP6 + DDR_ADDRMAP9 + DDR_ADDRMAP10 + DDR_ADDRMAP11 + >; + + st,ctl-perf = < + DDR_SCHED + DDR_SCHED1 + DDR_PERFHPR1 + DDR_PERFLPR1 + DDR_PERFWR1 + DDR_PCFGR_0 + DDR_PCFGW_0 + DDR_PCFGQOS0_0 + DDR_PCFGQOS1_0 + DDR_PCFGWQOS0_0 + DDR_PCFGWQOS1_0 + >; + + st,phy-reg = < + DDR_PGCR + DDR_ACIOCR + DDR_DXCCR + DDR_DSGCR + DDR_DCR + DDR_ODTCR + DDR_ZQ0CR1 + DDR_DX0GCR + DDR_DX1GCR + >; + + st,phy-timing = < + DDR_PTR0 + DDR_PTR1 + DDR_PTR2 + DDR_DTPR0 + DDR_DTPR1 + DDR_DTPR2 + DDR_MR0 + DDR_MR1 + DDR_MR2 + DDR_MR3 + >; +}; + +#undef DDR_MEM_NAME +#undef DDR_MEM_SPEED +#undef DDR_MEM_SIZE +#undef DDR_MSTR +#undef DDR_MRCTRL0 +#undef DDR_MRCTRL1 +#undef DDR_DERATEEN +#undef DDR_DERATEINT +#undef DDR_PWRCTL +#undef DDR_PWRTMG +#undef DDR_HWLPCTL +#undef DDR_RFSHCTL0 +#undef DDR_RFSHCTL3 +#undef DDR_RFSHTMG +#undef DDR_CRCPARCTL0 +#undef DDR_DRAMTMG0 +#undef DDR_DRAMTMG1 +#undef DDR_DRAMTMG2 +#undef DDR_DRAMTMG3 +#undef DDR_DRAMTMG4 +#undef DDR_DRAMTMG5 +#undef DDR_DRAMTMG6 +#undef DDR_DRAMTMG7 +#undef DDR_DRAMTMG8 +#undef DDR_DRAMTMG14 +#undef DDR_ZQCTL0 +#undef DDR_DFITMG0 +#undef DDR_DFITMG1 +#undef DDR_DFILPCFG0 +#undef DDR_DFIUPD0 +#undef DDR_DFIUPD1 +#undef DDR_DFIUPD2 +#undef DDR_DFIPHYMSTR +#undef DDR_ADDRMAP1 +#undef DDR_ADDRMAP2 +#undef DDR_ADDRMAP3 +#undef DDR_ADDRMAP4 +#undef DDR_ADDRMAP5 +#undef DDR_ADDRMAP6 +#undef DDR_ADDRMAP9 +#undef DDR_ADDRMAP10 +#undef DDR_ADDRMAP11 +#undef DDR_ODTCFG +#undef DDR_ODTMAP +#undef DDR_SCHED +#undef DDR_SCHED1 +#undef DDR_PERFHPR1 +#undef DDR_PERFLPR1 +#undef DDR_PERFWR1 +#undef DDR_DBG0 +#undef DDR_DBG1 +#undef DDR_DBGCMD +#undef DDR_POISONCFG +#undef DDR_PCCFG +#undef DDR_PCFGR_0 +#undef DDR_PCFGW_0 +#undef DDR_PCFGQOS0_0 +#undef DDR_PCFGQOS1_0 +#undef DDR_PCFGWQOS0_0 +#undef DDR_PCFGWQOS1_0 +#undef DDR_PGCR +#undef DDR_PTR0 +#undef DDR_PTR1 +#undef DDR_PTR2 +#undef DDR_ACIOCR +#undef DDR_DXCCR +#undef DDR_DSGCR +#undef DDR_DCR +#undef DDR_DTPR0 +#undef DDR_DTPR1 +#undef DDR_DTPR2 +#undef DDR_MR0 +#undef DDR_MR1 +#undef DDR_MR2 +#undef DDR_MR3 +#undef DDR_ODTCR +#undef DDR_ZQ0CR1 +#undef DDR_DX0GCR +#undef DDR_DX1GCR diff --git a/fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi b/fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi new file mode 100644 index 000000000..a5f7989f4 --- /dev/null +++ b/fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * STM32MP135C DISCO BOARD configuration + * 1x DDR3L 4Gb, 16-bit, 533MHz. + * Reference used MT41K256M16TW-107 P from Micron + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 16 + * datasheet 1 + * DDR density 4 + * timing mode optimized + * Scheduling/QoS options : type = 6 + * address mapping : RBC + * Tc > + 85C : N + */ +#define DDR_MEM_NAME "DDR3-1066 bin F 1x4Gb 533MHz v1.53" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x20000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041B +#define DDR_DRAMTMG2 0x0607080F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x07040607 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02050105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x0F070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000F01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x00000001 +#define DDR_PERFLPR1 0x04000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00000000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x00100009 +#define DDR_PCFGQOS1_0 0x00000020 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x36D477D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000830 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX1GCR 0x0000CE81 + +#include "stm32mp13-ddr.dtsi" diff --git a/fdts/stm32mp13-fw-config.dtsi b/fdts/stm32mp13-fw-config.dtsi new file mode 100644 index 000000000..dc8ca1b43 --- /dev/null +++ b/fdts/stm32mp13-fw-config.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + */ + +#include +#include + +#include + +#ifndef DDR_SIZE +#error "DDR_SIZE is not defined" +#endif + +#define DDR_NS_BASE STM32MP_DDR_BASE +#define DDR_SEC_SIZE 0x01e00000 +#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE)) +#define DDR_SHARE_SIZE 0x00200000 +#define DDR_SHARE_BASE (DDR_SEC_BASE - DDR_SHARE_SIZE) +#define DDR_NS_SIZE (DDR_SHARE_BASE - DDR_NS_BASE) + +/dts-v1/; + +/ { + dtb-registry { + compatible = "fconf,dyn_cfg-dtb_registry"; + + hw-config { + load-address = <0x0 STM32MP_HW_CONFIG_BASE>; + max-size = ; + id = ; + }; + + nt_fw { + load-address = <0x0 STM32MP_BL33_BASE>; + max-size = ; + id = ; + }; + + tos_fw { + load-address = <0x0 DDR_SEC_BASE>; + max-size = ; + id = ; + }; + }; + + st-mem-firewall { + compatible = "st,mem-firewall"; + memory-ranges = < + DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR + DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) + DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0>; + }; +}; diff --git a/fdts/stm32mp13-pinctrl.dtsi b/fdts/stm32mp13-pinctrl.dtsi new file mode 100644 index 000000000..0ad06a4e1 --- /dev/null +++ b/fdts/stm32mp13-pinctrl.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue + */ +#include + +&pinctrl { + i2c4_pins_a: i2c4-0 { + pins { + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + uart4_pins_a: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART1_RX */ + ; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = ; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; +}; diff --git a/fdts/stm32mp131.dtsi b/fdts/stm32mp131.dtsi new file mode 100644 index 000000000..dff1b33d8 --- /dev/null +++ b/fdts/stm32mp131.dtsi @@ -0,0 +1,621 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&rcc CK_MPU>; + clock-names = "cpu"; + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + }; + }; + + nvmem_layout: nvmem_layout@0 { + compatible = "st,stm32-nvmem-layout"; + + nvmem-cells = <&cfg0_otp>, + <&part_number_otp>, + <&monotonic_otp>, + <&nand_otp>, + <&nand2_otp>, + <&uid_otp>, + <&hw2_otp>; + + nvmem-cell-names = "cfg0_otp", + "part_number_otp", + "monotonic_otp", + "nand_otp", + "nand2_otp", + "uid_otp", + "hw2_otp"; + }; + + clocks { + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + }; + + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts = ; + clocks = <&rcc USART3_K>; + resets = <&rcc USART3_R>; + status = "disabled"; + }; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts = ; + clocks = <&rcc UART4_K>; + resets = <&rcc UART4_R>; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts = ; + clocks = <&rcc UART5_K>; + resets = <&rcc UART5_R>; + status = "disabled"; + }; + + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts = ; + clocks = <&rcc UART7_K>; + resets = <&rcc UART7_R>; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts = ; + clocks = <&rcc UART8_K>; + resets = <&rcc UART8_R>; + status = "disabled"; + }; + + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts = ; + clocks = <&rcc USART6_K>; + resets = <&rcc USART6_R>; + status = "disabled"; + }; + + usbotg_hs: usb-otg@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts = ; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts = ; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + + rcc: rcc@50000000 { + compatible = "st,stm32mp13-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + #reset-cells = <1>; + interrupts = ; + secure-interrupts = ; + secure-interrupt-names = "wakeup"; + }; + + pwr_regulators: pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>; + + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; + }; + + vrefbuf: vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; + status = "disabled"; + }; + + hash: hash@54003000 { + compatible = "st,stm32mp13-hash"; + reg = <0x54003000 0x400>; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + status = "disabled"; + }; + + rng: rng@54004000 { + compatible = "st,stm32mp13-rng"; + reg = <0x54004000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + status = "disabled"; + }; + + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = ; + status = "disabled"; + }; + }; + + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = ; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; + }; + + usbh_ohci: usbh-ohci@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; + }; + + usbh_ehci: usbh-ehci@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; + status = "disabled"; + }; + + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + + ddr: ddr@5a003000{ + compatible = "st,stm32mp13-ddr"; + reg = <0x5a003000 0x550>, <0x5a004000 0x234>; + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + clock-names = "axidcg", + "ddrc1", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + }; + + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + + iwdg1: watchdog@5c003000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5c003000 0x400>; + interrupts = ; + clocks = <&rcc IWDG1>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + + bsec: efuse@5c005000 { + compatible = "st,stm32mp15-bsec"; + reg = <0x5c005000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + cfg0_otp: cfg0_otp@0 { + reg = <0x0 0x2>; + }; + part_number_otp: part_number_otp@4 { + reg = <0x4 0x2>; + }; + monotonic_otp: monotonic_otp@10 { + reg = <0x10 0x4>; + }; + nand_otp: cfg9_otp@24 { + reg = <0x24 0x4>; + }; + nand2_otp: cfg10_otp@28 { + reg = <0x28 0x4>; + }; + uid_otp: uid_otp@34 { + reg = <0x34 0xc>; + }; + hw2_otp: hw2_otp@48 { + reg = <0x48 0x4>; + }; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; + pkh_otp: pkh_otp@60 { + reg = <0x60 0x20>; + }; + mac_addr: mac_addr@e4 { + reg = <0xe4 0xc>; + st,non-secure-otp; + }; + }; + + tamp: tamp@5c00a000 { + reg = <0x5c00a000 0x400>; + }; + + /* + * Break node order to solve dependency probe issue between + * pinctrl and exti. + */ + pinctrl: pin-controller@50002000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp135-pinctrl"; + ranges = <0 0x50002000 0x8400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; + pins-are-numbered; + + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA>; + st,bank-name = "GPIOA"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOB>; + st,bank-name = "GPIOB"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOC>; + st,bank-name = "GPIOC"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&rcc GPIOD>; + st,bank-name = "GPIOD"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&rcc GPIOE>; + st,bank-name = "GPIOE"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&rcc GPIOF>; + st,bank-name = "GPIOF"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&rcc GPIOG>; + st,bank-name = "GPIOG"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&rcc GPIOH>; + st,bank-name = "GPIOH"; + ngpios = <15>; + gpio-ranges = <&pinctrl 0 112 15>; + }; + + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&rcc GPIOI>; + st,bank-name = "GPIOI"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 128 8>; + }; + }; + }; +}; diff --git a/fdts/stm32mp133.dtsi b/fdts/stm32mp133.dtsi new file mode 100644 index 000000000..8bbcc6154 --- /dev/null +++ b/fdts/stm32mp133.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp131.dtsi" + +/ { + soc { + m_can1: can@4400e000 { + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + status = "disabled"; + }; + + m_can2: can@4400f000 { + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + status = "disabled"; + }; + }; +}; diff --git a/fdts/stm32mp135.dtsi b/fdts/stm32mp135.dtsi new file mode 100644 index 000000000..415bb9b59 --- /dev/null +++ b/fdts/stm32mp135.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp133.dtsi" + +/ { + soc { + }; +}; diff --git a/fdts/stm32mp135f-dk-fw-config.dts b/fdts/stm32mp135f-dk-fw-config.dts new file mode 100644 index 000000000..21f82422b --- /dev/null +++ b/fdts/stm32mp135f-dk-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x20000000 /* 512MB */ +#include "stm32mp13-fw-config.dtsi" diff --git a/fdts/stm32mp135f-dk.dts b/fdts/stm32mp135f-dk.dts new file mode 100644 index 000000000..0fa064b7a --- /dev/null +++ b/fdts/stm32mp135f-dk.dts @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13-ddr3-1x4Gb-1066-binF.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP135F-DK Discovery Board"; + compatible = "st,stm32mp135f-dk", "st,stm32mp135"; + + aliases { + serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + v3v3_ao: v3v3_ao { + compatible = "regulator-fixed"; + regulator-name = "v3v3_ao"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&bsec { + board_id: board_id@f0 { + reg = <0xf0 0x4>; + st,non-secure-otp; + }; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; +}; + +&hash { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + status = "disabled"; + secure-status = "okay"; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + + status = "disabled"; + secure-status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&vin>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&vin>; + vref_ddr-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&v3v3_ao>; + + vddcpu: buck1 { + regulator-name = "vddcpu"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-over-current-protection; + }; + + vddcore: buck4 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_adc: ldo1 { + regulator-name = "vdd_adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + v1v8_periph: ldo6 { + regulator-name = "v1v8_periph"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + }; + + v3v3_sw: pwr_sw2 { + regulator-name = "v3v3_sw"; + regulator-active-discharge = <1>; + regulator-always-on; + }; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&nvmem_layout { + nvmem-cells = <&cfg0_otp>, + <&part_number_otp>, + <&monotonic_otp>, + <&nand_otp>, + <&nand2_otp>, + <&uid_otp>, + <&hw2_otp>, + <&pkh_otp>, + <&board_id>; + + nvmem-cell-names = "cfg0_otp", + "part_number_otp", + "monotonic_otp", + "nand_otp", + "nand2_otp", + "uid_otp", + "hw2_otp", + "pkh_otp", + "board_id"; +}; + +&pka { + secure-status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rcc { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MLAHBS_PLL3 + CLK_CKPER_HSE + CLK_RTC_LSE + CLK_SDMMC1_PLL4P + CLK_SDMMC2_PLL4P + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_I2C4_HSI + CLK_USBO_USBPHY + CLK_I2C12_HSI + CLK_UART2_HSI + CLK_UART4_HSI + CLK_SAES_AXI + >; + + st,clkdiv = < + DIV(DIV_AXI, 0) + DIV(DIV_MLAHB, 0) + DIV(DIV_APB1, 1) + DIV(DIV_APB2, 1) + DIV(DIV_APB3, 1) + DIV(DIV_APB4, 1) + DIV(DIV_APB5, 2) + DIV(DIV_APB6, 1) + DIV(DIV_RTC, 0) + >; + + st,pll_vco { + pll1_vco_1300Mhz: pll1-vco-1300Mhz { + src = < CLK_PLL12_HSE >; + divmn = < 2 80 >; + frac = < 0x800 >; + }; + + pll2_vco_1066Mhz: pll2-vco-1066Mhz { + src = < CLK_PLL12_HSE >; + divmn = < 2 65 >; + frac = < 0x1400 >; + }; + + pll3_vco_417_8Mhz: pll2-vco-417_8Mhz { + src = < CLK_PLL3_HSE >; + divmn = < 1 33 >; + frac = < 0x1a04 >; + }; + + pll4_vco_600Mhz: pll2-vco-600Mhz { + src = < CLK_PLL4_HSE >; + divmn = < 1 49 >; + }; + }; + + /* VCO = 1300.0 MHz => P = 650 (CPU) */ + pll1:st,pll@0 { + compatible = "st,stm32mp1-pll"; + reg = <0>; + + st,pll = < &pll1_cfg1 >; + + pll1_cfg1: pll1_cfg1 { + st,pll_vco = < &pll1_vco_1300Mhz >; + st,pll_div_pqr = < 0 1 1 >; + }; + }; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ + pll2:st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + + st,pll = < &pll2_cfg1 >; + + pll2_cfg1: pll2_cfg1 { + st,pll_vco = < &pll2_vco_1066Mhz >; + st,pll_div_pqr = < 1 1 0 >; + }; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 209 */ + pll3:st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + + st,pll = < &pll3_cfg1 >; + + pll3_cfg1: pll3_cfg1 { + st,pll_vco = < &pll3_vco_417_8Mhz >; + st,pll_div_pqr = < 1 16 1 >; + }; + }; + + /* VCO = 600.0 MHz => P = 50, Q = 10, R = 100 */ + pll4:st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + + st,pll = < &pll4_cfg1 >; + + pll4_cfg1: pll4_cfg1 { + st,pll_vco = < &pll4_vco_600Mhz >; + st,pll_div_pqr = < 11 59 5 >; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&saes { + secure-status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "disabled"; +}; + +&usart1 { + pinctrl-names = "default"; + pinctrl-0 = <&usart1_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; diff --git a/fdts/stm32mp13xa.dtsi b/fdts/stm32mp13xa.dtsi new file mode 100644 index 000000000..0ef2fce99 --- /dev/null +++ b/fdts/stm32mp13xa.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ diff --git a/fdts/stm32mp13xc.dtsi b/fdts/stm32mp13xc.dtsi new file mode 100644 index 000000000..c03bd43a3 --- /dev/null +++ b/fdts/stm32mp13xc.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp13xa.dtsi" + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + + saes: saes@54005000 { + compatible = "st,stm32-saes"; + reg = <0x54005000 0x400>; + clocks = <&rcc SAES_K>; + resets = <&rcc SAES_R>; + status = "disabled"; + }; + + pka: pka@54006000 { + compatible = "st,stm32-pka64"; + reg = <0x54006000 0x2000>; + clocks = <&rcc PKA>; + resets = <&rcc PKA_R>; + status = "disabled"; + }; + }; +}; diff --git a/fdts/stm32mp13xd.dtsi b/fdts/stm32mp13xd.dtsi new file mode 100644 index 000000000..0ef2fce99 --- /dev/null +++ b/fdts/stm32mp13xd.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ diff --git a/fdts/stm32mp13xf.dtsi b/fdts/stm32mp13xf.dtsi new file mode 100644 index 000000000..e467d71af --- /dev/null +++ b/fdts/stm32mp13xf.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp13xd.dtsi" + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + + saes: saes@54005000 { + compatible = "st,stm32-saes"; + reg = <0x54005000 0x400>; + clocks = <&rcc SAES_K>; + resets = <&rcc SAES_R>; + status = "disabled"; + }; + + pka: pka@54006000 { + compatible = "st,stm32-pka64"; + reg = <0x54006000 0x2000>; + clocks = <&rcc PKA>; + resets = <&rcc PKA_R>; + status = "disabled"; + }; + }; +}; diff --git a/include/drivers/st/stm32mp13_rcc.h b/include/drivers/st/stm32mp13_rcc.h new file mode 100644 index 000000000..1451c9a12 --- /dev/null +++ b/include/drivers/st/stm32mp13_rcc.h @@ -0,0 +1,1878 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP13_RCC_H +#define STM32MP13_RCC_H + +#include + +#define RCC_SECCFGR U(0X0) +#define RCC_MP_SREQSETR U(0X100) +#define RCC_MP_SREQCLRR U(0X104) +#define RCC_MP_APRSTCR U(0X108) +#define RCC_MP_APRSTSR U(0X10C) +#define RCC_PWRLPDLYCR U(0X110) +#define RCC_MP_GRSTCSETR U(0X114) +#define RCC_BR_RSTSCLRR U(0X118) +#define RCC_MP_RSTSSETR U(0X11C) +#define RCC_MP_RSTSCLRR U(0X120) +#define RCC_MP_IWDGFZSETR U(0X124) +#define RCC_MP_IWDGFZCLRR U(0X128) +#define RCC_MP_CIER U(0X200) +#define RCC_MP_CIFR U(0X204) +#define RCC_BDCR U(0X400) +#define RCC_RDLSICR U(0X404) +#define RCC_OCENSETR U(0X420) +#define RCC_OCENCLRR U(0X424) +#define RCC_OCRDYR U(0X428) +#define RCC_HSICFGR U(0X440) +#define RCC_CSICFGR U(0X444) +#define RCC_MCO1CFGR U(0X460) +#define RCC_MCO2CFGR U(0X464) +#define RCC_DBGCFGR U(0X468) +#define RCC_RCK12SELR U(0X480) +#define RCC_RCK3SELR U(0X484) +#define RCC_RCK4SELR U(0X488) +#define RCC_PLL1CR U(0X4A0) +#define RCC_PLL1CFGR1 U(0X4A4) +#define RCC_PLL1CFGR2 U(0X4A8) +#define RCC_PLL1FRACR U(0X4AC) +#define RCC_PLL1CSGR U(0X4B0) +#define RCC_PLL2CR U(0X4D0) +#define RCC_PLL2CFGR1 U(0X4D4) +#define RCC_PLL2CFGR2 U(0X4D8) +#define RCC_PLL2FRACR U(0X4DC) +#define RCC_PLL2CSGR U(0X4E0) +#define RCC_PLL3CR U(0X500) +#define RCC_PLL3CFGR1 U(0X504) +#define RCC_PLL3CFGR2 U(0X508) +#define RCC_PLL3FRACR U(0X50C) +#define RCC_PLL3CSGR U(0X510) +#define RCC_PLL4CR U(0X520) +#define RCC_PLL4CFGR1 U(0X524) +#define RCC_PLL4CFGR2 U(0X528) +#define RCC_PLL4FRACR U(0X52C) +#define RCC_PLL4CSGR U(0X530) +#define RCC_MPCKSELR U(0X540) +#define RCC_ASSCKSELR U(0X544) +#define RCC_MSSCKSELR U(0X548) +#define RCC_CPERCKSELR U(0X54C) +#define RCC_RTCDIVR U(0X560) +#define RCC_MPCKDIVR U(0X564) +#define RCC_AXIDIVR U(0X568) +#define RCC_MLAHBDIVR U(0X56C) +#define RCC_APB1DIVR U(0X570) +#define RCC_APB2DIVR U(0X574) +#define RCC_APB3DIVR U(0X578) +#define RCC_APB4DIVR U(0X57C) +#define RCC_APB5DIVR U(0X580) +#define RCC_APB6DIVR U(0X584) +#define RCC_TIMG1PRER U(0X5A0) +#define RCC_TIMG2PRER U(0X5A4) +#define RCC_TIMG3PRER U(0X5A8) +#define RCC_DDRITFCR U(0X5C0) +#define RCC_I2C12CKSELR U(0X600) +#define RCC_I2C345CKSELR U(0X604) +#define RCC_SPI2S1CKSELR U(0X608) +#define RCC_SPI2S23CKSELR U(0X60C) +#define RCC_SPI45CKSELR U(0X610) +#define RCC_UART12CKSELR U(0X614) +#define RCC_UART35CKSELR U(0X618) +#define RCC_UART4CKSELR U(0X61C) +#define RCC_UART6CKSELR U(0X620) +#define RCC_UART78CKSELR U(0X624) +#define RCC_LPTIM1CKSELR U(0X628) +#define RCC_LPTIM23CKSELR U(0X62C) +#define RCC_LPTIM45CKSELR U(0X630) +#define RCC_SAI1CKSELR U(0X634) +#define RCC_SAI2CKSELR U(0X638) +#define RCC_FDCANCKSELR U(0X63C) +#define RCC_SPDIFCKSELR U(0X640) +#define RCC_ADC12CKSELR U(0X644) +#define RCC_SDMMC12CKSELR U(0X648) +#define RCC_ETH12CKSELR U(0X64C) +#define RCC_USBCKSELR U(0X650) +#define RCC_QSPICKSELR U(0X654) +#define RCC_FMCCKSELR U(0X658) +#define RCC_RNG1CKSELR U(0X65C) +#define RCC_STGENCKSELR U(0X660) +#define RCC_DCMIPPCKSELR U(0X664) +#define RCC_SAESCKSELR U(0X668) +#define RCC_APB1RSTSETR U(0X6A0) +#define RCC_APB1RSTCLRR U(0X6A4) +#define RCC_APB2RSTSETR U(0X6A8) +#define RCC_APB2RSTCLRR U(0X6AC) +#define RCC_APB3RSTSETR U(0X6B0) +#define RCC_APB3RSTCLRR U(0X6B4) +#define RCC_APB4RSTSETR U(0X6B8) +#define RCC_APB4RSTCLRR U(0X6BC) +#define RCC_APB5RSTSETR U(0X6C0) +#define RCC_APB5RSTCLRR U(0X6C4) +#define RCC_APB6RSTSETR U(0X6C8) +#define RCC_APB6RSTCLRR U(0X6CC) +#define RCC_AHB2RSTSETR U(0X6D0) +#define RCC_AHB2RSTCLRR U(0X6D4) +#define RCC_AHB4RSTSETR U(0X6E0) +#define RCC_AHB4RSTCLRR U(0X6E4) +#define RCC_AHB5RSTSETR U(0X6E8) +#define RCC_AHB5RSTCLRR U(0X6EC) +#define RCC_AHB6RSTSETR U(0X6F0) +#define RCC_AHB6RSTCLRR U(0X6F4) +#define RCC_MP_APB1ENSETR U(0X700) +#define RCC_MP_APB1ENCLRR U(0X704) +#define RCC_MP_APB2ENSETR U(0X708) +#define RCC_MP_APB2ENCLRR U(0X70C) +#define RCC_MP_APB3ENSETR U(0X710) +#define RCC_MP_APB3ENCLRR U(0X714) +#define RCC_MP_S_APB3ENSETR U(0X718) +#define RCC_MP_S_APB3ENCLRR U(0X71C) +#define RCC_MP_NS_APB3ENSETR U(0X720) +#define RCC_MP_NS_APB3ENCLRR U(0X724) +#define RCC_MP_APB4ENSETR U(0X728) +#define RCC_MP_APB4ENCLRR U(0X72C) +#define RCC_MP_S_APB4ENSETR U(0X730) +#define RCC_MP_S_APB4ENCLRR U(0X734) +#define RCC_MP_NS_APB4ENSETR U(0X738) +#define RCC_MP_NS_APB4ENCLRR U(0X73C) +#define RCC_MP_APB5ENSETR U(0X740) +#define RCC_MP_APB5ENCLRR U(0X744) +#define RCC_MP_APB6ENSETR U(0X748) +#define RCC_MP_APB6ENCLRR U(0X74C) +#define RCC_MP_AHB2ENSETR U(0X750) +#define RCC_MP_AHB2ENCLRR U(0X754) +#define RCC_MP_AHB4ENSETR U(0X760) +#define RCC_MP_AHB4ENCLRR U(0X764) +#define RCC_MP_S_AHB4ENSETR U(0X768) +#define RCC_MP_S_AHB4ENCLRR U(0X76C) +#define RCC_MP_NS_AHB4ENSETR U(0X770) +#define RCC_MP_NS_AHB4ENCLRR U(0X774) +#define RCC_MP_AHB5ENSETR U(0X778) +#define RCC_MP_AHB5ENCLRR U(0X77C) +#define RCC_MP_AHB6ENSETR U(0X780) +#define RCC_MP_AHB6ENCLRR U(0X784) +#define RCC_MP_S_AHB6ENSETR U(0X788) +#define RCC_MP_S_AHB6ENCLRR U(0X78C) +#define RCC_MP_NS_AHB6ENSETR U(0X790) +#define RCC_MP_NS_AHB6ENCLRR U(0X794) +#define RCC_MP_APB1LPENSETR U(0X800) +#define RCC_MP_APB1LPENCLRR U(0X804) +#define RCC_MP_APB2LPENSETR U(0X808) +#define RCC_MP_APB2LPENCLRR U(0X80C) +#define RCC_MP_APB3LPENSETR U(0X810) +#define RCC_MP_APB3LPENCLRR U(0X814) +#define RCC_MP_S_APB3LPENSETR U(0X818) +#define RCC_MP_S_APB3LPENCLRR U(0X81C) +#define RCC_MP_NS_APB3LPENSETR U(0X820) +#define RCC_MP_NS_APB3LPENCLRR U(0X824) +#define RCC_MP_APB4LPENSETR U(0X828) +#define RCC_MP_APB4LPENCLRR U(0X82C) +#define RCC_MP_S_APB4LPENSETR U(0X830) +#define RCC_MP_S_APB4LPENCLRR U(0X834) +#define RCC_MP_NS_APB4LPENSETR U(0X838) +#define RCC_MP_NS_APB4LPENCLRR U(0X83C) +#define RCC_MP_APB5LPENSETR U(0X840) +#define RCC_MP_APB5LPENCLRR U(0X844) +#define RCC_MP_APB6LPENSETR U(0X848) +#define RCC_MP_APB6LPENCLRR U(0X84C) +#define RCC_MP_AHB2LPENSETR U(0X850) +#define RCC_MP_AHB2LPENCLRR U(0X854) +#define RCC_MP_AHB4LPENSETR U(0X858) +#define RCC_MP_AHB4LPENCLRR U(0X85C) +#define RCC_MP_S_AHB4LPENSETR U(0X868) +#define RCC_MP_S_AHB4LPENCLRR U(0X86C) +#define RCC_MP_NS_AHB4LPENSETR U(0X870) +#define RCC_MP_NS_AHB4LPENCLRR U(0X874) +#define RCC_MP_AHB5LPENSETR U(0X878) +#define RCC_MP_AHB5LPENCLRR U(0X87C) +#define RCC_MP_AHB6LPENSETR U(0X880) +#define RCC_MP_AHB6LPENCLRR U(0X884) +#define RCC_MP_S_AHB6LPENSETR U(0X888) +#define RCC_MP_S_AHB6LPENCLRR U(0X88C) +#define RCC_MP_NS_AHB6LPENSETR U(0X890) +#define RCC_MP_NS_AHB6LPENCLRR U(0X894) +#define RCC_MP_S_AXIMLPENSETR U(0X898) +#define RCC_MP_S_AXIMLPENCLRR U(0X89C) +#define RCC_MP_NS_AXIMLPENSETR U(0X8A0) +#define RCC_MP_NS_AXIMLPENCLRR U(0X8A4) +#define RCC_MP_MLAHBLPENSETR U(0X8A8) +#define RCC_MP_MLAHBLPENCLRR U(0X8AC) +#define RCC_APB3SECSR U(0X8C0) +#define RCC_APB4SECSR U(0X8C4) +#define RCC_APB5SECSR U(0X8C8) +#define RCC_APB6SECSR U(0X8CC) +#define RCC_AHB2SECSR U(0X8D0) +#define RCC_AHB4SECSR U(0X8D4) +#define RCC_AHB5SECSR U(0X8D8) +#define RCC_AHB6SECSR U(0X8DC) +#define RCC_VERR U(0XFF4) +#define RCC_IDR U(0XFF8) +#define RCC_SIDR U(0XFFC) + +/* RCC_SECCFGR register fields */ +#define RCC_SECCFGR_HSISEC BIT(0) +#define RCC_SECCFGR_CSISEC BIT(1) +#define RCC_SECCFGR_HSESEC BIT(2) +#define RCC_SECCFGR_LSISEC BIT(3) +#define RCC_SECCFGR_LSESEC BIT(4) +#define RCC_SECCFGR_PLL12SEC BIT(8) +#define RCC_SECCFGR_PLL3SEC BIT(9) +#define RCC_SECCFGR_PLL4SEC BIT(10) +#define RCC_SECCFGR_MPUSEC BIT(11) +#define RCC_SECCFGR_AXISEC BIT(12) +#define RCC_SECCFGR_MLAHBSEC BIT(13) +#define RCC_SECCFGR_APB3DIVSEC BIT(16) +#define RCC_SECCFGR_APB4DIVSEC BIT(17) +#define RCC_SECCFGR_APB5DIVSEC BIT(18) +#define RCC_SECCFGR_APB6DIVSEC BIT(19) +#define RCC_SECCFGR_TIMG3SEC BIT(20) +#define RCC_SECCFGR_CPERSEC BIT(21) +#define RCC_SECCFGR_MCO1SEC BIT(22) +#define RCC_SECCFGR_MCO2SEC BIT(23) +#define RCC_SECCFGR_STPSEC BIT(24) +#define RCC_SECCFGR_RSTSEC BIT(25) +#define RCC_SECCFGR_PWRSEC BIT(31) + +/* RCC_MP_SREQSETR register fields */ +#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) + +/* RCC_MP_SREQCLRR register fields */ +#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) + +/* RCC_MP_APRSTCR register fields */ +#define RCC_MP_APRSTCR_RDCTLEN BIT(0) +#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) +#define RCC_MP_APRSTCR_RSTTO_SHIFT 8 + +/* RCC_MP_APRSTSR register fields */ +#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) +#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 + +/* RCC_PWRLPDLYCR register fields */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) +#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 + +/* RCC_MP_GRSTCSETR register fields */ +#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) + +/* RCC_BR_RSTSCLRR register fields */ +#define RCC_BR_RSTSCLRR_PORRSTF BIT(0) +#define RCC_BR_RSTSCLRR_BORRSTF BIT(1) +#define RCC_BR_RSTSCLRR_PADRSTF BIT(2) +#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_BR_RSTSCLRR_VCPURSTF BIT(5) +#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) + +/* RCC_MP_RSTSSETR register fields */ +#define RCC_MP_RSTSSETR_PORRSTF BIT(0) +#define RCC_MP_RSTSSETR_BORRSTF BIT(1) +#define RCC_MP_RSTSSETR_PADRSTF BIT(2) +#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSSETR_VCORERSTF BIT(4) +#define RCC_MP_RSTSSETR_VCPURSTF BIT(5) +#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSSETR_STP2RSTF BIT(10) +#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSSETR_SPARE BIT(15) + +/* RCC_MP_RSTSCLRR register fields */ +#define RCC_MP_RSTSCLRR_PORRSTF BIT(0) +#define RCC_MP_RSTSCLRR_BORRSTF BIT(1) +#define RCC_MP_RSTSCLRR_PADRSTF BIT(2) +#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_MP_RSTSCLRR_VCPURSTF BIT(5) +#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSCLRR_STP2RSTF BIT(10) +#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSCLRR_SPARE BIT(15) + +/* RCC_MP_IWDGFZSETR register fields */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) + +/* RCC_MP_IWDGFZCLRR register fields */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) + +/* RCC_MP_CIER register fields */ +#define RCC_MP_CIER_LSIRDYIE BIT(0) +#define RCC_MP_CIER_LSERDYIE BIT(1) +#define RCC_MP_CIER_HSIRDYIE BIT(2) +#define RCC_MP_CIER_HSERDYIE BIT(3) +#define RCC_MP_CIER_CSIRDYIE BIT(4) +#define RCC_MP_CIER_PLL1DYIE BIT(8) +#define RCC_MP_CIER_PLL2DYIE BIT(9) +#define RCC_MP_CIER_PLL3DYIE BIT(10) +#define RCC_MP_CIER_PLL4DYIE BIT(11) +#define RCC_MP_CIER_LSECSSIE BIT(16) +#define RCC_MP_CIER_WKUPIE BIT(20) + +/* RCC_MP_CIFR register fields */ +#define RCC_MP_CIFR_LSIRDYF BIT(0) +#define RCC_MP_CIFR_LSERDYF BIT(1) +#define RCC_MP_CIFR_HSIRDYF BIT(2) +#define RCC_MP_CIFR_HSERDYF BIT(3) +#define RCC_MP_CIFR_CSIRDYF BIT(4) +#define RCC_MP_CIFR_PLL1DYF BIT(8) +#define RCC_MP_CIFR_PLL2DYF BIT(9) +#define RCC_MP_CIFR_PLL3DYF BIT(10) +#define RCC_MP_CIFR_PLL4DYF BIT(11) +#define RCC_MP_CIFR_LSECSSF BIT(16) +#define RCC_MP_CIFR_WKUPF BIT(20) + +/* RCC_BDCR register fields */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_DIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(8) +#define RCC_BDCR_LSECSSD BIT(9) +#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_VSWRST BIT(31) + +#define RCC_BDCR_LSEBYP_BIT 1 +#define RCC_BDCR_LSERDY_BIT 2 +#define RCC_BDCR_DIGBYP_BIT 3 +#define RCC_BDCR_LSECSSON_BIT 8 + +#define RCC_BDCR_LSEDRV_WIDTH 2 + +/* RCC_RDLSICR register fields */ +#define RCC_RDLSICR_LSION BIT(0) +#define RCC_RDLSICR_LSIRDY BIT(1) +#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) +#define RCC_RDLSICR_MRD_SHIFT 16 +#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) +#define RCC_RDLSICR_EADLY_SHIFT 24 +#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) +#define RCC_RDLSICR_SPARE_SHIFT 27 + +#define RCC_RDLSICR_LSIRDY_BIT 1 + +/* RCC_OCENSETR register fields */ +#define RCC_OCENSETR_HSION BIT(0) +#define RCC_OCENSETR_HSIKERON BIT(1) +#define RCC_OCENSETR_CSION BIT(4) +#define RCC_OCENSETR_CSIKERON BIT(5) +#define RCC_OCENSETR_DIGBYP BIT(7) +#define RCC_OCENSETR_HSEON BIT(8) +#define RCC_OCENSETR_HSEKERON BIT(9) +#define RCC_OCENSETR_HSEBYP BIT(10) +#define RCC_OCENSETR_HSECSSON BIT(11) + +#define RCC_OCENR_DIGBYP_BIT 7 +#define RCC_OCENR_HSEBYP_BIT 10 +#define RCC_OCENR_HSECSSON_BIT 11 + +/* RCC_OCENCLRR register fields */ +#define RCC_OCENCLRR_HSION BIT(0) +#define RCC_OCENCLRR_HSIKERON BIT(1) +#define RCC_OCENCLRR_CSION BIT(4) +#define RCC_OCENCLRR_CSIKERON BIT(5) +#define RCC_OCENCLRR_DIGBYP BIT(7) +#define RCC_OCENCLRR_HSEON BIT(8) +#define RCC_OCENCLRR_HSEKERON BIT(9) +#define RCC_OCENCLRR_HSEBYP BIT(10) + +/* RCC_OCRDYR register fields */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSIDIVRDY BIT(2) +#define RCC_OCRDYR_CSIRDY BIT(4) +#define RCC_OCRDYR_HSERDY BIT(8) +#define RCC_OCRDYR_MPUCKRDY BIT(23) +#define RCC_OCRDYR_AXICKRDY BIT(24) + +#define RCC_OCRDYR_HSIRDY_BIT 0 +#define RCC_OCRDYR_HSIDIVRDY_BIT 2 +#define RCC_OCRDYR_CSIRDY_BIT 4 +#define RCC_OCRDYR_HSERDY_BIT 8 + +/* RCC_HSICFGR register fields */ +#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) +#define RCC_HSICFGR_HSIDIV_SHIFT 0 +#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) +#define RCC_HSICFGR_HSITRIM_SHIFT 8 +#define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16) +#define RCC_HSICFGR_HSICAL_SHIFT 16 + +/* RCC_CSICFGR register fields */ +#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) +#define RCC_CSICFGR_CSITRIM_SHIFT 8 +#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) +#define RCC_CSICFGR_CSICAL_SHIFT 16 + +/* RCC_MCO1CFGR register fields */ +#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) +#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 +#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) +#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 +#define RCC_MCO1CFGR_MCO1ON BIT(12) + +/* RCC_MCO2CFGR register fields */ +#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) +#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 +#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) +#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 +#define RCC_MCO2CFGR_MCO2ON BIT(12) + +/* RCC_DBGCFGR register fields */ +#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) +#define RCC_DBGCFGR_TRACEDIV_SHIFT 0 +#define RCC_DBGCFGR_DBGCKEN BIT(8) +#define RCC_DBGCFGR_TRACECKEN BIT(9) +#define RCC_DBGCFGR_DBGRST BIT(12) + +/* RCC_RCK12SELR register fields */ +#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) +#define RCC_RCK12SELR_PLL12SRC_SHIFT 0 +#define RCC_RCK12SELR_PLL12SRCRDY BIT(31) + +/* RCC_RCK3SELR register fields */ +#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) +#define RCC_RCK3SELR_PLL3SRC_SHIFT 0 +#define RCC_RCK3SELR_PLL3SRCRDY BIT(31) + +/* RCC_RCK4SELR register fields */ +#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) +#define RCC_RCK4SELR_PLL4SRC_SHIFT 0 +#define RCC_RCK4SELR_PLL4SRCRDY BIT(31) + +/* RCC_PLL1CR register fields */ +#define RCC_PLL1CR_PLLON BIT(0) +#define RCC_PLL1CR_PLL1RDY BIT(1) +#define RCC_PLL1CR_SSCG_CTRL BIT(2) +#define RCC_PLL1CR_DIVPEN BIT(4) +#define RCC_PLL1CR_DIVQEN BIT(5) +#define RCC_PLL1CR_DIVREN BIT(6) + +/* RCC_PLL1CFGR1 register fields */ +#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL1CFGR1_DIVN_SHIFT 0 +#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) +#define RCC_PLL1CFGR1_DIVM1_SHIFT 16 + +/* RCC_PLL1CFGR2 register fields */ +#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL1CFGR2_DIVP_SHIFT 0 +#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL1CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL1CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL1FRACR register fields */ +#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL1FRACR_FRACV_SHIFT 3 +#define RCC_PLL1FRACR_FRACLE BIT(16) + +/* RCC_PLL1CSGR register fields */ +#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL1CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL1CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL1CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL1CSGR_SSCG_MODE BIT(15) +#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL1CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL2CR register fields */ +#define RCC_PLL2CR_PLLON BIT(0) +#define RCC_PLL2CR_PLL2RDY BIT(1) +#define RCC_PLL2CR_SSCG_CTRL BIT(2) +#define RCC_PLL2CR_DIVPEN BIT(4) +#define RCC_PLL2CR_DIVQEN BIT(5) +#define RCC_PLL2CR_DIVREN BIT(6) + +/* RCC_PLL2CFGR1 register fields */ +#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL2CFGR1_DIVN_SHIFT 0 +#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) +#define RCC_PLL2CFGR1_DIVM2_SHIFT 16 + +/* RCC_PLL2CFGR2 register fields */ +#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL2CFGR2_DIVP_SHIFT 0 +#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL2CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL2CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL2FRACR register fields */ +#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL2FRACR_FRACV_SHIFT 3 +#define RCC_PLL2FRACR_FRACLE BIT(16) + +/* RCC_PLL2CSGR register fields */ +#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL2CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL2CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL2CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL2CSGR_SSCG_MODE BIT(15) +#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL2CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL3CR register fields */ +#define RCC_PLL3CR_PLLON BIT(0) +#define RCC_PLL3CR_PLL3RDY BIT(1) +#define RCC_PLL3CR_SSCG_CTRL BIT(2) +#define RCC_PLL3CR_DIVPEN BIT(4) +#define RCC_PLL3CR_DIVQEN BIT(5) +#define RCC_PLL3CR_DIVREN BIT(6) + +/* RCC_PLL3CFGR1 register fields */ +#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL3CFGR1_DIVN_SHIFT 0 +#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) +#define RCC_PLL3CFGR1_DIVM3_SHIFT 16 +#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL3CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL3CFGR2 register fields */ +#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL3CFGR2_DIVP_SHIFT 0 +#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL3CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL3CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL3FRACR register fields */ +#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL3FRACR_FRACV_SHIFT 3 +#define RCC_PLL3FRACR_FRACLE BIT(16) + +/* RCC_PLL3CSGR register fields */ +#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL3CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL3CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL3CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL3CSGR_SSCG_MODE BIT(15) +#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL3CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL4CR register fields */ +#define RCC_PLL4CR_PLLON BIT(0) +#define RCC_PLL4CR_PLL4RDY BIT(1) +#define RCC_PLL4CR_SSCG_CTRL BIT(2) +#define RCC_PLL4CR_DIVPEN BIT(4) +#define RCC_PLL4CR_DIVQEN BIT(5) +#define RCC_PLL4CR_DIVREN BIT(6) + +/* RCC_PLL4CFGR1 register fields */ +#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL4CFGR1_DIVN_SHIFT 0 +#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) +#define RCC_PLL4CFGR1_DIVM4_SHIFT 16 +#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL4CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL4CFGR2 register fields */ +#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL4CFGR2_DIVP_SHIFT 0 +#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL4CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL4CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL4FRACR register fields */ +#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL4FRACR_FRACV_SHIFT 3 +#define RCC_PLL4FRACR_FRACLE BIT(16) + +/* RCC_PLL4CSGR register fields */ +#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL4CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL4CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL4CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL4CSGR_SSCG_MODE BIT(15) +#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL4CSGR_INC_STEP_SHIFT 16 + +/* RCC_MPCKSELR register fields */ +#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) +#define RCC_MPCKSELR_MPUSRC_SHIFT 0 +#define RCC_MPCKSELR_MPUSRCRDY BIT(31) + +/* RCC_ASSCKSELR register fields */ +#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) +#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 +#define RCC_ASSCKSELR_AXISSRCRDY BIT(31) + +/* RCC_MSSCKSELR register fields */ +#define RCC_MSSCKSELR_MLAHBSSRC_MASK GENMASK(1, 0) +#define RCC_MSSCKSELR_MLAHBSSRC_SHIFT 0 +#define RCC_MSSCKSELR_MLAHBSSRCRDY BIT(31) + +/* RCC_CPERCKSELR register fields */ +#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 + +/* RCC_RTCDIVR register fields */ +#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) +#define RCC_RTCDIVR_RTCDIV_SHIFT 0 + +/* RCC_MPCKDIVR register fields */ +#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(3, 0) +#define RCC_MPCKDIVR_MPUDIV_SHIFT 0 +#define RCC_MPCKDIVR_MPUDIVRDY BIT(31) + +/* RCC_AXIDIVR register fields */ +#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIVR_AXIDIV_SHIFT 0 +#define RCC_AXIDIVR_AXIDIVRDY BIT(31) + +/* RCC_MLAHBDIVR register fields */ +#define RCC_MLAHBDIVR_MLAHBDIV_MASK GENMASK(3, 0) +#define RCC_MLAHBDIVR_MLAHBDIV_SHIFT 0 +#define RCC_MLAHBDIVR_MLAHBDIVRDY BIT(31) + +/* RCC_APB1DIVR register fields */ +#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) +#define RCC_APB1DIVR_APB1DIV_SHIFT 0 +#define RCC_APB1DIVR_APB1DIVRDY BIT(31) + +/* RCC_APB2DIVR register fields */ +#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) +#define RCC_APB2DIVR_APB2DIV_SHIFT 0 +#define RCC_APB2DIVR_APB2DIVRDY BIT(31) + +/* RCC_APB3DIVR register fields */ +#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) +#define RCC_APB3DIVR_APB3DIV_SHIFT 0 +#define RCC_APB3DIVR_APB3DIVRDY BIT(31) + +/* RCC_APB4DIVR register fields */ +#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) +#define RCC_APB4DIVR_APB4DIV_SHIFT 0 +#define RCC_APB4DIVR_APB4DIVRDY BIT(31) + +/* RCC_APB5DIVR register fields */ +#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) +#define RCC_APB5DIVR_APB5DIV_SHIFT 0 +#define RCC_APB5DIVR_APB5DIVRDY BIT(31) + +/* RCC_APB6DIVR register fields */ +#define RCC_APB6DIVR_APB6DIV_MASK GENMASK(2, 0) +#define RCC_APB6DIVR_APB6DIV_SHIFT 0 +#define RCC_APB6DIVR_APB6DIVRDY BIT(31) + +/* RCC_TIMG1PRER register fields */ +#define RCC_TIMG1PRER_TIMG1PRE BIT(0) +#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) + +/* RCC_TIMG2PRER register fields */ +#define RCC_TIMG2PRER_TIMG2PRE BIT(0) +#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) + +/* RCC_TIMG3PRER register fields */ +#define RCC_TIMG3PRER_TIMG3PRE BIT(0) +#define RCC_TIMG3PRER_TIMG3PRERDY BIT(31) + +/* RCC_DDRITFCR register fields */ +#define RCC_DDRITFCR_DDRC1EN BIT(0) +#define RCC_DDRITFCR_DDRC1LPEN BIT(1) +#define RCC_DDRITFCR_DDRPHYCEN BIT(4) +#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) +#define RCC_DDRITFCR_DDRCAPBEN BIT(6) +#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) +#define RCC_DDRITFCR_AXIDCGEN BIT(8) +#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) +#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) +#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 +#define RCC_DDRITFCR_DDRCAPBRST BIT(14) +#define RCC_DDRITFCR_DDRCAXIRST BIT(15) +#define RCC_DDRITFCR_DDRCORERST BIT(16) +#define RCC_DDRITFCR_DPHYAPBRST BIT(17) +#define RCC_DDRITFCR_DPHYRST BIT(18) +#define RCC_DDRITFCR_DPHYCTLRST BIT(19) +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 +#define RCC_DDRITFCR_GSKPMOD BIT(23) +#define RCC_DDRITFCR_GSKPCTRL BIT(24) +#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) +#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 +#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) +#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 + +/* RCC_I2C12CKSELR register fields */ +#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) +#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 + +/* RCC_I2C345CKSELR register fields */ +#define RCC_I2C345CKSELR_I2C3SRC_MASK GENMASK(2, 0) +#define RCC_I2C345CKSELR_I2C3SRC_SHIFT 0 +#define RCC_I2C345CKSELR_I2C4SRC_MASK GENMASK(5, 3) +#define RCC_I2C345CKSELR_I2C4SRC_SHIFT 3 +#define RCC_I2C345CKSELR_I2C5SRC_MASK GENMASK(8, 6) +#define RCC_I2C345CKSELR_I2C5SRC_SHIFT 6 + +/* RCC_SPI2S1CKSELR register fields */ +#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 + +/* RCC_SPI2S23CKSELR register fields */ +#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 + +/* RCC_SPI45CKSELR register fields */ +#define RCC_SPI45CKSELR_SPI4SRC_MASK GENMASK(2, 0) +#define RCC_SPI45CKSELR_SPI4SRC_SHIFT 0 +#define RCC_SPI45CKSELR_SPI5SRC_MASK GENMASK(5, 3) +#define RCC_SPI45CKSELR_SPI5SRC_SHIFT 3 + +/* RCC_UART12CKSELR register fields */ +#define RCC_UART12CKSELR_UART1SRC_MASK GENMASK(2, 0) +#define RCC_UART12CKSELR_UART1SRC_SHIFT 0 +#define RCC_UART12CKSELR_UART2SRC_MASK GENMASK(5, 3) +#define RCC_UART12CKSELR_UART2SRC_SHIFT 3 + +/* RCC_UART35CKSELR register fields */ +#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) +#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 + +/* RCC_UART4CKSELR register fields */ +#define RCC_UART4CKSELR_UART4SRC_MASK GENMASK(2, 0) +#define RCC_UART4CKSELR_UART4SRC_SHIFT 0 + +/* RCC_UART6CKSELR register fields */ +#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) +#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 + +/* RCC_UART78CKSELR register fields */ +#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) +#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 + +/* RCC_LPTIM1CKSELR register fields */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 + +/* RCC_LPTIM23CKSELR register fields */ +#define RCC_LPTIM23CKSELR_LPTIM2SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM23CKSELR_LPTIM2SRC_SHIFT 0 +#define RCC_LPTIM23CKSELR_LPTIM3SRC_MASK GENMASK(5, 3) +#define RCC_LPTIM23CKSELR_LPTIM3SRC_SHIFT 3 + +/* RCC_LPTIM45CKSELR register fields */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 + +/* RCC_SAI1CKSELR register fields */ +#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) +#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 + +/* RCC_SAI2CKSELR register fields */ +#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) +#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 + +/* RCC_FDCANCKSELR register fields */ +#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) +#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 + +/* RCC_SPDIFCKSELR register fields */ +#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) +#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 + +/* RCC_ADC12CKSELR register fields */ +#define RCC_ADC12CKSELR_ADC1SRC_MASK GENMASK(1, 0) +#define RCC_ADC12CKSELR_ADC1SRC_SHIFT 0 +#define RCC_ADC12CKSELR_ADC2SRC_MASK GENMASK(3, 2) +#define RCC_ADC12CKSELR_ADC2SRC_SHIFT 2 + +/* RCC_SDMMC12CKSELR register fields */ +#define RCC_SDMMC12CKSELR_SDMMC1SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC12CKSELR_SDMMC1SRC_SHIFT 0 +#define RCC_SDMMC12CKSELR_SDMMC2SRC_MASK GENMASK(5, 3) +#define RCC_SDMMC12CKSELR_SDMMC2SRC_SHIFT 3 + +/* RCC_ETH12CKSELR register fields */ +#define RCC_ETH12CKSELR_ETH1SRC_MASK GENMASK(1, 0) +#define RCC_ETH12CKSELR_ETH1SRC_SHIFT 0 +#define RCC_ETH12CKSELR_ETH1PTPDIV_MASK GENMASK(7, 4) +#define RCC_ETH12CKSELR_ETH1PTPDIV_SHIFT 4 +#define RCC_ETH12CKSELR_ETH2SRC_MASK GENMASK(9, 8) +#define RCC_ETH12CKSELR_ETH2SRC_SHIFT 8 +#define RCC_ETH12CKSELR_ETH2PTPDIV_MASK GENMASK(15, 12) +#define RCC_ETH12CKSELR_ETH2PTPDIV_SHIFT 12 + +/* RCC_USBCKSELR register fields */ +#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) +#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 +#define RCC_USBCKSELR_USBOSRC BIT(4) + +/* RCC_QSPICKSELR register fields */ +#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) +#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 + +/* RCC_FMCCKSELR register fields */ +#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) +#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 + +/* RCC_RNG1CKSELR register fields */ +#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) +#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 + +/* RCC_STGENCKSELR register fields */ +#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) +#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 + +/* RCC_DCMIPPCKSELR register fields */ +#define RCC_DCMIPPCKSELR_DCMIPPSRC_MASK GENMASK(1, 0) +#define RCC_DCMIPPCKSELR_DCMIPPSRC_SHIFT 0 + +/* RCC_SAESCKSELR register fields */ +#define RCC_SAESCKSELR_SAESSRC_MASK GENMASK(1, 0) +#define RCC_SAESCKSELR_SAESSRC_SHIFT 0 + +/* RCC_APB1RSTSETR register fields */ +#define RCC_APB1RSTSETR_TIM2RST BIT(0) +#define RCC_APB1RSTSETR_TIM3RST BIT(1) +#define RCC_APB1RSTSETR_TIM4RST BIT(2) +#define RCC_APB1RSTSETR_TIM5RST BIT(3) +#define RCC_APB1RSTSETR_TIM6RST BIT(4) +#define RCC_APB1RSTSETR_TIM7RST BIT(5) +#define RCC_APB1RSTSETR_LPTIM1RST BIT(9) +#define RCC_APB1RSTSETR_SPI2RST BIT(11) +#define RCC_APB1RSTSETR_SPI3RST BIT(12) +#define RCC_APB1RSTSETR_USART3RST BIT(15) +#define RCC_APB1RSTSETR_UART4RST BIT(16) +#define RCC_APB1RSTSETR_UART5RST BIT(17) +#define RCC_APB1RSTSETR_UART7RST BIT(18) +#define RCC_APB1RSTSETR_UART8RST BIT(19) +#define RCC_APB1RSTSETR_I2C1RST BIT(21) +#define RCC_APB1RSTSETR_I2C2RST BIT(22) +#define RCC_APB1RSTSETR_SPDIFRST BIT(26) + +/* RCC_APB1RSTCLRR register fields */ +#define RCC_APB1RSTCLRR_TIM2RST BIT(0) +#define RCC_APB1RSTCLRR_TIM3RST BIT(1) +#define RCC_APB1RSTCLRR_TIM4RST BIT(2) +#define RCC_APB1RSTCLRR_TIM5RST BIT(3) +#define RCC_APB1RSTCLRR_TIM6RST BIT(4) +#define RCC_APB1RSTCLRR_TIM7RST BIT(5) +#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) +#define RCC_APB1RSTCLRR_SPI2RST BIT(11) +#define RCC_APB1RSTCLRR_SPI3RST BIT(12) +#define RCC_APB1RSTCLRR_USART3RST BIT(15) +#define RCC_APB1RSTCLRR_UART4RST BIT(16) +#define RCC_APB1RSTCLRR_UART5RST BIT(17) +#define RCC_APB1RSTCLRR_UART7RST BIT(18) +#define RCC_APB1RSTCLRR_UART8RST BIT(19) +#define RCC_APB1RSTCLRR_I2C1RST BIT(21) +#define RCC_APB1RSTCLRR_I2C2RST BIT(22) +#define RCC_APB1RSTCLRR_SPDIFRST BIT(26) + +/* RCC_APB2RSTSETR register fields */ +#define RCC_APB2RSTSETR_TIM1RST BIT(0) +#define RCC_APB2RSTSETR_TIM8RST BIT(1) +#define RCC_APB2RSTSETR_SPI1RST BIT(8) +#define RCC_APB2RSTSETR_USART6RST BIT(13) +#define RCC_APB2RSTSETR_SAI1RST BIT(16) +#define RCC_APB2RSTSETR_SAI2RST BIT(17) +#define RCC_APB2RSTSETR_DFSDMRST BIT(20) +#define RCC_APB2RSTSETR_FDCANRST BIT(24) + +/* RCC_APB2RSTCLRR register fields */ +#define RCC_APB2RSTCLRR_TIM1RST BIT(0) +#define RCC_APB2RSTCLRR_TIM8RST BIT(1) +#define RCC_APB2RSTCLRR_SPI1RST BIT(8) +#define RCC_APB2RSTCLRR_USART6RST BIT(13) +#define RCC_APB2RSTCLRR_SAI1RST BIT(16) +#define RCC_APB2RSTCLRR_SAI2RST BIT(17) +#define RCC_APB2RSTCLRR_DFSDMRST BIT(20) +#define RCC_APB2RSTCLRR_FDCANRST BIT(24) + +/* RCC_APB3RSTSETR register fields */ +#define RCC_APB3RSTSETR_LPTIM2RST BIT(0) +#define RCC_APB3RSTSETR_LPTIM3RST BIT(1) +#define RCC_APB3RSTSETR_LPTIM4RST BIT(2) +#define RCC_APB3RSTSETR_LPTIM5RST BIT(3) +#define RCC_APB3RSTSETR_SYSCFGRST BIT(11) +#define RCC_APB3RSTSETR_VREFRST BIT(13) +#define RCC_APB3RSTSETR_DTSRST BIT(16) +#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) + +/* RCC_APB3RSTCLRR register fields */ +#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) +#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) +#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) +#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) +#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) +#define RCC_APB3RSTCLRR_VREFRST BIT(13) +#define RCC_APB3RSTCLRR_DTSRST BIT(16) +#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) + +/* RCC_APB4RSTSETR register fields */ +#define RCC_APB4RSTSETR_LTDCRST BIT(0) +#define RCC_APB4RSTSETR_DCMIPPRST BIT(1) +#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTSETR_USBPHYRST BIT(16) + +/* RCC_APB4RSTCLRR register fields */ +#define RCC_APB4RSTCLRR_LTDCRST BIT(0) +#define RCC_APB4RSTCLRR_DCMIPPRST BIT(1) +#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTCLRR_USBPHYRST BIT(16) + +/* RCC_APB5RSTSETR register fields */ +#define RCC_APB5RSTSETR_STGENRST BIT(20) + +/* RCC_APB5RSTCLRR register fields */ +#define RCC_APB5RSTCLRR_STGENRST BIT(20) + +/* RCC_APB6RSTSETR register fields */ +#define RCC_APB6RSTSETR_USART1RST BIT(0) +#define RCC_APB6RSTSETR_USART2RST BIT(1) +#define RCC_APB6RSTSETR_SPI4RST BIT(2) +#define RCC_APB6RSTSETR_SPI5RST BIT(3) +#define RCC_APB6RSTSETR_I2C3RST BIT(4) +#define RCC_APB6RSTSETR_I2C4RST BIT(5) +#define RCC_APB6RSTSETR_I2C5RST BIT(6) +#define RCC_APB6RSTSETR_TIM12RST BIT(7) +#define RCC_APB6RSTSETR_TIM13RST BIT(8) +#define RCC_APB6RSTSETR_TIM14RST BIT(9) +#define RCC_APB6RSTSETR_TIM15RST BIT(10) +#define RCC_APB6RSTSETR_TIM16RST BIT(11) +#define RCC_APB6RSTSETR_TIM17RST BIT(12) + +/* RCC_APB6RSTCLRR register fields */ +#define RCC_APB6RSTCLRR_USART1RST BIT(0) +#define RCC_APB6RSTCLRR_USART2RST BIT(1) +#define RCC_APB6RSTCLRR_SPI4RST BIT(2) +#define RCC_APB6RSTCLRR_SPI5RST BIT(3) +#define RCC_APB6RSTCLRR_I2C3RST BIT(4) +#define RCC_APB6RSTCLRR_I2C4RST BIT(5) +#define RCC_APB6RSTCLRR_I2C5RST BIT(6) +#define RCC_APB6RSTCLRR_TIM12RST BIT(7) +#define RCC_APB6RSTCLRR_TIM13RST BIT(8) +#define RCC_APB6RSTCLRR_TIM14RST BIT(9) +#define RCC_APB6RSTCLRR_TIM15RST BIT(10) +#define RCC_APB6RSTCLRR_TIM16RST BIT(11) +#define RCC_APB6RSTCLRR_TIM17RST BIT(12) + +/* RCC_AHB2RSTSETR register fields */ +#define RCC_AHB2RSTSETR_DMA1RST BIT(0) +#define RCC_AHB2RSTSETR_DMA2RST BIT(1) +#define RCC_AHB2RSTSETR_DMAMUX1RST BIT(2) +#define RCC_AHB2RSTSETR_DMA3RST BIT(3) +#define RCC_AHB2RSTSETR_DMAMUX2RST BIT(4) +#define RCC_AHB2RSTSETR_ADC1RST BIT(5) +#define RCC_AHB2RSTSETR_ADC2RST BIT(6) +#define RCC_AHB2RSTSETR_USBORST BIT(8) + +/* RCC_AHB2RSTCLRR register fields */ +#define RCC_AHB2RSTCLRR_DMA1RST BIT(0) +#define RCC_AHB2RSTCLRR_DMA2RST BIT(1) +#define RCC_AHB2RSTCLRR_DMAMUX1RST BIT(2) +#define RCC_AHB2RSTCLRR_DMA3RST BIT(3) +#define RCC_AHB2RSTCLRR_DMAMUX2RST BIT(4) +#define RCC_AHB2RSTCLRR_ADC1RST BIT(5) +#define RCC_AHB2RSTCLRR_ADC2RST BIT(6) +#define RCC_AHB2RSTCLRR_USBORST BIT(8) + +/* RCC_AHB4RSTSETR register fields */ +#define RCC_AHB4RSTSETR_GPIOARST BIT(0) +#define RCC_AHB4RSTSETR_GPIOBRST BIT(1) +#define RCC_AHB4RSTSETR_GPIOCRST BIT(2) +#define RCC_AHB4RSTSETR_GPIODRST BIT(3) +#define RCC_AHB4RSTSETR_GPIOERST BIT(4) +#define RCC_AHB4RSTSETR_GPIOFRST BIT(5) +#define RCC_AHB4RSTSETR_GPIOGRST BIT(6) +#define RCC_AHB4RSTSETR_GPIOHRST BIT(7) +#define RCC_AHB4RSTSETR_GPIOIRST BIT(8) +#define RCC_AHB4RSTSETR_TSCRST BIT(15) + +/* RCC_AHB4RSTCLRR register fields */ +#define RCC_AHB4RSTCLRR_GPIOARST BIT(0) +#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) +#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) +#define RCC_AHB4RSTCLRR_GPIODRST BIT(3) +#define RCC_AHB4RSTCLRR_GPIOERST BIT(4) +#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) +#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) +#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) +#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) +#define RCC_AHB4RSTCLRR_TSCRST BIT(15) + +/* RCC_AHB5RSTSETR register fields */ +#define RCC_AHB5RSTSETR_PKARST BIT(2) +#define RCC_AHB5RSTSETR_SAESRST BIT(3) +#define RCC_AHB5RSTSETR_CRYP1RST BIT(4) +#define RCC_AHB5RSTSETR_HASH1RST BIT(5) +#define RCC_AHB5RSTSETR_RNG1RST BIT(6) +#define RCC_AHB5RSTSETR_AXIMCRST BIT(16) + +/* RCC_AHB5RSTCLRR register fields */ +#define RCC_AHB5RSTCLRR_PKARST BIT(2) +#define RCC_AHB5RSTCLRR_SAESRST BIT(3) +#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) +#define RCC_AHB5RSTCLRR_HASH1RST BIT(5) +#define RCC_AHB5RSTCLRR_RNG1RST BIT(6) +#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) + +/* RCC_AHB6RSTSETR register fields */ +#define RCC_AHB6RSTSETR_MDMARST BIT(0) +#define RCC_AHB6RSTSETR_MCERST BIT(1) +#define RCC_AHB6RSTSETR_ETH1MACRST BIT(10) +#define RCC_AHB6RSTSETR_FMCRST BIT(12) +#define RCC_AHB6RSTSETR_QSPIRST BIT(14) +#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTSETR_CRC1RST BIT(20) +#define RCC_AHB6RSTSETR_USBHRST BIT(24) +#define RCC_AHB6RSTSETR_ETH2MACRST BIT(30) + +/* RCC_AHB6RSTCLRR register fields */ +#define RCC_AHB6RSTCLRR_MDMARST BIT(0) +#define RCC_AHB6RSTCLRR_MCERST BIT(1) +#define RCC_AHB6RSTCLRR_ETH1MACRST BIT(10) +#define RCC_AHB6RSTCLRR_FMCRST BIT(12) +#define RCC_AHB6RSTCLRR_QSPIRST BIT(14) +#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTCLRR_CRC1RST BIT(20) +#define RCC_AHB6RSTCLRR_USBHRST BIT(24) +#define RCC_AHB6RSTCLRR_ETH2MACRST BIT(30) + +/* RCC_MP_APB1ENSETR register fields */ +#define RCC_MP_APB1ENSETR_TIM2EN BIT(0) +#define RCC_MP_APB1ENSETR_TIM3EN BIT(1) +#define RCC_MP_APB1ENSETR_TIM4EN BIT(2) +#define RCC_MP_APB1ENSETR_TIM5EN BIT(3) +#define RCC_MP_APB1ENSETR_TIM6EN BIT(4) +#define RCC_MP_APB1ENSETR_TIM7EN BIT(5) +#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENSETR_SPI2EN BIT(11) +#define RCC_MP_APB1ENSETR_SPI3EN BIT(12) +#define RCC_MP_APB1ENSETR_USART3EN BIT(15) +#define RCC_MP_APB1ENSETR_UART4EN BIT(16) +#define RCC_MP_APB1ENSETR_UART5EN BIT(17) +#define RCC_MP_APB1ENSETR_UART7EN BIT(18) +#define RCC_MP_APB1ENSETR_UART8EN BIT(19) +#define RCC_MP_APB1ENSETR_I2C1EN BIT(21) +#define RCC_MP_APB1ENSETR_I2C2EN BIT(22) +#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) + +/* RCC_MP_APB1ENCLRR register fields */ +#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) +#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) +#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) +#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) +#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) +#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) +#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) +#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) +#define RCC_MP_APB1ENCLRR_USART3EN BIT(15) +#define RCC_MP_APB1ENCLRR_UART4EN BIT(16) +#define RCC_MP_APB1ENCLRR_UART5EN BIT(17) +#define RCC_MP_APB1ENCLRR_UART7EN BIT(18) +#define RCC_MP_APB1ENCLRR_UART8EN BIT(19) +#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) +#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) +#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) + +/* RCC_MP_APB2ENSETR register fields */ +#define RCC_MP_APB2ENSETR_TIM1EN BIT(0) +#define RCC_MP_APB2ENSETR_TIM8EN BIT(1) +#define RCC_MP_APB2ENSETR_SPI1EN BIT(8) +#define RCC_MP_APB2ENSETR_USART6EN BIT(13) +#define RCC_MP_APB2ENSETR_SAI1EN BIT(16) +#define RCC_MP_APB2ENSETR_SAI2EN BIT(17) +#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENSETR_FDCANEN BIT(24) + +/* RCC_MP_APB2ENCLRR register fields */ +#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) +#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) +#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) +#define RCC_MP_APB2ENCLRR_USART6EN BIT(13) +#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) +#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) +#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) + +/* RCC_MP_APB3ENSETR register fields */ +#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENSETR_VREFEN BIT(13) +#define RCC_MP_APB3ENSETR_DTSEN BIT(16) +#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENSETR_HDPEN BIT(20) + +/* RCC_MP_APB3ENCLRR register fields */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENCLRR_VREFEN BIT(13) +#define RCC_MP_APB3ENCLRR_DTSEN BIT(16) +#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENCLRR_HDPEN BIT(20) + +/* RCC_MP_S_APB3ENSETR register fields */ +#define RCC_MP_S_APB3ENSETR_SYSCFGEN BIT(0) + +/* RCC_MP_S_APB3ENCLRR register fields */ +#define RCC_MP_S_APB3ENCLRR_SYSCFGEN BIT(0) + +/* RCC_MP_NS_APB3ENSETR register fields */ +#define RCC_MP_NS_APB3ENSETR_SYSCFGEN BIT(0) + +/* RCC_MP_NS_APB3ENCLRR register fields */ +#define RCC_MP_NS_APB3ENCLRR_SYSCFGEN BIT(0) + +/* RCC_MP_APB4ENSETR register fields */ +#define RCC_MP_APB4ENSETR_DCMIPPEN BIT(1) +#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENSETR_STGENROEN BIT(20) + +/* RCC_MP_APB4ENCLRR register fields */ +#define RCC_MP_APB4ENCLRR_DCMIPPEN BIT(1) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) + +/* RCC_MP_S_APB4ENSETR register fields */ +#define RCC_MP_S_APB4ENSETR_LTDCEN BIT(0) + +/* RCC_MP_S_APB4ENCLRR register fields */ +#define RCC_MP_S_APB4ENCLRR_LTDCEN BIT(0) + +/* RCC_MP_NS_APB4ENSETR register fields */ +#define RCC_MP_NS_APB4ENSETR_LTDCEN BIT(0) + +/* RCC_MP_NS_APB4ENCLRR register fields */ +#define RCC_MP_NS_APB4ENCLRR_LTDCEN BIT(0) + +/* RCC_MP_APB5ENSETR register fields */ +#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENSETR_TZCEN BIT(11) +#define RCC_MP_APB5ENSETR_ETZPCEN BIT(13) +#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENSETR_BSECEN BIT(16) +#define RCC_MP_APB5ENSETR_STGENCEN BIT(20) + +/* RCC_MP_APB5ENCLRR register fields */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENCLRR_TZCEN BIT(11) +#define RCC_MP_APB5ENCLRR_ETZPCEN BIT(13) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENCLRR_BSECEN BIT(16) +#define RCC_MP_APB5ENCLRR_STGENCEN BIT(20) + +/* RCC_MP_APB6ENSETR register fields */ +#define RCC_MP_APB6ENSETR_USART1EN BIT(0) +#define RCC_MP_APB6ENSETR_USART2EN BIT(1) +#define RCC_MP_APB6ENSETR_SPI4EN BIT(2) +#define RCC_MP_APB6ENSETR_SPI5EN BIT(3) +#define RCC_MP_APB6ENSETR_I2C3EN BIT(4) +#define RCC_MP_APB6ENSETR_I2C4EN BIT(5) +#define RCC_MP_APB6ENSETR_I2C5EN BIT(6) +#define RCC_MP_APB6ENSETR_TIM12EN BIT(7) +#define RCC_MP_APB6ENSETR_TIM13EN BIT(8) +#define RCC_MP_APB6ENSETR_TIM14EN BIT(9) +#define RCC_MP_APB6ENSETR_TIM15EN BIT(10) +#define RCC_MP_APB6ENSETR_TIM16EN BIT(11) +#define RCC_MP_APB6ENSETR_TIM17EN BIT(12) + +/* RCC_MP_APB6ENCLRR register fields */ +#define RCC_MP_APB6ENCLRR_USART1EN BIT(0) +#define RCC_MP_APB6ENCLRR_USART2EN BIT(1) +#define RCC_MP_APB6ENCLRR_SPI4EN BIT(2) +#define RCC_MP_APB6ENCLRR_SPI5EN BIT(3) +#define RCC_MP_APB6ENCLRR_I2C3EN BIT(4) +#define RCC_MP_APB6ENCLRR_I2C4EN BIT(5) +#define RCC_MP_APB6ENCLRR_I2C5EN BIT(6) +#define RCC_MP_APB6ENCLRR_TIM12EN BIT(7) +#define RCC_MP_APB6ENCLRR_TIM13EN BIT(8) +#define RCC_MP_APB6ENCLRR_TIM14EN BIT(9) +#define RCC_MP_APB6ENCLRR_TIM15EN BIT(10) +#define RCC_MP_APB6ENCLRR_TIM16EN BIT(11) +#define RCC_MP_APB6ENCLRR_TIM17EN BIT(12) + +/* RCC_MP_AHB2ENSETR register fields */ +#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENSETR_DMAMUX1EN BIT(2) +#define RCC_MP_AHB2ENSETR_DMA3EN BIT(3) +#define RCC_MP_AHB2ENSETR_DMAMUX2EN BIT(4) +#define RCC_MP_AHB2ENSETR_ADC1EN BIT(5) +#define RCC_MP_AHB2ENSETR_ADC2EN BIT(6) +#define RCC_MP_AHB2ENSETR_USBOEN BIT(8) + +/* RCC_MP_AHB2ENCLRR register fields */ +#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENCLRR_DMAMUX1EN BIT(2) +#define RCC_MP_AHB2ENCLRR_DMA3EN BIT(3) +#define RCC_MP_AHB2ENCLRR_DMAMUX2EN BIT(4) +#define RCC_MP_AHB2ENCLRR_ADC1EN BIT(5) +#define RCC_MP_AHB2ENCLRR_ADC2EN BIT(6) +#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) + +/* RCC_MP_AHB4ENSETR register fields */ +#define RCC_MP_AHB4ENSETR_TSCEN BIT(15) + +/* RCC_MP_AHB4ENCLRR register fields */ +#define RCC_MP_AHB4ENCLRR_TSCEN BIT(15) + +/* RCC_MP_S_AHB4ENSETR register fields */ +#define RCC_MP_S_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MP_S_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MP_S_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MP_S_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MP_S_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MP_S_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MP_S_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MP_S_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MP_S_AHB4ENSETR_GPIOIEN BIT(8) + +/* RCC_MP_S_AHB4ENCLRR register fields */ +#define RCC_MP_S_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MP_S_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MP_S_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MP_S_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MP_S_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MP_S_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MP_S_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MP_S_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MP_S_AHB4ENCLRR_GPIOIEN BIT(8) + +/* RCC_MP_NS_AHB4ENSETR register fields */ +#define RCC_MP_NS_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MP_NS_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MP_NS_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MP_NS_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MP_NS_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MP_NS_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MP_NS_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MP_NS_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MP_NS_AHB4ENSETR_GPIOIEN BIT(8) + +/* RCC_MP_NS_AHB4ENCLRR register fields */ +#define RCC_MP_NS_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MP_NS_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MP_NS_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MP_NS_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MP_NS_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MP_NS_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MP_NS_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MP_NS_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MP_NS_AHB4ENCLRR_GPIOIEN BIT(8) + +/* RCC_MP_AHB5ENSETR register fields */ +#define RCC_MP_AHB5ENSETR_PKAEN BIT(2) +#define RCC_MP_AHB5ENSETR_SAESEN BIT(3) +#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) + +/* RCC_MP_AHB5ENCLRR register fields */ +#define RCC_MP_AHB5ENCLRR_PKAEN BIT(2) +#define RCC_MP_AHB5ENCLRR_SAESEN BIT(3) +#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) + +/* RCC_MP_AHB6ENSETR register fields */ +#define RCC_MP_AHB6ENSETR_MCEEN BIT(1) +#define RCC_MP_AHB6ENSETR_ETH1CKEN BIT(7) +#define RCC_MP_AHB6ENSETR_ETH1TXEN BIT(8) +#define RCC_MP_AHB6ENSETR_ETH1RXEN BIT(9) +#define RCC_MP_AHB6ENSETR_ETH1MACEN BIT(10) +#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) +#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENSETR_USBHEN BIT(24) +#define RCC_MP_AHB6ENSETR_ETH2CKEN BIT(27) +#define RCC_MP_AHB6ENSETR_ETH2TXEN BIT(28) +#define RCC_MP_AHB6ENSETR_ETH2RXEN BIT(29) +#define RCC_MP_AHB6ENSETR_ETH2MACEN BIT(30) + +/* RCC_MP_AHB6ENCLRR register fields */ +#define RCC_MP_AHB6ENCLRR_MCEEN BIT(1) +#define RCC_MP_AHB6ENCLRR_ETH1CKEN BIT(7) +#define RCC_MP_AHB6ENCLRR_ETH1TXEN BIT(8) +#define RCC_MP_AHB6ENCLRR_ETH1RXEN BIT(9) +#define RCC_MP_AHB6ENCLRR_ETH1MACEN BIT(10) +#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) +#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) +#define RCC_MP_AHB6ENCLRR_ETH2CKEN BIT(27) +#define RCC_MP_AHB6ENCLRR_ETH2TXEN BIT(28) +#define RCC_MP_AHB6ENCLRR_ETH2RXEN BIT(29) +#define RCC_MP_AHB6ENCLRR_ETH2MACEN BIT(30) + +/* RCC_MP_S_AHB6ENSETR register fields */ +#define RCC_MP_S_AHB6ENSETR_MDMAEN BIT(0) + +/* RCC_MP_S_AHB6ENCLRR register fields */ +#define RCC_MP_S_AHB6ENCLRR_MDMAEN BIT(0) + +/* RCC_MP_NS_AHB6ENSETR register fields */ +#define RCC_MP_NS_AHB6ENSETR_MDMAEN BIT(0) + +/* RCC_MP_NS_AHB6ENCLRR register fields */ +#define RCC_MP_NS_AHB6ENCLRR_MDMAEN BIT(0) + +/* RCC_MP_APB1LPENSETR register fields */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) + +/* RCC_MP_APB1LPENCLRR register fields */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) + +/* RCC_MP_APB2LPENSETR register fields */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) + +/* RCC_MP_APB2LPENCLRR register fields */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) + +/* RCC_MP_APB3LPENSETR register fields */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENSETR_DTSLPEN BIT(16) +#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_APB3LPENCLRR register fields */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENCLRR_DTSLPEN BIT(16) +#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_S_APB3LPENSETR register fields */ +#define RCC_MP_S_APB3LPENSETR_SYSCFGLPEN BIT(0) + +/* RCC_MP_S_APB3LPENCLRR register fields */ +#define RCC_MP_S_APB3LPENCLRR_SYSCFGLPEN BIT(0) + +/* RCC_MP_NS_APB3LPENSETR register fields */ +#define RCC_MP_NS_APB3LPENSETR_SYSCFGLPEN BIT(0) + +/* RCC_MP_NS_APB3LPENCLRR register fields */ +#define RCC_MP_NS_APB3LPENCLRR_SYSCFGLPEN BIT(0) + +/* RCC_MP_APB4LPENSETR register fields */ +#define RCC_MP_APB4LPENSETR_DCMIPPLPEN BIT(1) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) + +/* RCC_MP_APB4LPENCLRR register fields */ +#define RCC_MP_APB4LPENCLRR_DCMIPPLPEN BIT(1) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) + +/* RCC_MP_S_APB4LPENSETR register fields */ +#define RCC_MP_S_APB4LPENSETR_LTDCLPEN BIT(0) + +/* RCC_MP_S_APB4LPENCLRR register fields */ +#define RCC_MP_S_APB4LPENCLRR_LTDCLPEN BIT(0) + +/* RCC_MP_NS_APB4LPENSETR register fields */ +#define RCC_MP_NS_APB4LPENSETR_LTDCLPEN BIT(0) + +/* RCC_MP_NS_APB4LPENCLRR register fields */ +#define RCC_MP_NS_APB4LPENCLRR_LTDCLPEN BIT(0) + +/* RCC_MP_APB5LPENSETR register fields */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENSETR_TZCLPEN BIT(11) +#define RCC_MP_APB5LPENSETR_ETZPCLPEN BIT(13) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENSETR_STGENCLPEN BIT(20) +#define RCC_MP_APB5LPENSETR_STGENCSTPEN BIT(21) + +/* RCC_MP_APB5LPENCLRR register fields */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENCLRR_TZCLPEN BIT(11) +#define RCC_MP_APB5LPENCLRR_ETZPCLPEN BIT(13) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENCLRR_STGENCLPEN BIT(20) +#define RCC_MP_APB5LPENCLRR_STGENCSTPEN BIT(21) + +/* RCC_MP_APB6LPENSETR register fields */ +#define RCC_MP_APB6LPENSETR_USART1LPEN BIT(0) +#define RCC_MP_APB6LPENSETR_USART2LPEN BIT(1) +#define RCC_MP_APB6LPENSETR_SPI4LPEN BIT(2) +#define RCC_MP_APB6LPENSETR_SPI5LPEN BIT(3) +#define RCC_MP_APB6LPENSETR_I2C3LPEN BIT(4) +#define RCC_MP_APB6LPENSETR_I2C4LPEN BIT(5) +#define RCC_MP_APB6LPENSETR_I2C5LPEN BIT(6) +#define RCC_MP_APB6LPENSETR_TIM12LPEN BIT(7) +#define RCC_MP_APB6LPENSETR_TIM13LPEN BIT(8) +#define RCC_MP_APB6LPENSETR_TIM14LPEN BIT(9) +#define RCC_MP_APB6LPENSETR_TIM15LPEN BIT(10) +#define RCC_MP_APB6LPENSETR_TIM16LPEN BIT(11) +#define RCC_MP_APB6LPENSETR_TIM17LPEN BIT(12) + +/* RCC_MP_APB6LPENCLRR register fields */ +#define RCC_MP_APB6LPENCLRR_USART1LPEN BIT(0) +#define RCC_MP_APB6LPENCLRR_USART2LPEN BIT(1) +#define RCC_MP_APB6LPENCLRR_SPI4LPEN BIT(2) +#define RCC_MP_APB6LPENCLRR_SPI5LPEN BIT(3) +#define RCC_MP_APB6LPENCLRR_I2C3LPEN BIT(4) +#define RCC_MP_APB6LPENCLRR_I2C4LPEN BIT(5) +#define RCC_MP_APB6LPENCLRR_I2C5LPEN BIT(6) +#define RCC_MP_APB6LPENCLRR_TIM12LPEN BIT(7) +#define RCC_MP_APB6LPENCLRR_TIM13LPEN BIT(8) +#define RCC_MP_APB6LPENCLRR_TIM14LPEN BIT(9) +#define RCC_MP_APB6LPENCLRR_TIM15LPEN BIT(10) +#define RCC_MP_APB6LPENCLRR_TIM16LPEN BIT(11) +#define RCC_MP_APB6LPENCLRR_TIM17LPEN BIT(12) + +/* RCC_MP_AHB2LPENSETR register fields */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENSETR_DMAMUX1LPEN BIT(2) +#define RCC_MP_AHB2LPENSETR_DMA3LPEN BIT(3) +#define RCC_MP_AHB2LPENSETR_DMAMUX2LPEN BIT(4) +#define RCC_MP_AHB2LPENSETR_ADC1LPEN BIT(5) +#define RCC_MP_AHB2LPENSETR_ADC2LPEN BIT(6) +#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) + +/* RCC_MP_AHB2LPENCLRR register fields */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENCLRR_DMAMUX1LPEN BIT(2) +#define RCC_MP_AHB2LPENCLRR_DMA3LPEN BIT(3) +#define RCC_MP_AHB2LPENCLRR_DMAMUX2LPEN BIT(4) +#define RCC_MP_AHB2LPENCLRR_ADC1LPEN BIT(5) +#define RCC_MP_AHB2LPENCLRR_ADC2LPEN BIT(6) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) + +/* RCC_MP_AHB4LPENSETR register fields */ +#define RCC_MP_AHB4LPENSETR_TSCLPEN BIT(15) + +/* RCC_MP_AHB4LPENCLRR register fields */ +#define RCC_MP_AHB4LPENCLRR_TSCLPEN BIT(15) + +/* RCC_MP_S_AHB4LPENSETR register fields */ +#define RCC_MP_S_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MP_S_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MP_S_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MP_S_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MP_S_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MP_S_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MP_S_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MP_S_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MP_S_AHB4LPENSETR_GPIOILPEN BIT(8) + +/* RCC_MP_S_AHB4LPENCLRR register fields */ +#define RCC_MP_S_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MP_S_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MP_S_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MP_S_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MP_S_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MP_S_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MP_S_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MP_S_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MP_S_AHB4LPENCLRR_GPIOILPEN BIT(8) + +/* RCC_MP_NS_AHB4LPENSETR register fields */ +#define RCC_MP_NS_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MP_NS_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MP_NS_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MP_NS_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MP_NS_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MP_NS_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MP_NS_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MP_NS_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MP_NS_AHB4LPENSETR_GPIOILPEN BIT(8) + +/* RCC_MP_NS_AHB4LPENCLRR register fields */ +#define RCC_MP_NS_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MP_NS_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOILPEN BIT(8) + +/* RCC_MP_AHB5LPENSETR register fields */ +#define RCC_MP_AHB5LPENSETR_PKALPEN BIT(2) +#define RCC_MP_AHB5LPENSETR_SAESLPEN BIT(3) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB5LPENCLRR register fields */ +#define RCC_MP_AHB5LPENCLRR_PKALPEN BIT(2) +#define RCC_MP_AHB5LPENCLRR_SAESLPEN BIT(3) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB6LPENSETR register fields */ +#define RCC_MP_AHB6LPENSETR_MCELPEN BIT(1) +#define RCC_MP_AHB6LPENSETR_ETH1CKLPEN BIT(7) +#define RCC_MP_AHB6LPENSETR_ETH1TXLPEN BIT(8) +#define RCC_MP_AHB6LPENSETR_ETH1RXLPEN BIT(9) +#define RCC_MP_AHB6LPENSETR_ETH1MACLPEN BIT(10) +#define RCC_MP_AHB6LPENSETR_ETH1STPEN BIT(11) +#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) +#define RCC_MP_AHB6LPENSETR_ETH2CKLPEN BIT(27) +#define RCC_MP_AHB6LPENSETR_ETH2TXLPEN BIT(28) +#define RCC_MP_AHB6LPENSETR_ETH2RXLPEN BIT(29) +#define RCC_MP_AHB6LPENSETR_ETH2MACLPEN BIT(30) +#define RCC_MP_AHB6LPENSETR_ETH2STPEN BIT(31) + +/* RCC_MP_AHB6LPENCLRR register fields */ +#define RCC_MP_AHB6LPENCLRR_MCELPEN BIT(1) +#define RCC_MP_AHB6LPENCLRR_ETH1CKLPEN BIT(7) +#define RCC_MP_AHB6LPENCLRR_ETH1TXLPEN BIT(8) +#define RCC_MP_AHB6LPENCLRR_ETH1RXLPEN BIT(9) +#define RCC_MP_AHB6LPENCLRR_ETH1MACLPEN BIT(10) +#define RCC_MP_AHB6LPENCLRR_ETH1STPEN BIT(11) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) +#define RCC_MP_AHB6LPENCLRR_ETH2CKLPEN BIT(27) +#define RCC_MP_AHB6LPENCLRR_ETH2TXLPEN BIT(28) +#define RCC_MP_AHB6LPENCLRR_ETH2RXLPEN BIT(29) +#define RCC_MP_AHB6LPENCLRR_ETH2MACLPEN BIT(30) +#define RCC_MP_AHB6LPENCLRR_ETH2STPEN BIT(31) + +/* RCC_MP_S_AHB6LPENSETR register fields */ +#define RCC_MP_S_AHB6LPENSETR_MDMALPEN BIT(0) + +/* RCC_MP_S_AHB6LPENCLRR register fields */ +#define RCC_MP_S_AHB6LPENCLRR_MDMALPEN BIT(0) + +/* RCC_MP_NS_AHB6LPENSETR register fields */ +#define RCC_MP_NS_AHB6LPENSETR_MDMALPEN BIT(0) + +/* RCC_MP_NS_AHB6LPENCLRR register fields */ +#define RCC_MP_NS_AHB6LPENCLRR_MDMALPEN BIT(0) + +/* RCC_MP_S_AXIMLPENSETR register fields */ +#define RCC_MP_S_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MP_S_AXIMLPENCLRR register fields */ +#define RCC_MP_S_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MP_NS_AXIMLPENSETR register fields */ +#define RCC_MP_NS_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MP_NS_AXIMLPENCLRR register fields */ +#define RCC_MP_NS_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MP_MLAHBLPENSETR register fields */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENSETR_SRAM3LPEN BIT(2) + +/* RCC_MP_MLAHBLPENCLRR register fields */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENCLRR_SRAM3LPEN BIT(2) + +/* RCC_APB3SECSR register fields */ +#define RCC_APB3SECSR_LPTIM2SECF BIT(0) +#define RCC_APB3SECSR_LPTIM3SECF BIT(1) +#define RCC_APB3SECSR_VREFSECF BIT(13) + +/* RCC_APB4SECSR register fields */ +#define RCC_APB4SECSR_DCMIPPSECF BIT(1) +#define RCC_APB4SECSR_USBPHYSECF BIT(16) + +/* RCC_APB5SECSR register fields */ +#define RCC_APB5SECSR_RTCSECF BIT(8) +#define RCC_APB5SECSR_TZCSECF BIT(11) +#define RCC_APB5SECSR_ETZPCSECF BIT(13) +#define RCC_APB5SECSR_IWDG1SECF BIT(15) +#define RCC_APB5SECSR_BSECSECF BIT(16) +#define RCC_APB5SECSR_STGENCSECF_MASK GENMASK(21, 20) +#define RCC_APB5SECSR_STGENCSECF_SHIFT 20 + +/* RCC_APB6SECSR register fields */ +#define RCC_APB6SECSR_USART1SECF BIT(0) +#define RCC_APB6SECSR_USART2SECF BIT(1) +#define RCC_APB6SECSR_SPI4SECF BIT(2) +#define RCC_APB6SECSR_SPI5SECF BIT(3) +#define RCC_APB6SECSR_I2C3SECF BIT(4) +#define RCC_APB6SECSR_I2C4SECF BIT(5) +#define RCC_APB6SECSR_I2C5SECF BIT(6) +#define RCC_APB6SECSR_TIM12SECF BIT(7) +#define RCC_APB6SECSR_TIM13SECF BIT(8) +#define RCC_APB6SECSR_TIM14SECF BIT(9) +#define RCC_APB6SECSR_TIM15SECF BIT(10) +#define RCC_APB6SECSR_TIM16SECF BIT(11) +#define RCC_APB6SECSR_TIM17SECF BIT(12) + +/* RCC_AHB2SECSR register fields */ +#define RCC_AHB2SECSR_DMA3SECF BIT(3) +#define RCC_AHB2SECSR_DMAMUX2SECF BIT(4) +#define RCC_AHB2SECSR_ADC1SECF BIT(5) +#define RCC_AHB2SECSR_ADC2SECF BIT(6) +#define RCC_AHB2SECSR_USBOSECF BIT(8) + +/* RCC_AHB4SECSR register fields */ +#define RCC_AHB4SECSR_TSCSECF BIT(15) + +/* RCC_AHB5SECSR register fields */ +#define RCC_AHB5SECSR_PKASECF BIT(2) +#define RCC_AHB5SECSR_SAESSECF BIT(3) +#define RCC_AHB5SECSR_CRYP1SECF BIT(4) +#define RCC_AHB5SECSR_HASH1SECF BIT(5) +#define RCC_AHB5SECSR_RNG1SECF BIT(6) +#define RCC_AHB5SECSR_BKPSRAMSECF BIT(8) + +/* RCC_AHB6SECSR register fields */ +#define RCC_AHB6SECSR_MCESECF BIT(1) +#define RCC_AHB6SECSR_ETH1SECF_MASK GENMASK(11, 7) +#define RCC_AHB6SECSR_ETH1SECF_SHIFT 7 +#define RCC_AHB6SECSR_FMCSECF BIT(12) +#define RCC_AHB6SECSR_QSPISECF BIT(14) +#define RCC_AHB6SECSR_SDMMC1SECF BIT(16) +#define RCC_AHB6SECSR_SDMMC2SECF BIT(17) +#define RCC_AHB6SECSR_ETH2SECF_MASK GENMASK(31, 27) +#define RCC_AHB6SECSR_ETH2SECF_SHIFT 27 + +/* RCC_VERR register fields */ +#define RCC_VERR_MINREV_MASK GENMASK(3, 0) +#define RCC_VERR_MINREV_SHIFT 0 +#define RCC_VERR_MAJREV_MASK GENMASK(7, 4) +#define RCC_VERR_MAJREV_SHIFT 4 + +/* RCC_IDR register fields */ +#define RCC_IDR_ID_MASK GENMASK(31, 0) +#define RCC_IDR_ID_SHIFT 0 + +/* RCC_SIDR register fields */ +#define RCC_SIDR_SID_MASK GENMASK(31, 0) +#define RCC_SIDR_SID_SHIFT 0 + +/* Used for all RCC_PLLCR registers */ +#define RCC_PLLNCR_PLLON BIT(0) +#define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) +#define RCC_PLLNCR_DIVPEN BIT(4) +#define RCC_PLLNCR_DIVQEN BIT(5) +#define RCC_PLLNCR_DIVREN BIT(6) +#define RCC_PLLNCR_DIVEN_SHIFT 4 + +/* Used for all RCC_PLLCFGR1 registers */ +#define RCC_PLLNCFGR1_DIVM_SHIFT 16 +#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) +#define RCC_PLLNCFGR1_DIVN_SHIFT 0 +#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) + +/* Only for PLL3 and PLL4 */ +#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 +#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) + +/* Used for all RCC_PLLCFGR2 registers */ +#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_SHIFT 0 +#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVQ_SHIFT 8 +#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLLNCFGR2_DIVR_SHIFT 16 +#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) + +/* Used for all RCC_PLLFRACR registers */ +#define RCC_PLLNFRACR_FRACV_SHIFT 3 +#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLLNFRACR_FRACLE BIT(16) + +/* Used for all RCC_PLLCSGR registers */ +#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 +#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 +#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 +#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) + +/* Used for most of RCC_SELR registers */ +#define RCC_SELR_SRC_MASK GENMASK(2, 0) +#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) +#define RCC_SELR_SRCRDY BIT(31) + +/* Values of RCC_MPCKSELR register */ +#define RCC_MPCKSELR_HSI 0x00000000 +#define RCC_MPCKSELR_HSE 0x00000001 +#define RCC_MPCKSELR_PLL 0x00000002 +#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 + +/* Values of RCC_ASSCKSELR register */ +#define RCC_ASSCKSELR_HSI 0x00000000 +#define RCC_ASSCKSELR_HSE 0x00000001 +#define RCC_ASSCKSELR_PLL 0x00000002 + +/* Values of RCC_MSSCKSELR register */ +#define RCC_MSSCKSELR_HSI 0x00000000 +#define RCC_MSSCKSELR_HSE 0x00000001 +#define RCC_MSSCKSELR_CSI 0x00000002 +#define RCC_MSSCKSELR_PLL 0x00000003 + +/* Values of RCC_CPERCKSELR register */ +#define RCC_CPERCKSELR_HSI 0x00000000 +#define RCC_CPERCKSELR_CSI 0x00000001 +#define RCC_CPERCKSELR_HSE 0x00000002 + +/* Used for most of DIVR register: max div for RTC */ +#define RCC_DIVR_DIV_MASK GENMASK(5, 0) +#define RCC_DIVR_DIVRDY BIT(31) + +/* Masks for specific DIVR registers */ +#define RCC_APBXDIV_MASK GENMASK(2, 0) +#define RCC_MPUDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MLAHBDIV_MASK GENMASK(3, 0) + +/* Used for TIMER Prescaler */ +#define RCC_TIMGXPRER_TIMGXPRE BIT(0) + +/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET U(4) + +/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ +#define RCC_RSTCLRR_OFFSET U(4) + +/* RCC_OCENSETR register fields */ +#define RCC_OCENR_HSION BIT(0) +#define RCC_OCENR_HSIKERON BIT(1) +#define RCC_OCENR_CSION BIT(4) +#define RCC_OCENR_CSIKERON BIT(5) +#define RCC_OCENR_DIGBYP BIT(7) +#define RCC_OCENR_HSEON BIT(8) +#define RCC_OCENR_HSEKERON BIT(9) +#define RCC_OCENR_HSEBYP BIT(10) +#define RCC_OCENR_HSECSSON BIT(11) + +#define RCC_OCENR_DIGBYP_BIT 7 +#define RCC_OCENR_HSEBYP_BIT 10 +#define RCC_OCENR_HSECSSON_BIT 11 + +/* Used for RCC_MCO related operations */ +#define RCC_MCOCFG_MCOON BIT(12) +#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) +#define RCC_MCOCFG_MCODIV_SHIFT 4 +#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) + +#define RCC_UART4CKSELR_HSI 0x00000002 + +#define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_PERSRC_SHIFT 0 + +#define RCC_USBCKSELR_USBOSRC_MASK BIT(4) +#define RCC_USBCKSELR_USBOSRC_SHIFT 4 + +#define RCC_DDRITFCR_DDRCKMOD_SSR 0 +#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) +#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) + +#define RCC_DDRITFCR_DDRC2EN BIT(0) +#define RCC_DDRITFCR_DDRC2LPEN BIT(1) + +#define RCC_MP_CIFR_MASK U(0x110F1F) +#define RCC_OFFSET_MASK GENMASK(11, 0) + +#endif /* STM32MP1_RCC_H */ diff --git a/include/drivers/st/stm32mp15_rcc.h b/include/drivers/st/stm32mp15_rcc.h new file mode 100644 index 000000000..ddc0397d7 --- /dev/null +++ b/include/drivers/st/stm32mp15_rcc.h @@ -0,0 +1,2328 @@ +/* + * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_RCC_H +#define STM32MP1_RCC_H + +#include + +#define RCC_TZCR U(0x00) +#define RCC_OCENSETR U(0x0C) +#define RCC_OCENCLRR U(0x10) +#define RCC_HSICFGR U(0x18) +#define RCC_CSICFGR U(0x1C) +#define RCC_MPCKSELR U(0x20) +#define RCC_ASSCKSELR U(0x24) +#define RCC_RCK12SELR U(0x28) +#define RCC_MPCKDIVR U(0x2C) +#define RCC_AXIDIVR U(0x30) +#define RCC_APB4DIVR U(0x3C) +#define RCC_APB5DIVR U(0x40) +#define RCC_RTCDIVR U(0x44) +#define RCC_MSSCKSELR U(0x48) +#define RCC_PLL1CR U(0x80) +#define RCC_PLL1CFGR1 U(0x84) +#define RCC_PLL1CFGR2 U(0x88) +#define RCC_PLL1FRACR U(0x8C) +#define RCC_PLL1CSGR U(0x90) +#define RCC_PLL2CR U(0x94) +#define RCC_PLL2CFGR1 U(0x98) +#define RCC_PLL2CFGR2 U(0x9C) +#define RCC_PLL2FRACR U(0xA0) +#define RCC_PLL2CSGR U(0xA4) +#define RCC_I2C46CKSELR U(0xC0) +#define RCC_SPI6CKSELR U(0xC4) +#define RCC_UART1CKSELR U(0xC8) +#define RCC_RNG1CKSELR U(0xCC) +#define RCC_CPERCKSELR U(0xD0) +#define RCC_STGENCKSELR U(0xD4) +#define RCC_DDRITFCR U(0xD8) +#define RCC_MP_BOOTCR U(0x100) +#define RCC_MP_SREQSETR U(0x104) +#define RCC_MP_SREQCLRR U(0x108) +#define RCC_MP_GCR U(0x10C) +#define RCC_MP_APRSTCR U(0x110) +#define RCC_MP_APRSTSR U(0x114) +#define RCC_BDCR U(0x140) +#define RCC_RDLSICR U(0x144) +#define RCC_APB4RSTSETR U(0x180) +#define RCC_APB4RSTCLRR U(0x184) +#define RCC_APB5RSTSETR U(0x188) +#define RCC_APB5RSTCLRR U(0x18C) +#define RCC_AHB5RSTSETR U(0x190) +#define RCC_AHB5RSTCLRR U(0x194) +#define RCC_AHB6RSTSETR U(0x198) +#define RCC_AHB6RSTCLRR U(0x19C) +#define RCC_TZAHB6RSTSETR U(0x1A0) +#define RCC_TZAHB6RSTCLRR U(0x1A4) +#define RCC_MP_APB4ENSETR U(0x200) +#define RCC_MP_APB4ENCLRR U(0x204) +#define RCC_MP_APB5ENSETR U(0x208) +#define RCC_MP_APB5ENCLRR U(0x20C) +#define RCC_MP_AHB5ENSETR U(0x210) +#define RCC_MP_AHB5ENCLRR U(0x214) +#define RCC_MP_AHB6ENSETR U(0x218) +#define RCC_MP_AHB6ENCLRR U(0x21C) +#define RCC_MP_TZAHB6ENSETR U(0x220) +#define RCC_MP_TZAHB6ENCLRR U(0x224) +#define RCC_MC_APB4ENSETR U(0x280) +#define RCC_MC_APB4ENCLRR U(0x284) +#define RCC_MC_APB5ENSETR U(0x288) +#define RCC_MC_APB5ENCLRR U(0x28C) +#define RCC_MC_AHB5ENSETR U(0x290) +#define RCC_MC_AHB5ENCLRR U(0x294) +#define RCC_MC_AHB6ENSETR U(0x298) +#define RCC_MC_AHB6ENCLRR U(0x29C) +#define RCC_MP_APB4LPENSETR U(0x300) +#define RCC_MP_APB4LPENCLRR U(0x304) +#define RCC_MP_APB5LPENSETR U(0x308) +#define RCC_MP_APB5LPENCLRR U(0x30C) +#define RCC_MP_AHB5LPENSETR U(0x310) +#define RCC_MP_AHB5LPENCLRR U(0x314) +#define RCC_MP_AHB6LPENSETR U(0x318) +#define RCC_MP_AHB6LPENCLRR U(0x31C) +#define RCC_MP_TZAHB6LPENSETR U(0x320) +#define RCC_MP_TZAHB6LPENCLRR U(0x324) +#define RCC_MC_APB4LPENSETR U(0x380) +#define RCC_MC_APB4LPENCLRR U(0x384) +#define RCC_MC_APB5LPENSETR U(0x388) +#define RCC_MC_APB5LPENCLRR U(0x38C) +#define RCC_MC_AHB5LPENSETR U(0x390) +#define RCC_MC_AHB5LPENCLRR U(0x394) +#define RCC_MC_AHB6LPENSETR U(0x398) +#define RCC_MC_AHB6LPENCLRR U(0x39C) +#define RCC_BR_RSTSCLRR U(0x400) +#define RCC_MP_GRSTCSETR U(0x404) +#define RCC_MP_RSTSCLRR U(0x408) +#define RCC_MP_IWDGFZSETR U(0x40C) +#define RCC_MP_IWDGFZCLRR U(0x410) +#define RCC_MP_CIER U(0x414) +#define RCC_MP_CIFR U(0x418) +#define RCC_PWRLPDLYCR U(0x41C) +#define RCC_MP_RSTSSETR U(0x420) +#define RCC_MCO1CFGR U(0x800) +#define RCC_MCO2CFGR U(0x804) +#define RCC_OCRDYR U(0x808) +#define RCC_DBGCFGR U(0x80C) +#define RCC_RCK3SELR U(0x820) +#define RCC_RCK4SELR U(0x824) +#define RCC_TIMG1PRER U(0x828) +#define RCC_TIMG2PRER U(0x82C) +#define RCC_MCUDIVR U(0x830) +#define RCC_APB1DIVR U(0x834) +#define RCC_APB2DIVR U(0x838) +#define RCC_APB3DIVR U(0x83C) +#define RCC_PLL3CR U(0x880) +#define RCC_PLL3CFGR1 U(0x884) +#define RCC_PLL3CFGR2 U(0x888) +#define RCC_PLL3FRACR U(0x88C) +#define RCC_PLL3CSGR U(0x890) +#define RCC_PLL4CR U(0x894) +#define RCC_PLL4CFGR1 U(0x898) +#define RCC_PLL4CFGR2 U(0x89C) +#define RCC_PLL4FRACR U(0x8A0) +#define RCC_PLL4CSGR U(0x8A4) +#define RCC_I2C12CKSELR U(0x8C0) +#define RCC_I2C35CKSELR U(0x8C4) +#define RCC_SAI1CKSELR U(0x8C8) +#define RCC_SAI2CKSELR U(0x8CC) +#define RCC_SAI3CKSELR U(0x8D0) +#define RCC_SAI4CKSELR U(0x8D4) +#define RCC_SPI2S1CKSELR U(0x8D8) +#define RCC_SPI2S23CKSELR U(0x8DC) +#define RCC_SPI45CKSELR U(0x8E0) +#define RCC_UART6CKSELR U(0x8E4) +#define RCC_UART24CKSELR U(0x8E8) +#define RCC_UART35CKSELR U(0x8EC) +#define RCC_UART78CKSELR U(0x8F0) +#define RCC_SDMMC12CKSELR U(0x8F4) +#define RCC_SDMMC3CKSELR U(0x8F8) +#define RCC_ETHCKSELR U(0x8FC) +#define RCC_QSPICKSELR U(0x900) +#define RCC_FMCCKSELR U(0x904) +#define RCC_FDCANCKSELR U(0x90C) +#define RCC_SPDIFCKSELR U(0x914) +#define RCC_CECCKSELR U(0x918) +#define RCC_USBCKSELR U(0x91C) +#define RCC_RNG2CKSELR U(0x920) +#define RCC_DSICKSELR U(0x924) +#define RCC_ADCCKSELR U(0x928) +#define RCC_LPTIM45CKSELR U(0x92C) +#define RCC_LPTIM23CKSELR U(0x930) +#define RCC_LPTIM1CKSELR U(0x934) +#define RCC_APB1RSTSETR U(0x980) +#define RCC_APB1RSTCLRR U(0x984) +#define RCC_APB2RSTSETR U(0x988) +#define RCC_APB2RSTCLRR U(0x98C) +#define RCC_APB3RSTSETR U(0x990) +#define RCC_APB3RSTCLRR U(0x994) +#define RCC_AHB2RSTSETR U(0x998) +#define RCC_AHB2RSTCLRR U(0x99C) +#define RCC_AHB3RSTSETR U(0x9A0) +#define RCC_AHB3RSTCLRR U(0x9A4) +#define RCC_AHB4RSTSETR U(0x9A8) +#define RCC_AHB4RSTCLRR U(0x9AC) +#define RCC_MP_APB1ENSETR U(0xA00) +#define RCC_MP_APB1ENCLRR U(0xA04) +#define RCC_MP_APB2ENSETR U(0xA08) +#define RCC_MP_APB2ENCLRR U(0xA0C) +#define RCC_MP_APB3ENSETR U(0xA10) +#define RCC_MP_APB3ENCLRR U(0xA14) +#define RCC_MP_AHB2ENSETR U(0xA18) +#define RCC_MP_AHB2ENCLRR U(0xA1C) +#define RCC_MP_AHB3ENSETR U(0xA20) +#define RCC_MP_AHB3ENCLRR U(0xA24) +#define RCC_MP_AHB4ENSETR U(0xA28) +#define RCC_MP_AHB4ENCLRR U(0xA2C) +#define RCC_MP_MLAHBENSETR U(0xA38) +#define RCC_MP_MLAHBENCLRR U(0xA3C) +#define RCC_MC_APB1ENSETR U(0xA80) +#define RCC_MC_APB1ENCLRR U(0xA84) +#define RCC_MC_APB2ENSETR U(0xA88) +#define RCC_MC_APB2ENCLRR U(0xA8C) +#define RCC_MC_APB3ENSETR U(0xA90) +#define RCC_MC_APB3ENCLRR U(0xA94) +#define RCC_MC_AHB2ENSETR U(0xA98) +#define RCC_MC_AHB2ENCLRR U(0xA9C) +#define RCC_MC_AHB3ENSETR U(0xAA0) +#define RCC_MC_AHB3ENCLRR U(0xAA4) +#define RCC_MC_AHB4ENSETR U(0xAA8) +#define RCC_MC_AHB4ENCLRR U(0xAAC) +#define RCC_MC_AXIMENSETR U(0xAB0) +#define RCC_MC_AXIMENCLRR U(0xAB4) +#define RCC_MC_MLAHBENSETR U(0xAB8) +#define RCC_MC_MLAHBENCLRR U(0xABC) +#define RCC_MP_APB1LPENSETR U(0xB00) +#define RCC_MP_APB1LPENCLRR U(0xB04) +#define RCC_MP_APB2LPENSETR U(0xB08) +#define RCC_MP_APB2LPENCLRR U(0xB0C) +#define RCC_MP_APB3LPENSETR U(0xB10) +#define RCC_MP_APB3LPENCLRR U(0xB14) +#define RCC_MP_AHB2LPENSETR U(0xB18) +#define RCC_MP_AHB2LPENCLRR U(0xB1C) +#define RCC_MP_AHB3LPENSETR U(0xB20) +#define RCC_MP_AHB3LPENCLRR U(0xB24) +#define RCC_MP_AHB4LPENSETR U(0xB28) +#define RCC_MP_AHB4LPENCLRR U(0xB2C) +#define RCC_MP_AXIMLPENSETR U(0xB30) +#define RCC_MP_AXIMLPENCLRR U(0xB34) +#define RCC_MP_MLAHBLPENSETR U(0xB38) +#define RCC_MP_MLAHBLPENCLRR U(0xB3C) +#define RCC_MC_APB1LPENSETR U(0xB80) +#define RCC_MC_APB1LPENCLRR U(0xB84) +#define RCC_MC_APB2LPENSETR U(0xB88) +#define RCC_MC_APB2LPENCLRR U(0xB8C) +#define RCC_MC_APB3LPENSETR U(0xB90) +#define RCC_MC_APB3LPENCLRR U(0xB94) +#define RCC_MC_AHB2LPENSETR U(0xB98) +#define RCC_MC_AHB2LPENCLRR U(0xB9C) +#define RCC_MC_AHB3LPENSETR U(0xBA0) +#define RCC_MC_AHB3LPENCLRR U(0xBA4) +#define RCC_MC_AHB4LPENSETR U(0xBA8) +#define RCC_MC_AHB4LPENCLRR U(0xBAC) +#define RCC_MC_AXIMLPENSETR U(0xBB0) +#define RCC_MC_AXIMLPENCLRR U(0xBB4) +#define RCC_MC_MLAHBLPENSETR U(0xBB8) +#define RCC_MC_MLAHBLPENCLRR U(0xBBC) +#define RCC_MC_RSTSCLRR U(0xC00) +#define RCC_MC_CIER U(0xC14) +#define RCC_MC_CIFR U(0xC18) +#define RCC_VERR U(0xFF4) +#define RCC_IDR U(0xFF8) +#define RCC_SIDR U(0xFFC) + +/* RCC_TZCR register fields */ +#define RCC_TZCR_TZEN BIT(0) +#define RCC_TZCR_MCKPROT BIT(1) + +/* RCC_OCENSETR register fields */ +#define RCC_OCENSETR_HSION BIT(0) +#define RCC_OCENSETR_HSIKERON BIT(1) +#define RCC_OCENSETR_CSION BIT(4) +#define RCC_OCENSETR_CSIKERON BIT(5) +#define RCC_OCENSETR_DIGBYP BIT(7) +#define RCC_OCENSETR_HSEON BIT(8) +#define RCC_OCENSETR_HSEKERON BIT(9) +#define RCC_OCENSETR_HSEBYP BIT(10) +#define RCC_OCENSETR_HSECSSON BIT(11) + +/* RCC_OCENCLRR register fields */ +#define RCC_OCENCLRR_HSION BIT(0) +#define RCC_OCENCLRR_HSIKERON BIT(1) +#define RCC_OCENCLRR_CSION BIT(4) +#define RCC_OCENCLRR_CSIKERON BIT(5) +#define RCC_OCENCLRR_DIGBYP BIT(7) +#define RCC_OCENCLRR_HSEON BIT(8) +#define RCC_OCENCLRR_HSEKERON BIT(9) +#define RCC_OCENCLRR_HSEBYP BIT(10) + +/* RCC_HSICFGR register fields */ +#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) +#define RCC_HSICFGR_HSIDIV_SHIFT 0 +#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) +#define RCC_HSICFGR_HSITRIM_SHIFT 8 +#define RCC_HSICFGR_HSICAL_MASK GENMASK(24, 16) +#define RCC_HSICFGR_HSICAL_SHIFT 16 +#define RCC_HSICFGR_HSICAL_TEMP_MASK GENMASK(27, 25) + +/* RCC_CSICFGR register fields */ +#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) +#define RCC_CSICFGR_CSITRIM_SHIFT 8 +#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) +#define RCC_CSICFGR_CSICAL_SHIFT 16 + +/* RCC_MPCKSELR register fields */ +#define RCC_MPCKSELR_HSI 0x00000000 +#define RCC_MPCKSELR_HSE 0x00000001 +#define RCC_MPCKSELR_PLL 0x00000002 +#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 +#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) +#define RCC_MPCKSELR_MPUSRC_SHIFT 0 +#define RCC_MPCKSELR_MPUSRCRDY BIT(31) + +/* RCC_ASSCKSELR register fields */ +#define RCC_ASSCKSELR_HSI 0x00000000 +#define RCC_ASSCKSELR_HSE 0x00000001 +#define RCC_ASSCKSELR_PLL 0x00000002 +#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) +#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 +#define RCC_ASSCKSELR_AXISSRCRDY BIT(31) + +/* RCC_RCK12SELR register fields */ +#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) +#define RCC_RCK12SELR_PLL12SRC_SHIFT 0 +#define RCC_RCK12SELR_PLL12SRCRDY BIT(31) + +/* RCC_MPCKDIVR register fields */ +#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(2, 0) +#define RCC_MPCKDIVR_MPUDIV_SHIFT 0 +#define RCC_MPCKDIVR_MPUDIVRDY BIT(31) + +/* RCC_AXIDIVR register fields */ +#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIVR_AXIDIV_SHIFT 0 +#define RCC_AXIDIVR_AXIDIVRDY BIT(31) + +/* RCC_APB4DIVR register fields */ +#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) +#define RCC_APB4DIVR_APB4DIV_SHIFT 0 +#define RCC_APB4DIVR_APB4DIVRDY BIT(31) + +/* RCC_APB5DIVR register fields */ +#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) +#define RCC_APB5DIVR_APB5DIV_SHIFT 0 +#define RCC_APB5DIVR_APB5DIVRDY BIT(31) + +/* RCC_RTCDIVR register fields */ +#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) +#define RCC_RTCDIVR_RTCDIV_SHIFT 0 + +/* RCC_MSSCKSELR register fields */ +#define RCC_MSSCKSELR_HSI 0x00000000 +#define RCC_MSSCKSELR_HSE 0x00000001 +#define RCC_MSSCKSELR_CSI 0x00000002 +#define RCC_MSSCKSELR_PLL 0x00000003 +#define RCC_MSSCKSELR_MCUSSRC_MASK GENMASK(1, 0) +#define RCC_MSSCKSELR_MCUSSRC_SHIFT 0 +#define RCC_MSSCKSELR_MCUSSRCRDY BIT(31) + +/* RCC_PLL1CR register fields */ +#define RCC_PLL1CR_PLLON BIT(0) +#define RCC_PLL1CR_PLL1RDY BIT(1) +#define RCC_PLL1CR_SSCG_CTRL BIT(2) +#define RCC_PLL1CR_DIVPEN BIT(4) +#define RCC_PLL1CR_DIVQEN BIT(5) +#define RCC_PLL1CR_DIVREN BIT(6) + +/* RCC_PLL1CFGR1 register fields */ +#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL1CFGR1_DIVN_SHIFT 0 +#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) +#define RCC_PLL1CFGR1_DIVM1_SHIFT 16 + +/* RCC_PLL1CFGR2 register fields */ +#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL1CFGR2_DIVP_SHIFT 0 +#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL1CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL1CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL1FRACR register fields */ +#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL1FRACR_FRACV_SHIFT 3 +#define RCC_PLL1FRACR_FRACLE BIT(16) + +/* RCC_PLL1CSGR register fields */ +#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL1CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL1CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL1CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL1CSGR_SSCG_MODE BIT(15) +#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL1CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL2CR register fields */ +#define RCC_PLL2CR_PLLON BIT(0) +#define RCC_PLL2CR_PLL2RDY BIT(1) +#define RCC_PLL2CR_SSCG_CTRL BIT(2) +#define RCC_PLL2CR_DIVPEN BIT(4) +#define RCC_PLL2CR_DIVQEN BIT(5) +#define RCC_PLL2CR_DIVREN BIT(6) + +/* RCC_PLL2CFGR1 register fields */ +#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL2CFGR1_DIVN_SHIFT 0 +#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) +#define RCC_PLL2CFGR1_DIVM2_SHIFT 16 + +/* RCC_PLL2CFGR2 register fields */ +#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL2CFGR2_DIVP_SHIFT 0 +#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL2CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL2CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL2FRACR register fields */ +#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL2FRACR_FRACV_SHIFT 3 +#define RCC_PLL2FRACR_FRACLE BIT(16) + +/* RCC_PLL2CSGR register fields */ +#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL2CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL2CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL2CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL2CSGR_SSCG_MODE BIT(15) +#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL2CSGR_INC_STEP_SHIFT 16 + +/* RCC_I2C46CKSELR register fields */ +#define RCC_I2C46CKSELR_I2C46SRC_MASK GENMASK(2, 0) +#define RCC_I2C46CKSELR_I2C46SRC_SHIFT 0 + +/* RCC_SPI6CKSELR register fields */ +#define RCC_SPI6CKSELR_SPI6SRC_MASK GENMASK(2, 0) +#define RCC_SPI6CKSELR_SPI6SRC_SHIFT 0 + +/* RCC_UART1CKSELR register fields */ +#define RCC_UART1CKSELR_UART1SRC_MASK GENMASK(2, 0) +#define RCC_UART1CKSELR_UART1SRC_SHIFT 0 + +/* RCC_RNG1CKSELR register fields */ +#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) +#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 + +/* RCC_CPERCKSELR register fields */ +#define RCC_CPERCKSELR_HSI 0x00000000 +#define RCC_CPERCKSELR_CSI 0x00000001 +#define RCC_CPERCKSELR_HSE 0x00000002 +#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 + +/* RCC_STGENCKSELR register fields */ +#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) +#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 + +/* RCC_DDRITFCR register fields */ +#define RCC_DDRITFCR_DDRC1EN BIT(0) +#define RCC_DDRITFCR_DDRC1LPEN BIT(1) +#define RCC_DDRITFCR_DDRC2EN BIT(2) +#define RCC_DDRITFCR_DDRC2LPEN BIT(3) +#define RCC_DDRITFCR_DDRPHYCEN BIT(4) +#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) +#define RCC_DDRITFCR_DDRCAPBEN BIT(6) +#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) +#define RCC_DDRITFCR_AXIDCGEN BIT(8) +#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) +#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) +#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 +#define RCC_DDRITFCR_DDRCAPBRST BIT(14) +#define RCC_DDRITFCR_DDRCAXIRST BIT(15) +#define RCC_DDRITFCR_DDRCORERST BIT(16) +#define RCC_DDRITFCR_DPHYAPBRST BIT(17) +#define RCC_DDRITFCR_DPHYRST BIT(18) +#define RCC_DDRITFCR_DPHYCTLRST BIT(19) +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 +#define RCC_DDRITFCR_DDRCKMOD_SSR 0 +#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) +#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) +#define RCC_DDRITFCR_GSKPMOD BIT(23) +#define RCC_DDRITFCR_GSKPCTRL BIT(24) +#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) +#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 +#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) +#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 + +/* RCC_MP_BOOTCR register fields */ +#define RCC_MP_BOOTCR_MCU_BEN BIT(0) +#define RCC_MP_BOOTCR_MPU_BEN BIT(1) + +/* RCC_MP_SREQSETR register fields */ +#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) +#define RCC_MP_SREQSETR_STPREQ_P1 BIT(1) + +/* RCC_MP_SREQCLRR register fields */ +#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) +#define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1) + +/* RCC_MP_GCR register fields */ +#define RCC_MP_GCR_BOOT_MCU BIT(0) + +/* RCC_MP_APRSTCR register fields */ +#define RCC_MP_APRSTCR_RDCTLEN BIT(0) +#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) +#define RCC_MP_APRSTCR_RSTTO_SHIFT 8 + +/* RCC_MP_APRSTSR register fields */ +#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) +#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 + +/* RCC_BDCR register fields */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_DIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(8) +#define RCC_BDCR_LSECSSD BIT(9) +#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_VSWRST BIT(31) + +/* RCC_RDLSICR register fields */ +#define RCC_RDLSICR_LSION BIT(0) +#define RCC_RDLSICR_LSIRDY BIT(1) +#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) +#define RCC_RDLSICR_MRD_SHIFT 16 +#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) +#define RCC_RDLSICR_EADLY_SHIFT 24 +#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) +#define RCC_RDLSICR_SPARE_SHIFT 27 + +/* RCC_APB4RSTSETR register fields */ +#define RCC_APB4RSTSETR_LTDCRST BIT(0) +#define RCC_APB4RSTSETR_DSIRST BIT(4) +#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTSETR_USBPHYRST BIT(16) + +/* RCC_APB4RSTCLRR register fields */ +#define RCC_APB4RSTCLRR_LTDCRST BIT(0) +#define RCC_APB4RSTCLRR_DSIRST BIT(4) +#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTCLRR_USBPHYRST BIT(16) + +/* RCC_APB5RSTSETR register fields */ +#define RCC_APB5RSTSETR_SPI6RST BIT(0) +#define RCC_APB5RSTSETR_I2C4RST BIT(2) +#define RCC_APB5RSTSETR_I2C6RST BIT(3) +#define RCC_APB5RSTSETR_USART1RST BIT(4) +#define RCC_APB5RSTSETR_STGENRST BIT(20) + +/* RCC_APB5RSTCLRR register fields */ +#define RCC_APB5RSTCLRR_SPI6RST BIT(0) +#define RCC_APB5RSTCLRR_I2C4RST BIT(2) +#define RCC_APB5RSTCLRR_I2C6RST BIT(3) +#define RCC_APB5RSTCLRR_USART1RST BIT(4) +#define RCC_APB5RSTCLRR_STGENRST BIT(20) + +/* RCC_AHB5RSTSETR register fields */ +#define RCC_AHB5RSTSETR_GPIOZRST BIT(0) +#define RCC_AHB5RSTSETR_CRYP1RST BIT(4) +#define RCC_AHB5RSTSETR_HASH1RST BIT(5) +#define RCC_AHB5RSTSETR_RNG1RST BIT(6) +#define RCC_AHB5RSTSETR_AXIMCRST BIT(16) + +/* RCC_AHB5RSTCLRR register fields */ +#define RCC_AHB5RSTCLRR_GPIOZRST BIT(0) +#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) +#define RCC_AHB5RSTCLRR_HASH1RST BIT(5) +#define RCC_AHB5RSTCLRR_RNG1RST BIT(6) +#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) + +/* RCC_AHB6RSTSETR register fields */ +#define RCC_AHB6RSTSETR_GPURST BIT(5) +#define RCC_AHB6RSTSETR_ETHMACRST BIT(10) +#define RCC_AHB6RSTSETR_FMCRST BIT(12) +#define RCC_AHB6RSTSETR_QSPIRST BIT(14) +#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTSETR_CRC1RST BIT(20) +#define RCC_AHB6RSTSETR_USBHRST BIT(24) + +/* RCC_AHB6RSTCLRR register fields */ +#define RCC_AHB6RSTCLRR_ETHMACRST BIT(10) +#define RCC_AHB6RSTCLRR_FMCRST BIT(12) +#define RCC_AHB6RSTCLRR_QSPIRST BIT(14) +#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTCLRR_CRC1RST BIT(20) +#define RCC_AHB6RSTCLRR_USBHRST BIT(24) + +/* RCC_TZAHB6RSTSETR register fields */ +#define RCC_TZAHB6RSTSETR_MDMARST BIT(0) + +/* RCC_TZAHB6RSTCLRR register fields */ +#define RCC_TZAHB6RSTCLRR_MDMARST BIT(0) + +/* RCC_MP_APB4ENSETR register fields */ +#define RCC_MP_APB4ENSETR_LTDCEN BIT(0) +#define RCC_MP_APB4ENSETR_DSIEN BIT(4) +#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENSETR_STGENROEN BIT(20) + +/* RCC_MP_APB4ENCLRR register fields */ +#define RCC_MP_APB4ENCLRR_LTDCEN BIT(0) +#define RCC_MP_APB4ENCLRR_DSIEN BIT(4) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) + +/* RCC_MP_APB5ENSETR register fields */ +#define RCC_MP_APB5ENSETR_SPI6EN BIT(0) +#define RCC_MP_APB5ENSETR_I2C4EN BIT(2) +#define RCC_MP_APB5ENSETR_I2C6EN BIT(3) +#define RCC_MP_APB5ENSETR_USART1EN BIT(4) +#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENSETR_TZC1EN BIT(11) +#define RCC_MP_APB5ENSETR_TZC2EN BIT(12) +#define RCC_MP_APB5ENSETR_TZPCEN BIT(13) +#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENSETR_BSECEN BIT(16) +#define RCC_MP_APB5ENSETR_STGENEN BIT(20) + +/* RCC_MP_APB5ENCLRR register fields */ +#define RCC_MP_APB5ENCLRR_SPI6EN BIT(0) +#define RCC_MP_APB5ENCLRR_I2C4EN BIT(2) +#define RCC_MP_APB5ENCLRR_I2C6EN BIT(3) +#define RCC_MP_APB5ENCLRR_USART1EN BIT(4) +#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENCLRR_TZC1EN BIT(11) +#define RCC_MP_APB5ENCLRR_TZC2EN BIT(12) +#define RCC_MP_APB5ENCLRR_TZPCEN BIT(13) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENCLRR_BSECEN BIT(16) +#define RCC_MP_APB5ENCLRR_STGENEN BIT(20) + +/* RCC_MP_AHB5ENSETR register fields */ +#define RCC_MP_AHB5ENSETR_GPIOZEN BIT(0) +#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) + +/* RCC_MP_AHB5ENCLRR register fields */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN BIT(0) +#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) + +/* RCC_MP_AHB6ENSETR register fields */ +#define RCC_MP_AHB6ENSETR_MDMAEN BIT(0) +#define RCC_MP_AHB6ENSETR_GPUEN BIT(5) +#define RCC_MP_AHB6ENSETR_ETHCKEN BIT(7) +#define RCC_MP_AHB6ENSETR_ETHTXEN BIT(8) +#define RCC_MP_AHB6ENSETR_ETHRXEN BIT(9) +#define RCC_MP_AHB6ENSETR_ETHMACEN BIT(10) +#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) +#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENSETR_USBHEN BIT(24) + +/* RCC_MP_AHB6ENCLRR register fields */ +#define RCC_MP_AHB6ENCLRR_MDMAEN BIT(0) +#define RCC_MP_AHB6ENCLRR_GPUEN BIT(5) +#define RCC_MP_AHB6ENCLRR_ETHCKEN BIT(7) +#define RCC_MP_AHB6ENCLRR_ETHTXEN BIT(8) +#define RCC_MP_AHB6ENCLRR_ETHRXEN BIT(9) +#define RCC_MP_AHB6ENCLRR_ETHMACEN BIT(10) +#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) +#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) + +/* RCC_MP_TZAHB6ENSETR register fields */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN BIT(0) + +/* RCC_MP_TZAHB6ENCLRR register fields */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN BIT(0) + +/* RCC_MC_APB4ENSETR register fields */ +#define RCC_MC_APB4ENSETR_LTDCEN BIT(0) +#define RCC_MC_APB4ENSETR_DSIEN BIT(4) +#define RCC_MC_APB4ENSETR_DDRPERFMEN BIT(8) +#define RCC_MC_APB4ENSETR_USBPHYEN BIT(16) +#define RCC_MC_APB4ENSETR_STGENROEN BIT(20) + +/* RCC_MC_APB4ENCLRR register fields */ +#define RCC_MC_APB4ENCLRR_LTDCEN BIT(0) +#define RCC_MC_APB4ENCLRR_DSIEN BIT(4) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN BIT(8) +#define RCC_MC_APB4ENCLRR_USBPHYEN BIT(16) +#define RCC_MC_APB4ENCLRR_STGENROEN BIT(20) + +/* RCC_MC_APB5ENSETR register fields */ +#define RCC_MC_APB5ENSETR_SPI6EN BIT(0) +#define RCC_MC_APB5ENSETR_I2C4EN BIT(2) +#define RCC_MC_APB5ENSETR_I2C6EN BIT(3) +#define RCC_MC_APB5ENSETR_USART1EN BIT(4) +#define RCC_MC_APB5ENSETR_RTCAPBEN BIT(8) +#define RCC_MC_APB5ENSETR_TZC1EN BIT(11) +#define RCC_MC_APB5ENSETR_TZC2EN BIT(12) +#define RCC_MC_APB5ENSETR_TZPCEN BIT(13) +#define RCC_MC_APB5ENSETR_BSECEN BIT(16) +#define RCC_MC_APB5ENSETR_STGENEN BIT(20) + +/* RCC_MC_APB5ENCLRR register fields */ +#define RCC_MC_APB5ENCLRR_SPI6EN BIT(0) +#define RCC_MC_APB5ENCLRR_I2C4EN BIT(2) +#define RCC_MC_APB5ENCLRR_I2C6EN BIT(3) +#define RCC_MC_APB5ENCLRR_USART1EN BIT(4) +#define RCC_MC_APB5ENCLRR_RTCAPBEN BIT(8) +#define RCC_MC_APB5ENCLRR_TZC1EN BIT(11) +#define RCC_MC_APB5ENCLRR_TZC2EN BIT(12) +#define RCC_MC_APB5ENCLRR_TZPCEN BIT(13) +#define RCC_MC_APB5ENCLRR_BSECEN BIT(16) +#define RCC_MC_APB5ENCLRR_STGENEN BIT(20) + +/* RCC_MC_AHB5ENSETR register fields */ +#define RCC_MC_AHB5ENSETR_GPIOZEN BIT(0) +#define RCC_MC_AHB5ENSETR_CRYP1EN BIT(4) +#define RCC_MC_AHB5ENSETR_HASH1EN BIT(5) +#define RCC_MC_AHB5ENSETR_RNG1EN BIT(6) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN BIT(8) + +/* RCC_MC_AHB5ENCLRR register fields */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN BIT(0) +#define RCC_MC_AHB5ENCLRR_CRYP1EN BIT(4) +#define RCC_MC_AHB5ENCLRR_HASH1EN BIT(5) +#define RCC_MC_AHB5ENCLRR_RNG1EN BIT(6) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN BIT(8) + +/* RCC_MC_AHB6ENSETR register fields */ +#define RCC_MC_AHB6ENSETR_MDMAEN BIT(0) +#define RCC_MC_AHB6ENSETR_GPUEN BIT(5) +#define RCC_MC_AHB6ENSETR_ETHCKEN BIT(7) +#define RCC_MC_AHB6ENSETR_ETHTXEN BIT(8) +#define RCC_MC_AHB6ENSETR_ETHRXEN BIT(9) +#define RCC_MC_AHB6ENSETR_ETHMACEN BIT(10) +#define RCC_MC_AHB6ENSETR_FMCEN BIT(12) +#define RCC_MC_AHB6ENSETR_QSPIEN BIT(14) +#define RCC_MC_AHB6ENSETR_SDMMC1EN BIT(16) +#define RCC_MC_AHB6ENSETR_SDMMC2EN BIT(17) +#define RCC_MC_AHB6ENSETR_CRC1EN BIT(20) +#define RCC_MC_AHB6ENSETR_USBHEN BIT(24) + +/* RCC_MC_AHB6ENCLRR register fields */ +#define RCC_MC_AHB6ENCLRR_MDMAEN BIT(0) +#define RCC_MC_AHB6ENCLRR_GPUEN BIT(5) +#define RCC_MC_AHB6ENCLRR_ETHCKEN BIT(7) +#define RCC_MC_AHB6ENCLRR_ETHTXEN BIT(8) +#define RCC_MC_AHB6ENCLRR_ETHRXEN BIT(9) +#define RCC_MC_AHB6ENCLRR_ETHMACEN BIT(10) +#define RCC_MC_AHB6ENCLRR_FMCEN BIT(12) +#define RCC_MC_AHB6ENCLRR_QSPIEN BIT(14) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN BIT(16) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN BIT(17) +#define RCC_MC_AHB6ENCLRR_CRC1EN BIT(20) +#define RCC_MC_AHB6ENCLRR_USBHEN BIT(24) + +/* RCC_MP_APB4LPENSETR register fields */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN BIT(0) +#define RCC_MP_APB4LPENSETR_DSILPEN BIT(4) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) + +/* RCC_MP_APB4LPENCLRR register fields */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN BIT(0) +#define RCC_MP_APB4LPENCLRR_DSILPEN BIT(4) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) + +/* RCC_MP_APB5LPENSETR register fields */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN BIT(0) +#define RCC_MP_APB5LPENSETR_I2C4LPEN BIT(2) +#define RCC_MP_APB5LPENSETR_I2C6LPEN BIT(3) +#define RCC_MP_APB5LPENSETR_USART1LPEN BIT(4) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENSETR_TZC1LPEN BIT(11) +#define RCC_MP_APB5LPENSETR_TZC2LPEN BIT(12) +#define RCC_MP_APB5LPENSETR_TZPCLPEN BIT(13) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENSETR_STGENLPEN BIT(20) +#define RCC_MP_APB5LPENSETR_STGENSTPEN BIT(21) + +/* RCC_MP_APB5LPENCLRR register fields */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN BIT(0) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN BIT(2) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN BIT(3) +#define RCC_MP_APB5LPENCLRR_USART1LPEN BIT(4) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN BIT(11) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN BIT(12) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN BIT(13) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENCLRR_STGENLPEN BIT(20) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN BIT(21) + +/* RCC_MP_AHB5LPENSETR register fields */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN BIT(0) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB5LPENCLRR register fields */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN BIT(0) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB6LPENSETR register fields */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN BIT(0) +#define RCC_MP_AHB6LPENSETR_GPULPEN BIT(5) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN BIT(7) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN BIT(8) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN BIT(9) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN BIT(10) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN BIT(11) +#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) + +/* RCC_MP_AHB6LPENCLRR register fields */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN BIT(0) +#define RCC_MP_AHB6LPENCLRR_GPULPEN BIT(5) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN BIT(7) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN BIT(8) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN BIT(9) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN BIT(10) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN BIT(11) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) + +/* RCC_MP_TZAHB6LPENSETR register fields */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN BIT(0) + +/* RCC_MP_TZAHB6LPENCLRR register fields */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN BIT(0) + +/* RCC_MC_APB4LPENSETR register fields */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN BIT(0) +#define RCC_MC_APB4LPENSETR_DSILPEN BIT(4) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN BIT(8) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN BIT(16) +#define RCC_MC_APB4LPENSETR_STGENROLPEN BIT(20) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN BIT(21) + +/* RCC_MC_APB4LPENCLRR register fields */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN BIT(0) +#define RCC_MC_APB4LPENCLRR_DSILPEN BIT(4) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN BIT(8) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN BIT(16) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN BIT(20) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN BIT(21) + +/* RCC_MC_APB5LPENSETR register fields */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN BIT(0) +#define RCC_MC_APB5LPENSETR_I2C4LPEN BIT(2) +#define RCC_MC_APB5LPENSETR_I2C6LPEN BIT(3) +#define RCC_MC_APB5LPENSETR_USART1LPEN BIT(4) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN BIT(8) +#define RCC_MC_APB5LPENSETR_TZC1LPEN BIT(11) +#define RCC_MC_APB5LPENSETR_TZC2LPEN BIT(12) +#define RCC_MC_APB5LPENSETR_TZPCLPEN BIT(13) +#define RCC_MC_APB5LPENSETR_BSECLPEN BIT(16) +#define RCC_MC_APB5LPENSETR_STGENLPEN BIT(20) +#define RCC_MC_APB5LPENSETR_STGENSTPEN BIT(21) + +/* RCC_MC_APB5LPENCLRR register fields */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN BIT(0) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN BIT(2) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN BIT(3) +#define RCC_MC_APB5LPENCLRR_USART1LPEN BIT(4) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN BIT(8) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN BIT(11) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN BIT(12) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN BIT(13) +#define RCC_MC_APB5LPENCLRR_BSECLPEN BIT(16) +#define RCC_MC_APB5LPENCLRR_STGENLPEN BIT(20) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN BIT(21) + +/* RCC_MC_AHB5LPENSETR register fields */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN BIT(0) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN BIT(4) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN BIT(5) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN BIT(6) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN BIT(8) + +/* RCC_MC_AHB5LPENCLRR register fields */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN BIT(0) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN BIT(4) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN BIT(5) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN BIT(6) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) + +/* RCC_MC_AHB6LPENSETR register fields */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN BIT(0) +#define RCC_MC_AHB6LPENSETR_GPULPEN BIT(5) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN BIT(7) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN BIT(8) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN BIT(9) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN BIT(10) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN BIT(11) +#define RCC_MC_AHB6LPENSETR_FMCLPEN BIT(12) +#define RCC_MC_AHB6LPENSETR_QSPILPEN BIT(14) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN BIT(16) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN BIT(17) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN BIT(20) +#define RCC_MC_AHB6LPENSETR_USBHLPEN BIT(24) + +/* RCC_MC_AHB6LPENCLRR register fields */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN BIT(0) +#define RCC_MC_AHB6LPENCLRR_GPULPEN BIT(5) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN BIT(7) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN BIT(8) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN BIT(9) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN BIT(10) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN BIT(11) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN BIT(12) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN BIT(14) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN BIT(16) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN BIT(17) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN BIT(20) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN BIT(24) + +/* RCC_BR_RSTSCLRR register fields */ +#define RCC_BR_RSTSCLRR_PORRSTF BIT(0) +#define RCC_BR_RSTSCLRR_BORRSTF BIT(1) +#define RCC_BR_RSTSCLRR_PADRSTF BIT(2) +#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_BR_RSTSCLRR_MCSYSRSTF BIT(7) +#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) +#define RCC_BR_RSTSCLRR_MPUP1RSTF BIT(14) + +/* RCC_MP_GRSTCSETR register fields */ +#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MCURST BIT(1) +#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) +#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) + +/* RCC_MP_RSTSCLRR register fields */ +#define RCC_MP_RSTSCLRR_PORRSTF BIT(0) +#define RCC_MP_RSTSCLRR_BORRSTF BIT(1) +#define RCC_MP_RSTSCLRR_PADRSTF BIT(2) +#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7) +#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSCLRR_MPUP1RSTF BIT(14) +#define RCC_MP_RSTSCLRR_SPARE BIT(15) + +/* RCC_MP_IWDGFZSETR register fields */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) + +/* RCC_MP_IWDGFZCLRR register fields */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) + +/* RCC_MP_CIER register fields */ +#define RCC_MP_CIER_LSIRDYIE BIT(0) +#define RCC_MP_CIER_LSERDYIE BIT(1) +#define RCC_MP_CIER_HSIRDYIE BIT(2) +#define RCC_MP_CIER_HSERDYIE BIT(3) +#define RCC_MP_CIER_CSIRDYIE BIT(4) +#define RCC_MP_CIER_PLL1DYIE BIT(8) +#define RCC_MP_CIER_PLL2DYIE BIT(9) +#define RCC_MP_CIER_PLL3DYIE BIT(10) +#define RCC_MP_CIER_PLL4DYIE BIT(11) +#define RCC_MP_CIER_LSECSSIE BIT(16) +#define RCC_MP_CIER_WKUPIE BIT(20) + +/* RCC_MP_CIFR register fields */ +#define RCC_MP_CIFR_MASK U(0x110F1F) +#define RCC_MP_CIFR_LSIRDYF BIT(0) +#define RCC_MP_CIFR_LSERDYF BIT(1) +#define RCC_MP_CIFR_HSIRDYF BIT(2) +#define RCC_MP_CIFR_HSERDYF BIT(3) +#define RCC_MP_CIFR_CSIRDYF BIT(4) +#define RCC_MP_CIFR_PLL1DYF BIT(8) +#define RCC_MP_CIFR_PLL2DYF BIT(9) +#define RCC_MP_CIFR_PLL3DYF BIT(10) +#define RCC_MP_CIFR_PLL4DYF BIT(11) +#define RCC_MP_CIFR_LSECSSF BIT(16) +#define RCC_MP_CIFR_WKUPF BIT(20) + +/* RCC_PWRLPDLYCR register fields */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) +#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 +#define RCC_PWRLPDLYCR_MCTMPSKP BIT(24) + +/* RCC_MP_RSTSSETR register fields */ +#define RCC_MP_RSTSSETR_PORRSTF BIT(0) +#define RCC_MP_RSTSSETR_BORRSTF BIT(1) +#define RCC_MP_RSTSSETR_PADRSTF BIT(2) +#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSSETR_VCORERSTF BIT(4) +#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSSETR_MCSYSRSTF BIT(7) +#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSSETR_MPUP1RSTF BIT(14) +#define RCC_MP_RSTSSETR_SPARE BIT(15) + +/* RCC_MCO1CFGR register fields */ +#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) +#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 +#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) +#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 +#define RCC_MCO1CFGR_MCO1ON BIT(12) + +/* RCC_MCO2CFGR register fields */ +#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) +#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 +#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) +#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 +#define RCC_MCO2CFGR_MCO2ON BIT(12) + +/* RCC_OCRDYR register fields */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSIDIVRDY BIT(2) +#define RCC_OCRDYR_CSIRDY BIT(4) +#define RCC_OCRDYR_HSERDY BIT(8) +#define RCC_OCRDYR_MPUCKRDY BIT(23) +#define RCC_OCRDYR_AXICKRDY BIT(24) +#define RCC_OCRDYR_CKREST BIT(25) + +/* RCC_DBGCFGR register fields */ +#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) +#define RCC_DBGCFGR_TRACEDIV_SHIFT 0 +#define RCC_DBGCFGR_DBGCKEN BIT(8) +#define RCC_DBGCFGR_TRACECKEN BIT(9) +#define RCC_DBGCFGR_DBGRST BIT(12) + +/* RCC_RCK3SELR register fields */ +#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) +#define RCC_RCK3SELR_PLL3SRC_SHIFT 0 +#define RCC_RCK3SELR_PLL3SRCRDY BIT(31) + +/* RCC_RCK4SELR register fields */ +#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) +#define RCC_RCK4SELR_PLL4SRC_SHIFT 0 +#define RCC_RCK4SELR_PLL4SRCRDY BIT(31) + +/* RCC_TIMG1PRER register fields */ +#define RCC_TIMG1PRER_TIMG1PRE BIT(0) +#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) + +/* RCC_TIMG2PRER register fields */ +#define RCC_TIMG2PRER_TIMG2PRE BIT(0) +#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) + +/* RCC_MCUDIVR register fields */ +#define RCC_MCUDIVR_MCUDIV_MASK GENMASK(3, 0) +#define RCC_MCUDIVR_MCUDIV_SHIFT 0 +#define RCC_MCUDIVR_MCUDIVRDY BIT(31) + +/* RCC_APB1DIVR register fields */ +#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) +#define RCC_APB1DIVR_APB1DIV_SHIFT 0 +#define RCC_APB1DIVR_APB1DIVRDY BIT(31) + +/* RCC_APB2DIVR register fields */ +#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) +#define RCC_APB2DIVR_APB2DIV_SHIFT 0 +#define RCC_APB2DIVR_APB2DIVRDY BIT(31) + +/* RCC_APB3DIVR register fields */ +#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) +#define RCC_APB3DIVR_APB3DIV_SHIFT 0 +#define RCC_APB3DIVR_APB3DIVRDY BIT(31) + +/* RCC_PLL3CR register fields */ +#define RCC_PLL3CR_PLLON BIT(0) +#define RCC_PLL3CR_PLL3RDY BIT(1) +#define RCC_PLL3CR_SSCG_CTRL BIT(2) +#define RCC_PLL3CR_DIVPEN BIT(4) +#define RCC_PLL3CR_DIVQEN BIT(5) +#define RCC_PLL3CR_DIVREN BIT(6) + +/* RCC_PLL3CFGR1 register fields */ +#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL3CFGR1_DIVN_SHIFT 0 +#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) +#define RCC_PLL3CFGR1_DIVM3_SHIFT 16 +#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL3CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL3CFGR2 register fields */ +#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL3CFGR2_DIVP_SHIFT 0 +#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL3CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL3CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL3FRACR register fields */ +#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL3FRACR_FRACV_SHIFT 3 +#define RCC_PLL3FRACR_FRACLE BIT(16) + +/* RCC_PLL3CSGR register fields */ +#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL3CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL3CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL3CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL3CSGR_SSCG_MODE BIT(15) +#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL3CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL4CR register fields */ +#define RCC_PLL4CR_PLLON BIT(0) +#define RCC_PLL4CR_PLL4RDY BIT(1) +#define RCC_PLL4CR_SSCG_CTRL BIT(2) +#define RCC_PLL4CR_DIVPEN BIT(4) +#define RCC_PLL4CR_DIVQEN BIT(5) +#define RCC_PLL4CR_DIVREN BIT(6) + +/* RCC_PLL4CFGR1 register fields */ +#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL4CFGR1_DIVN_SHIFT 0 +#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) +#define RCC_PLL4CFGR1_DIVM4_SHIFT 16 +#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL4CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL4CFGR2 register fields */ +#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL4CFGR2_DIVP_SHIFT 0 +#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL4CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL4CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL4FRACR register fields */ +#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL4FRACR_FRACV_SHIFT 3 +#define RCC_PLL4FRACR_FRACLE BIT(16) + +/* RCC_PLL4CSGR register fields */ +#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL4CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL4CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL4CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL4CSGR_SSCG_MODE BIT(15) +#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL4CSGR_INC_STEP_SHIFT 16 + +/* RCC_I2C12CKSELR register fields */ +#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) +#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 + +/* RCC_I2C35CKSELR register fields */ +#define RCC_I2C35CKSELR_I2C35SRC_MASK GENMASK(2, 0) +#define RCC_I2C35CKSELR_I2C35SRC_SHIFT 0 + +/* RCC_SAI1CKSELR register fields */ +#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) +#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 + +/* RCC_SAI2CKSELR register fields */ +#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) +#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 + +/* RCC_SAI3CKSELR register fields */ +#define RCC_SAI3CKSELR_SAI3SRC_MASK GENMASK(2, 0) +#define RCC_SAI3CKSELR_SAI3SRC_SHIFT 0 + +/* RCC_SAI4CKSELR register fields */ +#define RCC_SAI4CKSELR_SAI4SRC_MASK GENMASK(2, 0) +#define RCC_SAI4CKSELR_SAI4SRC_SHIFT 0 + +/* RCC_SPI2S1CKSELR register fields */ +#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 + +/* RCC_SPI2S23CKSELR register fields */ +#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 + +/* RCC_SPI45CKSELR register fields */ +#define RCC_SPI45CKSELR_SPI45SRC_MASK GENMASK(2, 0) +#define RCC_SPI45CKSELR_SPI45SRC_SHIFT 0 + +/* RCC_UART6CKSELR register fields */ +#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) +#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 + +/* RCC_UART24CKSELR register fields */ +#define RCC_UART24CKSELR_HSI 0x00000002 +#define RCC_UART24CKSELR_UART24SRC_MASK GENMASK(2, 0) +#define RCC_UART24CKSELR_UART24SRC_SHIFT 0 + +/* RCC_UART35CKSELR register fields */ +#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) +#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 + +/* RCC_UART78CKSELR register fields */ +#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) +#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 + +/* RCC_SDMMC12CKSELR register fields */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_SHIFT 0 + +/* RCC_SDMMC3CKSELR register fields */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_SHIFT 0 + +/* RCC_ETHCKSELR register fields */ +#define RCC_ETHCKSELR_ETHSRC_MASK GENMASK(1, 0) +#define RCC_ETHCKSELR_ETHSRC_SHIFT 0 +#define RCC_ETHCKSELR_ETHPTPDIV_MASK GENMASK(7, 4) +#define RCC_ETHCKSELR_ETHPTPDIV_SHIFT 4 + +/* RCC_QSPICKSELR register fields */ +#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) +#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 + +/* RCC_FMCCKSELR register fields */ +#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) +#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 + +/* RCC_FDCANCKSELR register fields */ +#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) +#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 + +/* RCC_SPDIFCKSELR register fields */ +#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) +#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 + +/* RCC_CECCKSELR register fields */ +#define RCC_CECCKSELR_CECSRC_MASK GENMASK(1, 0) +#define RCC_CECCKSELR_CECSRC_SHIFT 0 + +/* RCC_USBCKSELR register fields */ +#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) +#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 +#define RCC_USBCKSELR_USBOSRC BIT(4) +#define RCC_USBCKSELR_USBOSRC_MASK BIT(4) +#define RCC_USBCKSELR_USBOSRC_SHIFT 4 + +/* RCC_RNG2CKSELR register fields */ +#define RCC_RNG2CKSELR_RNG2SRC_MASK GENMASK(1, 0) +#define RCC_RNG2CKSELR_RNG2SRC_SHIFT 0 + +/* RCC_DSICKSELR register fields */ +#define RCC_DSICKSELR_DSISRC BIT(0) + +/* RCC_ADCCKSELR register fields */ +#define RCC_ADCCKSELR_ADCSRC_MASK GENMASK(1, 0) +#define RCC_ADCCKSELR_ADCSRC_SHIFT 0 + +/* RCC_LPTIM45CKSELR register fields */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 + +/* RCC_LPTIM23CKSELR register fields */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_SHIFT 0 + +/* RCC_LPTIM1CKSELR register fields */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 + +/* RCC_APB1RSTSETR register fields */ +#define RCC_APB1RSTSETR_TIM2RST BIT(0) +#define RCC_APB1RSTSETR_TIM3RST BIT(1) +#define RCC_APB1RSTSETR_TIM4RST BIT(2) +#define RCC_APB1RSTSETR_TIM5RST BIT(3) +#define RCC_APB1RSTSETR_TIM6RST BIT(4) +#define RCC_APB1RSTSETR_TIM7RST BIT(5) +#define RCC_APB1RSTSETR_TIM12RST BIT(6) +#define RCC_APB1RSTSETR_TIM13RST BIT(7) +#define RCC_APB1RSTSETR_TIM14RST BIT(8) +#define RCC_APB1RSTSETR_LPTIM1RST BIT(9) +#define RCC_APB1RSTSETR_SPI2RST BIT(11) +#define RCC_APB1RSTSETR_SPI3RST BIT(12) +#define RCC_APB1RSTSETR_USART2RST BIT(14) +#define RCC_APB1RSTSETR_USART3RST BIT(15) +#define RCC_APB1RSTSETR_UART4RST BIT(16) +#define RCC_APB1RSTSETR_UART5RST BIT(17) +#define RCC_APB1RSTSETR_UART7RST BIT(18) +#define RCC_APB1RSTSETR_UART8RST BIT(19) +#define RCC_APB1RSTSETR_I2C1RST BIT(21) +#define RCC_APB1RSTSETR_I2C2RST BIT(22) +#define RCC_APB1RSTSETR_I2C3RST BIT(23) +#define RCC_APB1RSTSETR_I2C5RST BIT(24) +#define RCC_APB1RSTSETR_SPDIFRST BIT(26) +#define RCC_APB1RSTSETR_CECRST BIT(27) +#define RCC_APB1RSTSETR_DAC12RST BIT(29) +#define RCC_APB1RSTSETR_MDIOSRST BIT(31) + +/* RCC_APB1RSTCLRR register fields */ +#define RCC_APB1RSTCLRR_TIM2RST BIT(0) +#define RCC_APB1RSTCLRR_TIM3RST BIT(1) +#define RCC_APB1RSTCLRR_TIM4RST BIT(2) +#define RCC_APB1RSTCLRR_TIM5RST BIT(3) +#define RCC_APB1RSTCLRR_TIM6RST BIT(4) +#define RCC_APB1RSTCLRR_TIM7RST BIT(5) +#define RCC_APB1RSTCLRR_TIM12RST BIT(6) +#define RCC_APB1RSTCLRR_TIM13RST BIT(7) +#define RCC_APB1RSTCLRR_TIM14RST BIT(8) +#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) +#define RCC_APB1RSTCLRR_SPI2RST BIT(11) +#define RCC_APB1RSTCLRR_SPI3RST BIT(12) +#define RCC_APB1RSTCLRR_USART2RST BIT(14) +#define RCC_APB1RSTCLRR_USART3RST BIT(15) +#define RCC_APB1RSTCLRR_UART4RST BIT(16) +#define RCC_APB1RSTCLRR_UART5RST BIT(17) +#define RCC_APB1RSTCLRR_UART7RST BIT(18) +#define RCC_APB1RSTCLRR_UART8RST BIT(19) +#define RCC_APB1RSTCLRR_I2C1RST BIT(21) +#define RCC_APB1RSTCLRR_I2C2RST BIT(22) +#define RCC_APB1RSTCLRR_I2C3RST BIT(23) +#define RCC_APB1RSTCLRR_I2C5RST BIT(24) +#define RCC_APB1RSTCLRR_SPDIFRST BIT(26) +#define RCC_APB1RSTCLRR_CECRST BIT(27) +#define RCC_APB1RSTCLRR_DAC12RST BIT(29) +#define RCC_APB1RSTCLRR_MDIOSRST BIT(31) + +/* RCC_APB2RSTSETR register fields */ +#define RCC_APB2RSTSETR_TIM1RST BIT(0) +#define RCC_APB2RSTSETR_TIM8RST BIT(1) +#define RCC_APB2RSTSETR_TIM15RST BIT(2) +#define RCC_APB2RSTSETR_TIM16RST BIT(3) +#define RCC_APB2RSTSETR_TIM17RST BIT(4) +#define RCC_APB2RSTSETR_SPI1RST BIT(8) +#define RCC_APB2RSTSETR_SPI4RST BIT(9) +#define RCC_APB2RSTSETR_SPI5RST BIT(10) +#define RCC_APB2RSTSETR_USART6RST BIT(13) +#define RCC_APB2RSTSETR_SAI1RST BIT(16) +#define RCC_APB2RSTSETR_SAI2RST BIT(17) +#define RCC_APB2RSTSETR_SAI3RST BIT(18) +#define RCC_APB2RSTSETR_DFSDMRST BIT(20) +#define RCC_APB2RSTSETR_FDCANRST BIT(24) + +/* RCC_APB2RSTCLRR register fields */ +#define RCC_APB2RSTCLRR_TIM1RST BIT(0) +#define RCC_APB2RSTCLRR_TIM8RST BIT(1) +#define RCC_APB2RSTCLRR_TIM15RST BIT(2) +#define RCC_APB2RSTCLRR_TIM16RST BIT(3) +#define RCC_APB2RSTCLRR_TIM17RST BIT(4) +#define RCC_APB2RSTCLRR_SPI1RST BIT(8) +#define RCC_APB2RSTCLRR_SPI4RST BIT(9) +#define RCC_APB2RSTCLRR_SPI5RST BIT(10) +#define RCC_APB2RSTCLRR_USART6RST BIT(13) +#define RCC_APB2RSTCLRR_SAI1RST BIT(16) +#define RCC_APB2RSTCLRR_SAI2RST BIT(17) +#define RCC_APB2RSTCLRR_SAI3RST BIT(18) +#define RCC_APB2RSTCLRR_DFSDMRST BIT(20) +#define RCC_APB2RSTCLRR_FDCANRST BIT(24) + +/* RCC_APB3RSTSETR register fields */ +#define RCC_APB3RSTSETR_LPTIM2RST BIT(0) +#define RCC_APB3RSTSETR_LPTIM3RST BIT(1) +#define RCC_APB3RSTSETR_LPTIM4RST BIT(2) +#define RCC_APB3RSTSETR_LPTIM5RST BIT(3) +#define RCC_APB3RSTSETR_SAI4RST BIT(8) +#define RCC_APB3RSTSETR_SYSCFGRST BIT(11) +#define RCC_APB3RSTSETR_VREFRST BIT(13) +#define RCC_APB3RSTSETR_TMPSENSRST BIT(16) +#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) + +/* RCC_APB3RSTCLRR register fields */ +#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) +#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) +#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) +#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) +#define RCC_APB3RSTCLRR_SAI4RST BIT(8) +#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) +#define RCC_APB3RSTCLRR_VREFRST BIT(13) +#define RCC_APB3RSTCLRR_TMPSENSRST BIT(16) +#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) + +/* RCC_AHB2RSTSETR register fields */ +#define RCC_AHB2RSTSETR_DMA1RST BIT(0) +#define RCC_AHB2RSTSETR_DMA2RST BIT(1) +#define RCC_AHB2RSTSETR_DMAMUXRST BIT(2) +#define RCC_AHB2RSTSETR_ADC12RST BIT(5) +#define RCC_AHB2RSTSETR_USBORST BIT(8) +#define RCC_AHB2RSTSETR_SDMMC3RST BIT(16) + +/* RCC_AHB2RSTCLRR register fields */ +#define RCC_AHB2RSTCLRR_DMA1RST BIT(0) +#define RCC_AHB2RSTCLRR_DMA2RST BIT(1) +#define RCC_AHB2RSTCLRR_DMAMUXRST BIT(2) +#define RCC_AHB2RSTCLRR_ADC12RST BIT(5) +#define RCC_AHB2RSTCLRR_USBORST BIT(8) +#define RCC_AHB2RSTCLRR_SDMMC3RST BIT(16) + +/* RCC_AHB3RSTSETR register fields */ +#define RCC_AHB3RSTSETR_DCMIRST BIT(0) +#define RCC_AHB3RSTSETR_CRYP2RST BIT(4) +#define RCC_AHB3RSTSETR_HASH2RST BIT(5) +#define RCC_AHB3RSTSETR_RNG2RST BIT(6) +#define RCC_AHB3RSTSETR_CRC2RST BIT(7) +#define RCC_AHB3RSTSETR_HSEMRST BIT(11) +#define RCC_AHB3RSTSETR_IPCCRST BIT(12) + +/* RCC_AHB3RSTCLRR register fields */ +#define RCC_AHB3RSTCLRR_DCMIRST BIT(0) +#define RCC_AHB3RSTCLRR_CRYP2RST BIT(4) +#define RCC_AHB3RSTCLRR_HASH2RST BIT(5) +#define RCC_AHB3RSTCLRR_RNG2RST BIT(6) +#define RCC_AHB3RSTCLRR_CRC2RST BIT(7) +#define RCC_AHB3RSTCLRR_HSEMRST BIT(11) +#define RCC_AHB3RSTCLRR_IPCCRST BIT(12) + +/* RCC_AHB4RSTSETR register fields */ +#define RCC_AHB4RSTSETR_GPIOARST BIT(0) +#define RCC_AHB4RSTSETR_GPIOBRST BIT(1) +#define RCC_AHB4RSTSETR_GPIOCRST BIT(2) +#define RCC_AHB4RSTSETR_GPIODRST BIT(3) +#define RCC_AHB4RSTSETR_GPIOERST BIT(4) +#define RCC_AHB4RSTSETR_GPIOFRST BIT(5) +#define RCC_AHB4RSTSETR_GPIOGRST BIT(6) +#define RCC_AHB4RSTSETR_GPIOHRST BIT(7) +#define RCC_AHB4RSTSETR_GPIOIRST BIT(8) +#define RCC_AHB4RSTSETR_GPIOJRST BIT(9) +#define RCC_AHB4RSTSETR_GPIOKRST BIT(10) + +/* RCC_AHB4RSTCLRR register fields */ +#define RCC_AHB4RSTCLRR_GPIOARST BIT(0) +#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) +#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) +#define RCC_AHB4RSTCLRR_GPIODRST BIT(3) +#define RCC_AHB4RSTCLRR_GPIOERST BIT(4) +#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) +#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) +#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) +#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) +#define RCC_AHB4RSTCLRR_GPIOJRST BIT(9) +#define RCC_AHB4RSTCLRR_GPIOKRST BIT(10) + +/* RCC_MP_APB1ENSETR register fields */ +#define RCC_MP_APB1ENSETR_TIM2EN BIT(0) +#define RCC_MP_APB1ENSETR_TIM3EN BIT(1) +#define RCC_MP_APB1ENSETR_TIM4EN BIT(2) +#define RCC_MP_APB1ENSETR_TIM5EN BIT(3) +#define RCC_MP_APB1ENSETR_TIM6EN BIT(4) +#define RCC_MP_APB1ENSETR_TIM7EN BIT(5) +#define RCC_MP_APB1ENSETR_TIM12EN BIT(6) +#define RCC_MP_APB1ENSETR_TIM13EN BIT(7) +#define RCC_MP_APB1ENSETR_TIM14EN BIT(8) +#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENSETR_SPI2EN BIT(11) +#define RCC_MP_APB1ENSETR_SPI3EN BIT(12) +#define RCC_MP_APB1ENSETR_USART2EN BIT(14) +#define RCC_MP_APB1ENSETR_USART3EN BIT(15) +#define RCC_MP_APB1ENSETR_UART4EN BIT(16) +#define RCC_MP_APB1ENSETR_UART5EN BIT(17) +#define RCC_MP_APB1ENSETR_UART7EN BIT(18) +#define RCC_MP_APB1ENSETR_UART8EN BIT(19) +#define RCC_MP_APB1ENSETR_I2C1EN BIT(21) +#define RCC_MP_APB1ENSETR_I2C2EN BIT(22) +#define RCC_MP_APB1ENSETR_I2C3EN BIT(23) +#define RCC_MP_APB1ENSETR_I2C5EN BIT(24) +#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) +#define RCC_MP_APB1ENSETR_CECEN BIT(27) +#define RCC_MP_APB1ENSETR_DAC12EN BIT(29) +#define RCC_MP_APB1ENSETR_MDIOSEN BIT(31) + +/* RCC_MP_APB1ENCLRR register fields */ +#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) +#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) +#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) +#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) +#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) +#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) +#define RCC_MP_APB1ENCLRR_TIM12EN BIT(6) +#define RCC_MP_APB1ENCLRR_TIM13EN BIT(7) +#define RCC_MP_APB1ENCLRR_TIM14EN BIT(8) +#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) +#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) +#define RCC_MP_APB1ENCLRR_USART2EN BIT(14) +#define RCC_MP_APB1ENCLRR_USART3EN BIT(15) +#define RCC_MP_APB1ENCLRR_UART4EN BIT(16) +#define RCC_MP_APB1ENCLRR_UART5EN BIT(17) +#define RCC_MP_APB1ENCLRR_UART7EN BIT(18) +#define RCC_MP_APB1ENCLRR_UART8EN BIT(19) +#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) +#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) +#define RCC_MP_APB1ENCLRR_I2C3EN BIT(23) +#define RCC_MP_APB1ENCLRR_I2C5EN BIT(24) +#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) +#define RCC_MP_APB1ENCLRR_CECEN BIT(27) +#define RCC_MP_APB1ENCLRR_DAC12EN BIT(29) +#define RCC_MP_APB1ENCLRR_MDIOSEN BIT(31) + +/* RCC_MP_APB2ENSETR register fields */ +#define RCC_MP_APB2ENSETR_TIM1EN BIT(0) +#define RCC_MP_APB2ENSETR_TIM8EN BIT(1) +#define RCC_MP_APB2ENSETR_TIM15EN BIT(2) +#define RCC_MP_APB2ENSETR_TIM16EN BIT(3) +#define RCC_MP_APB2ENSETR_TIM17EN BIT(4) +#define RCC_MP_APB2ENSETR_SPI1EN BIT(8) +#define RCC_MP_APB2ENSETR_SPI4EN BIT(9) +#define RCC_MP_APB2ENSETR_SPI5EN BIT(10) +#define RCC_MP_APB2ENSETR_USART6EN BIT(13) +#define RCC_MP_APB2ENSETR_SAI1EN BIT(16) +#define RCC_MP_APB2ENSETR_SAI2EN BIT(17) +#define RCC_MP_APB2ENSETR_SAI3EN BIT(18) +#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENSETR_FDCANEN BIT(24) + +/* RCC_MP_APB2ENCLRR register fields */ +#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) +#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) +#define RCC_MP_APB2ENCLRR_TIM15EN BIT(2) +#define RCC_MP_APB2ENCLRR_TIM16EN BIT(3) +#define RCC_MP_APB2ENCLRR_TIM17EN BIT(4) +#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) +#define RCC_MP_APB2ENCLRR_SPI4EN BIT(9) +#define RCC_MP_APB2ENCLRR_SPI5EN BIT(10) +#define RCC_MP_APB2ENCLRR_USART6EN BIT(13) +#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) +#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) +#define RCC_MP_APB2ENCLRR_SAI3EN BIT(18) +#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) + +/* RCC_MP_APB3ENSETR register fields */ +#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENSETR_SAI4EN BIT(8) +#define RCC_MP_APB3ENSETR_SYSCFGEN BIT(11) +#define RCC_MP_APB3ENSETR_VREFEN BIT(13) +#define RCC_MP_APB3ENSETR_TMPSENSEN BIT(16) +#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENSETR_HDPEN BIT(20) + +/* RCC_MP_APB3ENCLRR register fields */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENCLRR_SAI4EN BIT(8) +#define RCC_MP_APB3ENCLRR_SYSCFGEN BIT(11) +#define RCC_MP_APB3ENCLRR_VREFEN BIT(13) +#define RCC_MP_APB3ENCLRR_TMPSENSEN BIT(16) +#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENCLRR_HDPEN BIT(20) + +/* RCC_MP_AHB2ENSETR register fields */ +#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENSETR_DMAMUXEN BIT(2) +#define RCC_MP_AHB2ENSETR_ADC12EN BIT(5) +#define RCC_MP_AHB2ENSETR_USBOEN BIT(8) +#define RCC_MP_AHB2ENSETR_SDMMC3EN BIT(16) + +/* RCC_MP_AHB2ENCLRR register fields */ +#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN BIT(2) +#define RCC_MP_AHB2ENCLRR_ADC12EN BIT(5) +#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN BIT(16) + +/* RCC_MP_AHB3ENSETR register fields */ +#define RCC_MP_AHB3ENSETR_DCMIEN BIT(0) +#define RCC_MP_AHB3ENSETR_CRYP2EN BIT(4) +#define RCC_MP_AHB3ENSETR_HASH2EN BIT(5) +#define RCC_MP_AHB3ENSETR_RNG2EN BIT(6) +#define RCC_MP_AHB3ENSETR_CRC2EN BIT(7) +#define RCC_MP_AHB3ENSETR_HSEMEN BIT(11) +#define RCC_MP_AHB3ENSETR_IPCCEN BIT(12) + +/* RCC_MP_AHB3ENCLRR register fields */ +#define RCC_MP_AHB3ENCLRR_DCMIEN BIT(0) +#define RCC_MP_AHB3ENCLRR_CRYP2EN BIT(4) +#define RCC_MP_AHB3ENCLRR_HASH2EN BIT(5) +#define RCC_MP_AHB3ENCLRR_RNG2EN BIT(6) +#define RCC_MP_AHB3ENCLRR_CRC2EN BIT(7) +#define RCC_MP_AHB3ENCLRR_HSEMEN BIT(11) +#define RCC_MP_AHB3ENCLRR_IPCCEN BIT(12) + +/* RCC_MP_AHB4ENSETR register fields */ +#define RCC_MP_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MP_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MP_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MP_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MP_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MP_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MP_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MP_AHB4ENSETR_GPIOIEN BIT(8) +#define RCC_MP_AHB4ENSETR_GPIOJEN BIT(9) +#define RCC_MP_AHB4ENSETR_GPIOKEN BIT(10) + +/* RCC_MP_AHB4ENCLRR register fields */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MP_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MP_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MP_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MP_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MP_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MP_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MP_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MP_AHB4ENCLRR_GPIOIEN BIT(8) +#define RCC_MP_AHB4ENCLRR_GPIOJEN BIT(9) +#define RCC_MP_AHB4ENCLRR_GPIOKEN BIT(10) + +/* RCC_MP_MLAHBENSETR register fields */ +#define RCC_MP_MLAHBENSETR_RETRAMEN BIT(4) + +/* RCC_MP_MLAHBENCLRR register fields */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN BIT(4) + +/* RCC_MC_APB1ENSETR register fields */ +#define RCC_MC_APB1ENSETR_TIM2EN BIT(0) +#define RCC_MC_APB1ENSETR_TIM3EN BIT(1) +#define RCC_MC_APB1ENSETR_TIM4EN BIT(2) +#define RCC_MC_APB1ENSETR_TIM5EN BIT(3) +#define RCC_MC_APB1ENSETR_TIM6EN BIT(4) +#define RCC_MC_APB1ENSETR_TIM7EN BIT(5) +#define RCC_MC_APB1ENSETR_TIM12EN BIT(6) +#define RCC_MC_APB1ENSETR_TIM13EN BIT(7) +#define RCC_MC_APB1ENSETR_TIM14EN BIT(8) +#define RCC_MC_APB1ENSETR_LPTIM1EN BIT(9) +#define RCC_MC_APB1ENSETR_SPI2EN BIT(11) +#define RCC_MC_APB1ENSETR_SPI3EN BIT(12) +#define RCC_MC_APB1ENSETR_USART2EN BIT(14) +#define RCC_MC_APB1ENSETR_USART3EN BIT(15) +#define RCC_MC_APB1ENSETR_UART4EN BIT(16) +#define RCC_MC_APB1ENSETR_UART5EN BIT(17) +#define RCC_MC_APB1ENSETR_UART7EN BIT(18) +#define RCC_MC_APB1ENSETR_UART8EN BIT(19) +#define RCC_MC_APB1ENSETR_I2C1EN BIT(21) +#define RCC_MC_APB1ENSETR_I2C2EN BIT(22) +#define RCC_MC_APB1ENSETR_I2C3EN BIT(23) +#define RCC_MC_APB1ENSETR_I2C5EN BIT(24) +#define RCC_MC_APB1ENSETR_SPDIFEN BIT(26) +#define RCC_MC_APB1ENSETR_CECEN BIT(27) +#define RCC_MC_APB1ENSETR_WWDG1EN BIT(28) +#define RCC_MC_APB1ENSETR_DAC12EN BIT(29) +#define RCC_MC_APB1ENSETR_MDIOSEN BIT(31) + +/* RCC_MC_APB1ENCLRR register fields */ +#define RCC_MC_APB1ENCLRR_TIM2EN BIT(0) +#define RCC_MC_APB1ENCLRR_TIM3EN BIT(1) +#define RCC_MC_APB1ENCLRR_TIM4EN BIT(2) +#define RCC_MC_APB1ENCLRR_TIM5EN BIT(3) +#define RCC_MC_APB1ENCLRR_TIM6EN BIT(4) +#define RCC_MC_APB1ENCLRR_TIM7EN BIT(5) +#define RCC_MC_APB1ENCLRR_TIM12EN BIT(6) +#define RCC_MC_APB1ENCLRR_TIM13EN BIT(7) +#define RCC_MC_APB1ENCLRR_TIM14EN BIT(8) +#define RCC_MC_APB1ENCLRR_LPTIM1EN BIT(9) +#define RCC_MC_APB1ENCLRR_SPI2EN BIT(11) +#define RCC_MC_APB1ENCLRR_SPI3EN BIT(12) +#define RCC_MC_APB1ENCLRR_USART2EN BIT(14) +#define RCC_MC_APB1ENCLRR_USART3EN BIT(15) +#define RCC_MC_APB1ENCLRR_UART4EN BIT(16) +#define RCC_MC_APB1ENCLRR_UART5EN BIT(17) +#define RCC_MC_APB1ENCLRR_UART7EN BIT(18) +#define RCC_MC_APB1ENCLRR_UART8EN BIT(19) +#define RCC_MC_APB1ENCLRR_I2C1EN BIT(21) +#define RCC_MC_APB1ENCLRR_I2C2EN BIT(22) +#define RCC_MC_APB1ENCLRR_I2C3EN BIT(23) +#define RCC_MC_APB1ENCLRR_I2C5EN BIT(24) +#define RCC_MC_APB1ENCLRR_SPDIFEN BIT(26) +#define RCC_MC_APB1ENCLRR_CECEN BIT(27) +#define RCC_MC_APB1ENCLRR_DAC12EN BIT(29) +#define RCC_MC_APB1ENCLRR_MDIOSEN BIT(31) + +/* RCC_MC_APB2ENSETR register fields */ +#define RCC_MC_APB2ENSETR_TIM1EN BIT(0) +#define RCC_MC_APB2ENSETR_TIM8EN BIT(1) +#define RCC_MC_APB2ENSETR_TIM15EN BIT(2) +#define RCC_MC_APB2ENSETR_TIM16EN BIT(3) +#define RCC_MC_APB2ENSETR_TIM17EN BIT(4) +#define RCC_MC_APB2ENSETR_SPI1EN BIT(8) +#define RCC_MC_APB2ENSETR_SPI4EN BIT(9) +#define RCC_MC_APB2ENSETR_SPI5EN BIT(10) +#define RCC_MC_APB2ENSETR_USART6EN BIT(13) +#define RCC_MC_APB2ENSETR_SAI1EN BIT(16) +#define RCC_MC_APB2ENSETR_SAI2EN BIT(17) +#define RCC_MC_APB2ENSETR_SAI3EN BIT(18) +#define RCC_MC_APB2ENSETR_DFSDMEN BIT(20) +#define RCC_MC_APB2ENSETR_ADFSDMEN BIT(21) +#define RCC_MC_APB2ENSETR_FDCANEN BIT(24) + +/* RCC_MC_APB2ENCLRR register fields */ +#define RCC_MC_APB2ENCLRR_TIM1EN BIT(0) +#define RCC_MC_APB2ENCLRR_TIM8EN BIT(1) +#define RCC_MC_APB2ENCLRR_TIM15EN BIT(2) +#define RCC_MC_APB2ENCLRR_TIM16EN BIT(3) +#define RCC_MC_APB2ENCLRR_TIM17EN BIT(4) +#define RCC_MC_APB2ENCLRR_SPI1EN BIT(8) +#define RCC_MC_APB2ENCLRR_SPI4EN BIT(9) +#define RCC_MC_APB2ENCLRR_SPI5EN BIT(10) +#define RCC_MC_APB2ENCLRR_USART6EN BIT(13) +#define RCC_MC_APB2ENCLRR_SAI1EN BIT(16) +#define RCC_MC_APB2ENCLRR_SAI2EN BIT(17) +#define RCC_MC_APB2ENCLRR_SAI3EN BIT(18) +#define RCC_MC_APB2ENCLRR_DFSDMEN BIT(20) +#define RCC_MC_APB2ENCLRR_ADFSDMEN BIT(21) +#define RCC_MC_APB2ENCLRR_FDCANEN BIT(24) + +/* RCC_MC_APB3ENSETR register fields */ +#define RCC_MC_APB3ENSETR_LPTIM2EN BIT(0) +#define RCC_MC_APB3ENSETR_LPTIM3EN BIT(1) +#define RCC_MC_APB3ENSETR_LPTIM4EN BIT(2) +#define RCC_MC_APB3ENSETR_LPTIM5EN BIT(3) +#define RCC_MC_APB3ENSETR_SAI4EN BIT(8) +#define RCC_MC_APB3ENSETR_SYSCFGEN BIT(11) +#define RCC_MC_APB3ENSETR_VREFEN BIT(13) +#define RCC_MC_APB3ENSETR_TMPSENSEN BIT(16) +#define RCC_MC_APB3ENSETR_PMBCTRLEN BIT(17) +#define RCC_MC_APB3ENSETR_HDPEN BIT(20) + +/* RCC_MC_APB3ENCLRR register fields */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN BIT(0) +#define RCC_MC_APB3ENCLRR_LPTIM3EN BIT(1) +#define RCC_MC_APB3ENCLRR_LPTIM4EN BIT(2) +#define RCC_MC_APB3ENCLRR_LPTIM5EN BIT(3) +#define RCC_MC_APB3ENCLRR_SAI4EN BIT(8) +#define RCC_MC_APB3ENCLRR_SYSCFGEN BIT(11) +#define RCC_MC_APB3ENCLRR_VREFEN BIT(13) +#define RCC_MC_APB3ENCLRR_TMPSENSEN BIT(16) +#define RCC_MC_APB3ENCLRR_PMBCTRLEN BIT(17) +#define RCC_MC_APB3ENCLRR_HDPEN BIT(20) + +/* RCC_MC_AHB2ENSETR register fields */ +#define RCC_MC_AHB2ENSETR_DMA1EN BIT(0) +#define RCC_MC_AHB2ENSETR_DMA2EN BIT(1) +#define RCC_MC_AHB2ENSETR_DMAMUXEN BIT(2) +#define RCC_MC_AHB2ENSETR_ADC12EN BIT(5) +#define RCC_MC_AHB2ENSETR_USBOEN BIT(8) +#define RCC_MC_AHB2ENSETR_SDMMC3EN BIT(16) + +/* RCC_MC_AHB2ENCLRR register fields */ +#define RCC_MC_AHB2ENCLRR_DMA1EN BIT(0) +#define RCC_MC_AHB2ENCLRR_DMA2EN BIT(1) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN BIT(2) +#define RCC_MC_AHB2ENCLRR_ADC12EN BIT(5) +#define RCC_MC_AHB2ENCLRR_USBOEN BIT(8) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN BIT(16) + +/* RCC_MC_AHB3ENSETR register fields */ +#define RCC_MC_AHB3ENSETR_DCMIEN BIT(0) +#define RCC_MC_AHB3ENSETR_CRYP2EN BIT(4) +#define RCC_MC_AHB3ENSETR_HASH2EN BIT(5) +#define RCC_MC_AHB3ENSETR_RNG2EN BIT(6) +#define RCC_MC_AHB3ENSETR_CRC2EN BIT(7) +#define RCC_MC_AHB3ENSETR_HSEMEN BIT(11) +#define RCC_MC_AHB3ENSETR_IPCCEN BIT(12) + +/* RCC_MC_AHB3ENCLRR register fields */ +#define RCC_MC_AHB3ENCLRR_DCMIEN BIT(0) +#define RCC_MC_AHB3ENCLRR_CRYP2EN BIT(4) +#define RCC_MC_AHB3ENCLRR_HASH2EN BIT(5) +#define RCC_MC_AHB3ENCLRR_RNG2EN BIT(6) +#define RCC_MC_AHB3ENCLRR_CRC2EN BIT(7) +#define RCC_MC_AHB3ENCLRR_HSEMEN BIT(11) +#define RCC_MC_AHB3ENCLRR_IPCCEN BIT(12) + +/* RCC_MC_AHB4ENSETR register fields */ +#define RCC_MC_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MC_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MC_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MC_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MC_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MC_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MC_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MC_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MC_AHB4ENSETR_GPIOIEN BIT(8) +#define RCC_MC_AHB4ENSETR_GPIOJEN BIT(9) +#define RCC_MC_AHB4ENSETR_GPIOKEN BIT(10) + +/* RCC_MC_AHB4ENCLRR register fields */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MC_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MC_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MC_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MC_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MC_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MC_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MC_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MC_AHB4ENCLRR_GPIOIEN BIT(8) +#define RCC_MC_AHB4ENCLRR_GPIOJEN BIT(9) +#define RCC_MC_AHB4ENCLRR_GPIOKEN BIT(10) + +/* RCC_MC_AXIMENSETR register fields */ +#define RCC_MC_AXIMENSETR_SYSRAMEN BIT(0) + +/* RCC_MC_AXIMENCLRR register fields */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN BIT(0) + +/* RCC_MC_MLAHBENSETR register fields */ +#define RCC_MC_MLAHBENSETR_RETRAMEN BIT(4) + +/* RCC_MC_MLAHBENCLRR register fields */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN BIT(4) + +/* RCC_MP_APB1LPENSETR register fields */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENSETR_TIM12LPEN BIT(6) +#define RCC_MP_APB1LPENSETR_TIM13LPEN BIT(7) +#define RCC_MP_APB1LPENSETR_TIM14LPEN BIT(8) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENSETR_USART2LPEN BIT(14) +#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENSETR_I2C3LPEN BIT(23) +#define RCC_MP_APB1LPENSETR_I2C5LPEN BIT(24) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) +#define RCC_MP_APB1LPENSETR_CECLPEN BIT(27) +#define RCC_MP_APB1LPENSETR_DAC12LPEN BIT(29) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN BIT(31) + +/* RCC_MP_APB1LPENCLRR register fields */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN BIT(6) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN BIT(7) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN BIT(8) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENCLRR_USART2LPEN BIT(14) +#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN BIT(23) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN BIT(24) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) +#define RCC_MP_APB1LPENCLRR_CECLPEN BIT(27) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN BIT(29) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN BIT(31) + +/* RCC_MP_APB2LPENSETR register fields */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENSETR_TIM15LPEN BIT(2) +#define RCC_MP_APB2LPENSETR_TIM16LPEN BIT(3) +#define RCC_MP_APB2LPENSETR_TIM17LPEN BIT(4) +#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENSETR_SPI4LPEN BIT(9) +#define RCC_MP_APB2LPENSETR_SPI5LPEN BIT(10) +#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENSETR_SAI3LPEN BIT(18) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) + +/* RCC_MP_APB2LPENCLRR register fields */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN BIT(2) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN BIT(3) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN BIT(4) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN BIT(9) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN BIT(10) +#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN BIT(18) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) + +/* RCC_MP_APB3LPENSETR register fields */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENSETR_SAI4LPEN BIT(8) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN BIT(11) +#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENSETR_TMPSENSLPEN BIT(16) +#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_APB3LPENCLRR register fields */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN BIT(8) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN BIT(11) +#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENCLRR_TMPSENSLPEN BIT(16) +#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_AHB2LPENSETR register fields */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN BIT(2) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN BIT(5) +#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN BIT(16) + +/* RCC_MP_AHB2LPENCLRR register fields */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN BIT(2) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN BIT(5) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN BIT(16) + +/* RCC_MP_AHB3LPENSETR register fields */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN BIT(0) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN BIT(4) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN BIT(5) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN BIT(6) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN BIT(7) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN BIT(11) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN BIT(12) + +/* RCC_MP_AHB3LPENCLRR register fields */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN BIT(0) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN BIT(4) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN BIT(5) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN BIT(6) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN BIT(7) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN BIT(11) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN BIT(12) + +/* RCC_MP_AHB4LPENSETR register fields */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN BIT(8) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN BIT(9) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN BIT(10) + +/* RCC_MP_AHB4LPENCLRR register fields */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN BIT(8) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN BIT(9) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN BIT(10) + +/* RCC_MP_AXIMLPENSETR register fields */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MP_AXIMLPENCLRR register fields */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MP_MLAHBLPENSETR register fields */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN BIT(2) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN BIT(4) + +/* RCC_MP_MLAHBLPENCLRR register fields */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN BIT(2) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN BIT(4) + +/* RCC_MC_APB1LPENSETR register fields */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN BIT(0) +#define RCC_MC_APB1LPENSETR_TIM3LPEN BIT(1) +#define RCC_MC_APB1LPENSETR_TIM4LPEN BIT(2) +#define RCC_MC_APB1LPENSETR_TIM5LPEN BIT(3) +#define RCC_MC_APB1LPENSETR_TIM6LPEN BIT(4) +#define RCC_MC_APB1LPENSETR_TIM7LPEN BIT(5) +#define RCC_MC_APB1LPENSETR_TIM12LPEN BIT(6) +#define RCC_MC_APB1LPENSETR_TIM13LPEN BIT(7) +#define RCC_MC_APB1LPENSETR_TIM14LPEN BIT(8) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN BIT(9) +#define RCC_MC_APB1LPENSETR_SPI2LPEN BIT(11) +#define RCC_MC_APB1LPENSETR_SPI3LPEN BIT(12) +#define RCC_MC_APB1LPENSETR_USART2LPEN BIT(14) +#define RCC_MC_APB1LPENSETR_USART3LPEN BIT(15) +#define RCC_MC_APB1LPENSETR_UART4LPEN BIT(16) +#define RCC_MC_APB1LPENSETR_UART5LPEN BIT(17) +#define RCC_MC_APB1LPENSETR_UART7LPEN BIT(18) +#define RCC_MC_APB1LPENSETR_UART8LPEN BIT(19) +#define RCC_MC_APB1LPENSETR_I2C1LPEN BIT(21) +#define RCC_MC_APB1LPENSETR_I2C2LPEN BIT(22) +#define RCC_MC_APB1LPENSETR_I2C3LPEN BIT(23) +#define RCC_MC_APB1LPENSETR_I2C5LPEN BIT(24) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN BIT(26) +#define RCC_MC_APB1LPENSETR_CECLPEN BIT(27) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN BIT(28) +#define RCC_MC_APB1LPENSETR_DAC12LPEN BIT(29) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN BIT(31) + +/* RCC_MC_APB1LPENCLRR register fields */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN BIT(0) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN BIT(1) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN BIT(2) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN BIT(3) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN BIT(4) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN BIT(5) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN BIT(6) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN BIT(7) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN BIT(8) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN BIT(9) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN BIT(11) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN BIT(12) +#define RCC_MC_APB1LPENCLRR_USART2LPEN BIT(14) +#define RCC_MC_APB1LPENCLRR_USART3LPEN BIT(15) +#define RCC_MC_APB1LPENCLRR_UART4LPEN BIT(16) +#define RCC_MC_APB1LPENCLRR_UART5LPEN BIT(17) +#define RCC_MC_APB1LPENCLRR_UART7LPEN BIT(18) +#define RCC_MC_APB1LPENCLRR_UART8LPEN BIT(19) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN BIT(21) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN BIT(22) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN BIT(23) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN BIT(24) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN BIT(26) +#define RCC_MC_APB1LPENCLRR_CECLPEN BIT(27) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN BIT(28) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN BIT(29) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN BIT(31) + +/* RCC_MC_APB2LPENSETR register fields */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN BIT(0) +#define RCC_MC_APB2LPENSETR_TIM8LPEN BIT(1) +#define RCC_MC_APB2LPENSETR_TIM15LPEN BIT(2) +#define RCC_MC_APB2LPENSETR_TIM16LPEN BIT(3) +#define RCC_MC_APB2LPENSETR_TIM17LPEN BIT(4) +#define RCC_MC_APB2LPENSETR_SPI1LPEN BIT(8) +#define RCC_MC_APB2LPENSETR_SPI4LPEN BIT(9) +#define RCC_MC_APB2LPENSETR_SPI5LPEN BIT(10) +#define RCC_MC_APB2LPENSETR_USART6LPEN BIT(13) +#define RCC_MC_APB2LPENSETR_SAI1LPEN BIT(16) +#define RCC_MC_APB2LPENSETR_SAI2LPEN BIT(17) +#define RCC_MC_APB2LPENSETR_SAI3LPEN BIT(18) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN BIT(20) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN BIT(21) +#define RCC_MC_APB2LPENSETR_FDCANLPEN BIT(24) + +/* RCC_MC_APB2LPENCLRR register fields */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN BIT(0) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN BIT(1) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN BIT(2) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN BIT(3) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN BIT(4) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN BIT(8) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN BIT(9) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN BIT(10) +#define RCC_MC_APB2LPENCLRR_USART6LPEN BIT(13) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN BIT(16) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN BIT(17) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN BIT(18) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN BIT(20) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN BIT(21) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN BIT(24) + +/* RCC_MC_APB3LPENSETR register fields */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN BIT(0) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN BIT(1) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN BIT(2) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN BIT(3) +#define RCC_MC_APB3LPENSETR_SAI4LPEN BIT(8) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN BIT(11) +#define RCC_MC_APB3LPENSETR_VREFLPEN BIT(13) +#define RCC_MC_APB3LPENSETR_TMPSENSLPEN BIT(16) +#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN BIT(17) + +/* RCC_MC_APB3LPENCLRR register fields */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN BIT(0) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN BIT(1) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN BIT(2) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN BIT(3) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN BIT(8) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN BIT(11) +#define RCC_MC_APB3LPENCLRR_VREFLPEN BIT(13) +#define RCC_MC_APB3LPENCLRR_TMPSENSLPEN BIT(16) +#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN BIT(17) + +/* RCC_MC_AHB2LPENSETR register fields */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN BIT(0) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN BIT(1) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN BIT(2) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN BIT(5) +#define RCC_MC_AHB2LPENSETR_USBOLPEN BIT(8) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN BIT(16) + +/* RCC_MC_AHB2LPENCLRR register fields */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN BIT(0) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN BIT(1) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN BIT(2) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN BIT(5) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN BIT(8) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN BIT(16) + +/* RCC_MC_AHB3LPENSETR register fields */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN BIT(0) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN BIT(4) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN BIT(5) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN BIT(6) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN BIT(7) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN BIT(11) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN BIT(12) + +/* RCC_MC_AHB3LPENCLRR register fields */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN BIT(0) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN BIT(4) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN BIT(5) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN BIT(6) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN BIT(7) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN BIT(11) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN BIT(12) + +/* RCC_MC_AHB4LPENSETR register fields */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN BIT(8) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN BIT(9) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN BIT(10) + +/* RCC_MC_AHB4LPENCLRR register fields */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN BIT(8) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN BIT(9) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN BIT(10) + +/* RCC_MC_AXIMLPENSETR register fields */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MC_AXIMLPENCLRR register fields */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MC_MLAHBLPENSETR register fields */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN BIT(0) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN BIT(1) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN BIT(2) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN BIT(4) + +/* RCC_MC_MLAHBLPENCLRR register fields */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN BIT(0) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN BIT(1) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN BIT(2) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN BIT(4) + +/* RCC_MC_RSTSCLRR register fields */ +#define RCC_MC_RSTSCLRR_PORRSTF BIT(0) +#define RCC_MC_RSTSCLRR_BORRSTF BIT(1) +#define RCC_MC_RSTSCLRR_PADRSTF BIT(2) +#define RCC_MC_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_MC_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_MC_RSTSCLRR_MCURSTF BIT(5) +#define RCC_MC_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_MC_RSTSCLRR_MCSYSRSTF BIT(7) +#define RCC_MC_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_MC_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_MC_RSTSCLRR_WWDG1RSTF BIT(10) + +/* RCC_MC_CIER register fields */ +#define RCC_MC_CIER_LSIRDYIE BIT(0) +#define RCC_MC_CIER_LSERDYIE BIT(1) +#define RCC_MC_CIER_HSIRDYIE BIT(2) +#define RCC_MC_CIER_HSERDYIE BIT(3) +#define RCC_MC_CIER_CSIRDYIE BIT(4) +#define RCC_MC_CIER_PLL1DYIE BIT(8) +#define RCC_MC_CIER_PLL2DYIE BIT(9) +#define RCC_MC_CIER_PLL3DYIE BIT(10) +#define RCC_MC_CIER_PLL4DYIE BIT(11) +#define RCC_MC_CIER_LSECSSIE BIT(16) +#define RCC_MC_CIER_WKUPIE BIT(20) + +/* RCC_MC_CIFR register fields */ +#define RCC_MC_CIFR_LSIRDYF BIT(0) +#define RCC_MC_CIFR_LSERDYF BIT(1) +#define RCC_MC_CIFR_HSIRDYF BIT(2) +#define RCC_MC_CIFR_HSERDYF BIT(3) +#define RCC_MC_CIFR_CSIRDYF BIT(4) +#define RCC_MC_CIFR_PLL1DYF BIT(8) +#define RCC_MC_CIFR_PLL2DYF BIT(9) +#define RCC_MC_CIFR_PLL3DYF BIT(10) +#define RCC_MC_CIFR_PLL4DYF BIT(11) +#define RCC_MC_CIFR_LSECSSF BIT(16) +#define RCC_MC_CIFR_WKUPF BIT(20) + +/* RCC_VERR register fields */ +#define RCC_VERR_MINREV_MASK GENMASK(3, 0) +#define RCC_VERR_MINREV_SHIFT 0 +#define RCC_VERR_MAJREV_MASK GENMASK(7, 4) +#define RCC_VERR_MAJREV_SHIFT 4 + +/* Used for RCC_OCENSETR and RCC_OCENCLRR registers */ +#define RCC_OCENR_HSION BIT(0) +#define RCC_OCENR_HSIKERON BIT(1) +#define RCC_OCENR_CSION BIT(4) +#define RCC_OCENR_CSIKERON BIT(5) +#define RCC_OCENR_DIGBYP BIT(7) +#define RCC_OCENR_HSEON BIT(8) +#define RCC_OCENR_HSEKERON BIT(9) +#define RCC_OCENR_HSEBYP BIT(10) +#define RCC_OCENR_HSECSSON BIT(11) + +/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET U(4) + +/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ +#define RCC_RSTCLRR_OFFSET U(4) + +/* Used for most of DIVR register: max div for RTC */ +#define RCC_DIVR_DIV_MASK GENMASK(5, 0) +#define RCC_DIVR_DIVRDY BIT(31) + +/* Masks for specific DIVR registers */ +#define RCC_APBXDIV_MASK GENMASK(2, 0) +#define RCC_MPUDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MCUDIV_MASK GENMASK(3, 0) + +/* Used for most of RCC_SELR registers */ +#define RCC_SELR_SRC_MASK GENMASK(2, 0) +#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) +#define RCC_SELR_SRCRDY BIT(31) + +/* Used for all RCC_PLLCR registers */ +#define RCC_PLLNCR_PLLON BIT(0) +#define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) +#define RCC_PLLNCR_DIVPEN BIT(4) +#define RCC_PLLNCR_DIVQEN BIT(5) +#define RCC_PLLNCR_DIVREN BIT(6) +#define RCC_PLLNCR_DIVEN_SHIFT 4 + +/* Used for all RCC_PLLCFGR1 registers */ +#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) +#define RCC_PLLNCFGR1_DIVM_SHIFT 16 +#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLLNCFGR1_DIVN_SHIFT 0 + +/* Only for PLL3 and PLL4 */ +#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 + +/* Used for all RCC_PLLCFGR2 registers */ +#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_SHIFT 0 +#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLLNCFGR2_DIVQ_SHIFT 8 +#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLLNCFGR2_DIVR_SHIFT 16 + +/* Used for all RCC_PLLFRACR registers */ +#define RCC_PLLNFRACR_FRACV_SHIFT 3 +#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLLNFRACR_FRACLE BIT(16) + +/* Used for all RCC_PLLCSGR registers */ +#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 +#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 +#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 +#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) + +/* Used for TIMER Prescaler */ +#define RCC_TIMGXPRER_TIMGXPRE BIT(0) + +/* Used for RCC_MCO related operations */ +#define RCC_MCOCFG_MCOON BIT(12) +#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) +#define RCC_MCOCFG_MCODIV_SHIFT 4 +#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) + +#endif /* STM32MP1_RCC_H */ diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index 14f93fdce..d79422508 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -1,2328 +1,12 @@ /* - * Copyright (c) 2015-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef STM32MP1_RCC_H -#define STM32MP1_RCC_H - -#include - -#define RCC_TZCR U(0x00) -#define RCC_OCENSETR U(0x0C) -#define RCC_OCENCLRR U(0x10) -#define RCC_HSICFGR U(0x18) -#define RCC_CSICFGR U(0x1C) -#define RCC_MPCKSELR U(0x20) -#define RCC_ASSCKSELR U(0x24) -#define RCC_RCK12SELR U(0x28) -#define RCC_MPCKDIVR U(0x2C) -#define RCC_AXIDIVR U(0x30) -#define RCC_APB4DIVR U(0x3C) -#define RCC_APB5DIVR U(0x40) -#define RCC_RTCDIVR U(0x44) -#define RCC_MSSCKSELR U(0x48) -#define RCC_PLL1CR U(0x80) -#define RCC_PLL1CFGR1 U(0x84) -#define RCC_PLL1CFGR2 U(0x88) -#define RCC_PLL1FRACR U(0x8C) -#define RCC_PLL1CSGR U(0x90) -#define RCC_PLL2CR U(0x94) -#define RCC_PLL2CFGR1 U(0x98) -#define RCC_PLL2CFGR2 U(0x9C) -#define RCC_PLL2FRACR U(0xA0) -#define RCC_PLL2CSGR U(0xA4) -#define RCC_I2C46CKSELR U(0xC0) -#define RCC_SPI6CKSELR U(0xC4) -#define RCC_UART1CKSELR U(0xC8) -#define RCC_RNG1CKSELR U(0xCC) -#define RCC_CPERCKSELR U(0xD0) -#define RCC_STGENCKSELR U(0xD4) -#define RCC_DDRITFCR U(0xD8) -#define RCC_MP_BOOTCR U(0x100) -#define RCC_MP_SREQSETR U(0x104) -#define RCC_MP_SREQCLRR U(0x108) -#define RCC_MP_GCR U(0x10C) -#define RCC_MP_APRSTCR U(0x110) -#define RCC_MP_APRSTSR U(0x114) -#define RCC_BDCR U(0x140) -#define RCC_RDLSICR U(0x144) -#define RCC_APB4RSTSETR U(0x180) -#define RCC_APB4RSTCLRR U(0x184) -#define RCC_APB5RSTSETR U(0x188) -#define RCC_APB5RSTCLRR U(0x18C) -#define RCC_AHB5RSTSETR U(0x190) -#define RCC_AHB5RSTCLRR U(0x194) -#define RCC_AHB6RSTSETR U(0x198) -#define RCC_AHB6RSTCLRR U(0x19C) -#define RCC_TZAHB6RSTSETR U(0x1A0) -#define RCC_TZAHB6RSTCLRR U(0x1A4) -#define RCC_MP_APB4ENSETR U(0x200) -#define RCC_MP_APB4ENCLRR U(0x204) -#define RCC_MP_APB5ENSETR U(0x208) -#define RCC_MP_APB5ENCLRR U(0x20C) -#define RCC_MP_AHB5ENSETR U(0x210) -#define RCC_MP_AHB5ENCLRR U(0x214) -#define RCC_MP_AHB6ENSETR U(0x218) -#define RCC_MP_AHB6ENCLRR U(0x21C) -#define RCC_MP_TZAHB6ENSETR U(0x220) -#define RCC_MP_TZAHB6ENCLRR U(0x224) -#define RCC_MC_APB4ENSETR U(0x280) -#define RCC_MC_APB4ENCLRR U(0x284) -#define RCC_MC_APB5ENSETR U(0x288) -#define RCC_MC_APB5ENCLRR U(0x28C) -#define RCC_MC_AHB5ENSETR U(0x290) -#define RCC_MC_AHB5ENCLRR U(0x294) -#define RCC_MC_AHB6ENSETR U(0x298) -#define RCC_MC_AHB6ENCLRR U(0x29C) -#define RCC_MP_APB4LPENSETR U(0x300) -#define RCC_MP_APB4LPENCLRR U(0x304) -#define RCC_MP_APB5LPENSETR U(0x308) -#define RCC_MP_APB5LPENCLRR U(0x30C) -#define RCC_MP_AHB5LPENSETR U(0x310) -#define RCC_MP_AHB5LPENCLRR U(0x314) -#define RCC_MP_AHB6LPENSETR U(0x318) -#define RCC_MP_AHB6LPENCLRR U(0x31C) -#define RCC_MP_TZAHB6LPENSETR U(0x320) -#define RCC_MP_TZAHB6LPENCLRR U(0x324) -#define RCC_MC_APB4LPENSETR U(0x380) -#define RCC_MC_APB4LPENCLRR U(0x384) -#define RCC_MC_APB5LPENSETR U(0x388) -#define RCC_MC_APB5LPENCLRR U(0x38C) -#define RCC_MC_AHB5LPENSETR U(0x390) -#define RCC_MC_AHB5LPENCLRR U(0x394) -#define RCC_MC_AHB6LPENSETR U(0x398) -#define RCC_MC_AHB6LPENCLRR U(0x39C) -#define RCC_BR_RSTSCLRR U(0x400) -#define RCC_MP_GRSTCSETR U(0x404) -#define RCC_MP_RSTSCLRR U(0x408) -#define RCC_MP_IWDGFZSETR U(0x40C) -#define RCC_MP_IWDGFZCLRR U(0x410) -#define RCC_MP_CIER U(0x414) -#define RCC_MP_CIFR U(0x418) -#define RCC_PWRLPDLYCR U(0x41C) -#define RCC_MP_RSTSSETR U(0x420) -#define RCC_MCO1CFGR U(0x800) -#define RCC_MCO2CFGR U(0x804) -#define RCC_OCRDYR U(0x808) -#define RCC_DBGCFGR U(0x80C) -#define RCC_RCK3SELR U(0x820) -#define RCC_RCK4SELR U(0x824) -#define RCC_TIMG1PRER U(0x828) -#define RCC_TIMG2PRER U(0x82C) -#define RCC_MCUDIVR U(0x830) -#define RCC_APB1DIVR U(0x834) -#define RCC_APB2DIVR U(0x838) -#define RCC_APB3DIVR U(0x83C) -#define RCC_PLL3CR U(0x880) -#define RCC_PLL3CFGR1 U(0x884) -#define RCC_PLL3CFGR2 U(0x888) -#define RCC_PLL3FRACR U(0x88C) -#define RCC_PLL3CSGR U(0x890) -#define RCC_PLL4CR U(0x894) -#define RCC_PLL4CFGR1 U(0x898) -#define RCC_PLL4CFGR2 U(0x89C) -#define RCC_PLL4FRACR U(0x8A0) -#define RCC_PLL4CSGR U(0x8A4) -#define RCC_I2C12CKSELR U(0x8C0) -#define RCC_I2C35CKSELR U(0x8C4) -#define RCC_SAI1CKSELR U(0x8C8) -#define RCC_SAI2CKSELR U(0x8CC) -#define RCC_SAI3CKSELR U(0x8D0) -#define RCC_SAI4CKSELR U(0x8D4) -#define RCC_SPI2S1CKSELR U(0x8D8) -#define RCC_SPI2S23CKSELR U(0x8DC) -#define RCC_SPI45CKSELR U(0x8E0) -#define RCC_UART6CKSELR U(0x8E4) -#define RCC_UART24CKSELR U(0x8E8) -#define RCC_UART35CKSELR U(0x8EC) -#define RCC_UART78CKSELR U(0x8F0) -#define RCC_SDMMC12CKSELR U(0x8F4) -#define RCC_SDMMC3CKSELR U(0x8F8) -#define RCC_ETHCKSELR U(0x8FC) -#define RCC_QSPICKSELR U(0x900) -#define RCC_FMCCKSELR U(0x904) -#define RCC_FDCANCKSELR U(0x90C) -#define RCC_SPDIFCKSELR U(0x914) -#define RCC_CECCKSELR U(0x918) -#define RCC_USBCKSELR U(0x91C) -#define RCC_RNG2CKSELR U(0x920) -#define RCC_DSICKSELR U(0x924) -#define RCC_ADCCKSELR U(0x928) -#define RCC_LPTIM45CKSELR U(0x92C) -#define RCC_LPTIM23CKSELR U(0x930) -#define RCC_LPTIM1CKSELR U(0x934) -#define RCC_APB1RSTSETR U(0x980) -#define RCC_APB1RSTCLRR U(0x984) -#define RCC_APB2RSTSETR U(0x988) -#define RCC_APB2RSTCLRR U(0x98C) -#define RCC_APB3RSTSETR U(0x990) -#define RCC_APB3RSTCLRR U(0x994) -#define RCC_AHB2RSTSETR U(0x998) -#define RCC_AHB2RSTCLRR U(0x99C) -#define RCC_AHB3RSTSETR U(0x9A0) -#define RCC_AHB3RSTCLRR U(0x9A4) -#define RCC_AHB4RSTSETR U(0x9A8) -#define RCC_AHB4RSTCLRR U(0x9AC) -#define RCC_MP_APB1ENSETR U(0xA00) -#define RCC_MP_APB1ENCLRR U(0xA04) -#define RCC_MP_APB2ENSETR U(0xA08) -#define RCC_MP_APB2ENCLRR U(0xA0C) -#define RCC_MP_APB3ENSETR U(0xA10) -#define RCC_MP_APB3ENCLRR U(0xA14) -#define RCC_MP_AHB2ENSETR U(0xA18) -#define RCC_MP_AHB2ENCLRR U(0xA1C) -#define RCC_MP_AHB3ENSETR U(0xA20) -#define RCC_MP_AHB3ENCLRR U(0xA24) -#define RCC_MP_AHB4ENSETR U(0xA28) -#define RCC_MP_AHB4ENCLRR U(0xA2C) -#define RCC_MP_MLAHBENSETR U(0xA38) -#define RCC_MP_MLAHBENCLRR U(0xA3C) -#define RCC_MC_APB1ENSETR U(0xA80) -#define RCC_MC_APB1ENCLRR U(0xA84) -#define RCC_MC_APB2ENSETR U(0xA88) -#define RCC_MC_APB2ENCLRR U(0xA8C) -#define RCC_MC_APB3ENSETR U(0xA90) -#define RCC_MC_APB3ENCLRR U(0xA94) -#define RCC_MC_AHB2ENSETR U(0xA98) -#define RCC_MC_AHB2ENCLRR U(0xA9C) -#define RCC_MC_AHB3ENSETR U(0xAA0) -#define RCC_MC_AHB3ENCLRR U(0xAA4) -#define RCC_MC_AHB4ENSETR U(0xAA8) -#define RCC_MC_AHB4ENCLRR U(0xAAC) -#define RCC_MC_AXIMENSETR U(0xAB0) -#define RCC_MC_AXIMENCLRR U(0xAB4) -#define RCC_MC_MLAHBENSETR U(0xAB8) -#define RCC_MC_MLAHBENCLRR U(0xABC) -#define RCC_MP_APB1LPENSETR U(0xB00) -#define RCC_MP_APB1LPENCLRR U(0xB04) -#define RCC_MP_APB2LPENSETR U(0xB08) -#define RCC_MP_APB2LPENCLRR U(0xB0C) -#define RCC_MP_APB3LPENSETR U(0xB10) -#define RCC_MP_APB3LPENCLRR U(0xB14) -#define RCC_MP_AHB2LPENSETR U(0xB18) -#define RCC_MP_AHB2LPENCLRR U(0xB1C) -#define RCC_MP_AHB3LPENSETR U(0xB20) -#define RCC_MP_AHB3LPENCLRR U(0xB24) -#define RCC_MP_AHB4LPENSETR U(0xB28) -#define RCC_MP_AHB4LPENCLRR U(0xB2C) -#define RCC_MP_AXIMLPENSETR U(0xB30) -#define RCC_MP_AXIMLPENCLRR U(0xB34) -#define RCC_MP_MLAHBLPENSETR U(0xB38) -#define RCC_MP_MLAHBLPENCLRR U(0xB3C) -#define RCC_MC_APB1LPENSETR U(0xB80) -#define RCC_MC_APB1LPENCLRR U(0xB84) -#define RCC_MC_APB2LPENSETR U(0xB88) -#define RCC_MC_APB2LPENCLRR U(0xB8C) -#define RCC_MC_APB3LPENSETR U(0xB90) -#define RCC_MC_APB3LPENCLRR U(0xB94) -#define RCC_MC_AHB2LPENSETR U(0xB98) -#define RCC_MC_AHB2LPENCLRR U(0xB9C) -#define RCC_MC_AHB3LPENSETR U(0xBA0) -#define RCC_MC_AHB3LPENCLRR U(0xBA4) -#define RCC_MC_AHB4LPENSETR U(0xBA8) -#define RCC_MC_AHB4LPENCLRR U(0xBAC) -#define RCC_MC_AXIMLPENSETR U(0xBB0) -#define RCC_MC_AXIMLPENCLRR U(0xBB4) -#define RCC_MC_MLAHBLPENSETR U(0xBB8) -#define RCC_MC_MLAHBLPENCLRR U(0xBBC) -#define RCC_MC_RSTSCLRR U(0xC00) -#define RCC_MC_CIER U(0xC14) -#define RCC_MC_CIFR U(0xC18) -#define RCC_VERR U(0xFF4) -#define RCC_IDR U(0xFF8) -#define RCC_SIDR U(0xFFC) - -/* RCC_TZCR register fields */ -#define RCC_TZCR_TZEN BIT(0) -#define RCC_TZCR_MCKPROT BIT(1) - -/* RCC_OCENSETR register fields */ -#define RCC_OCENSETR_HSION BIT(0) -#define RCC_OCENSETR_HSIKERON BIT(1) -#define RCC_OCENSETR_CSION BIT(4) -#define RCC_OCENSETR_CSIKERON BIT(5) -#define RCC_OCENSETR_DIGBYP BIT(7) -#define RCC_OCENSETR_HSEON BIT(8) -#define RCC_OCENSETR_HSEKERON BIT(9) -#define RCC_OCENSETR_HSEBYP BIT(10) -#define RCC_OCENSETR_HSECSSON BIT(11) - -/* RCC_OCENCLRR register fields */ -#define RCC_OCENCLRR_HSION BIT(0) -#define RCC_OCENCLRR_HSIKERON BIT(1) -#define RCC_OCENCLRR_CSION BIT(4) -#define RCC_OCENCLRR_CSIKERON BIT(5) -#define RCC_OCENCLRR_DIGBYP BIT(7) -#define RCC_OCENCLRR_HSEON BIT(8) -#define RCC_OCENCLRR_HSEKERON BIT(9) -#define RCC_OCENCLRR_HSEBYP BIT(10) - -/* RCC_HSICFGR register fields */ -#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) -#define RCC_HSICFGR_HSIDIV_SHIFT 0 -#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) -#define RCC_HSICFGR_HSITRIM_SHIFT 8 -#define RCC_HSICFGR_HSICAL_MASK GENMASK(24, 16) -#define RCC_HSICFGR_HSICAL_SHIFT 16 -#define RCC_HSICFGR_HSICAL_TEMP_MASK GENMASK(27, 25) - -/* RCC_CSICFGR register fields */ -#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) -#define RCC_CSICFGR_CSITRIM_SHIFT 8 -#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) -#define RCC_CSICFGR_CSICAL_SHIFT 16 - -/* RCC_MPCKSELR register fields */ -#define RCC_MPCKSELR_HSI 0x00000000 -#define RCC_MPCKSELR_HSE 0x00000001 -#define RCC_MPCKSELR_PLL 0x00000002 -#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 -#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) -#define RCC_MPCKSELR_MPUSRC_SHIFT 0 -#define RCC_MPCKSELR_MPUSRCRDY BIT(31) - -/* RCC_ASSCKSELR register fields */ -#define RCC_ASSCKSELR_HSI 0x00000000 -#define RCC_ASSCKSELR_HSE 0x00000001 -#define RCC_ASSCKSELR_PLL 0x00000002 -#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) -#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 -#define RCC_ASSCKSELR_AXISSRCRDY BIT(31) - -/* RCC_RCK12SELR register fields */ -#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) -#define RCC_RCK12SELR_PLL12SRC_SHIFT 0 -#define RCC_RCK12SELR_PLL12SRCRDY BIT(31) - -/* RCC_MPCKDIVR register fields */ -#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(2, 0) -#define RCC_MPCKDIVR_MPUDIV_SHIFT 0 -#define RCC_MPCKDIVR_MPUDIVRDY BIT(31) - -/* RCC_AXIDIVR register fields */ -#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) -#define RCC_AXIDIVR_AXIDIV_SHIFT 0 -#define RCC_AXIDIVR_AXIDIVRDY BIT(31) - -/* RCC_APB4DIVR register fields */ -#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) -#define RCC_APB4DIVR_APB4DIV_SHIFT 0 -#define RCC_APB4DIVR_APB4DIVRDY BIT(31) - -/* RCC_APB5DIVR register fields */ -#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) -#define RCC_APB5DIVR_APB5DIV_SHIFT 0 -#define RCC_APB5DIVR_APB5DIVRDY BIT(31) - -/* RCC_RTCDIVR register fields */ -#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) -#define RCC_RTCDIVR_RTCDIV_SHIFT 0 - -/* RCC_MSSCKSELR register fields */ -#define RCC_MSSCKSELR_HSI 0x00000000 -#define RCC_MSSCKSELR_HSE 0x00000001 -#define RCC_MSSCKSELR_CSI 0x00000002 -#define RCC_MSSCKSELR_PLL 0x00000003 -#define RCC_MSSCKSELR_MCUSSRC_MASK GENMASK(1, 0) -#define RCC_MSSCKSELR_MCUSSRC_SHIFT 0 -#define RCC_MSSCKSELR_MCUSSRCRDY BIT(31) - -/* RCC_PLL1CR register fields */ -#define RCC_PLL1CR_PLLON BIT(0) -#define RCC_PLL1CR_PLL1RDY BIT(1) -#define RCC_PLL1CR_SSCG_CTRL BIT(2) -#define RCC_PLL1CR_DIVPEN BIT(4) -#define RCC_PLL1CR_DIVQEN BIT(5) -#define RCC_PLL1CR_DIVREN BIT(6) - -/* RCC_PLL1CFGR1 register fields */ -#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) -#define RCC_PLL1CFGR1_DIVN_SHIFT 0 -#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) -#define RCC_PLL1CFGR1_DIVM1_SHIFT 16 - -/* RCC_PLL1CFGR2 register fields */ -#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) -#define RCC_PLL1CFGR2_DIVP_SHIFT 0 -#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) -#define RCC_PLL1CFGR2_DIVQ_SHIFT 8 -#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) -#define RCC_PLL1CFGR2_DIVR_SHIFT 16 - -/* RCC_PLL1FRACR register fields */ -#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) -#define RCC_PLL1FRACR_FRACV_SHIFT 3 -#define RCC_PLL1FRACR_FRACLE BIT(16) - -/* RCC_PLL1CSGR register fields */ -#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) -#define RCC_PLL1CSGR_MOD_PER_SHIFT 0 -#define RCC_PLL1CSGR_TPDFN_DIS BIT(13) -#define RCC_PLL1CSGR_RPDFN_DIS BIT(14) -#define RCC_PLL1CSGR_SSCG_MODE BIT(15) -#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) -#define RCC_PLL1CSGR_INC_STEP_SHIFT 16 - -/* RCC_PLL2CR register fields */ -#define RCC_PLL2CR_PLLON BIT(0) -#define RCC_PLL2CR_PLL2RDY BIT(1) -#define RCC_PLL2CR_SSCG_CTRL BIT(2) -#define RCC_PLL2CR_DIVPEN BIT(4) -#define RCC_PLL2CR_DIVQEN BIT(5) -#define RCC_PLL2CR_DIVREN BIT(6) - -/* RCC_PLL2CFGR1 register fields */ -#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) -#define RCC_PLL2CFGR1_DIVN_SHIFT 0 -#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) -#define RCC_PLL2CFGR1_DIVM2_SHIFT 16 - -/* RCC_PLL2CFGR2 register fields */ -#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) -#define RCC_PLL2CFGR2_DIVP_SHIFT 0 -#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) -#define RCC_PLL2CFGR2_DIVQ_SHIFT 8 -#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) -#define RCC_PLL2CFGR2_DIVR_SHIFT 16 - -/* RCC_PLL2FRACR register fields */ -#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) -#define RCC_PLL2FRACR_FRACV_SHIFT 3 -#define RCC_PLL2FRACR_FRACLE BIT(16) - -/* RCC_PLL2CSGR register fields */ -#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) -#define RCC_PLL2CSGR_MOD_PER_SHIFT 0 -#define RCC_PLL2CSGR_TPDFN_DIS BIT(13) -#define RCC_PLL2CSGR_RPDFN_DIS BIT(14) -#define RCC_PLL2CSGR_SSCG_MODE BIT(15) -#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) -#define RCC_PLL2CSGR_INC_STEP_SHIFT 16 - -/* RCC_I2C46CKSELR register fields */ -#define RCC_I2C46CKSELR_I2C46SRC_MASK GENMASK(2, 0) -#define RCC_I2C46CKSELR_I2C46SRC_SHIFT 0 - -/* RCC_SPI6CKSELR register fields */ -#define RCC_SPI6CKSELR_SPI6SRC_MASK GENMASK(2, 0) -#define RCC_SPI6CKSELR_SPI6SRC_SHIFT 0 - -/* RCC_UART1CKSELR register fields */ -#define RCC_UART1CKSELR_UART1SRC_MASK GENMASK(2, 0) -#define RCC_UART1CKSELR_UART1SRC_SHIFT 0 - -/* RCC_RNG1CKSELR register fields */ -#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) -#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 - -/* RCC_CPERCKSELR register fields */ -#define RCC_CPERCKSELR_HSI 0x00000000 -#define RCC_CPERCKSELR_CSI 0x00000001 -#define RCC_CPERCKSELR_HSE 0x00000002 -#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) -#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 - -/* RCC_STGENCKSELR register fields */ -#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) -#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 - -/* RCC_DDRITFCR register fields */ -#define RCC_DDRITFCR_DDRC1EN BIT(0) -#define RCC_DDRITFCR_DDRC1LPEN BIT(1) -#define RCC_DDRITFCR_DDRC2EN BIT(2) -#define RCC_DDRITFCR_DDRC2LPEN BIT(3) -#define RCC_DDRITFCR_DDRPHYCEN BIT(4) -#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) -#define RCC_DDRITFCR_DDRCAPBEN BIT(6) -#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) -#define RCC_DDRITFCR_AXIDCGEN BIT(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) -#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) -#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 -#define RCC_DDRITFCR_DDRCAPBRST BIT(14) -#define RCC_DDRITFCR_DDRCAXIRST BIT(15) -#define RCC_DDRITFCR_DDRCORERST BIT(16) -#define RCC_DDRITFCR_DPHYAPBRST BIT(17) -#define RCC_DDRITFCR_DPHYRST BIT(18) -#define RCC_DDRITFCR_DPHYCTLRST BIT(19) -#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) -#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 -#define RCC_DDRITFCR_DDRCKMOD_SSR 0 -#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) -#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) -#define RCC_DDRITFCR_GSKPMOD BIT(23) -#define RCC_DDRITFCR_GSKPCTRL BIT(24) -#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) -#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 -#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) -#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 - -/* RCC_MP_BOOTCR register fields */ -#define RCC_MP_BOOTCR_MCU_BEN BIT(0) -#define RCC_MP_BOOTCR_MPU_BEN BIT(1) - -/* RCC_MP_SREQSETR register fields */ -#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) -#define RCC_MP_SREQSETR_STPREQ_P1 BIT(1) - -/* RCC_MP_SREQCLRR register fields */ -#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) -#define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1) - -/* RCC_MP_GCR register fields */ -#define RCC_MP_GCR_BOOT_MCU BIT(0) - -/* RCC_MP_APRSTCR register fields */ -#define RCC_MP_APRSTCR_RDCTLEN BIT(0) -#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) -#define RCC_MP_APRSTCR_RSTTO_SHIFT 8 - -/* RCC_MP_APRSTSR register fields */ -#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) -#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 - -/* RCC_BDCR register fields */ -#define RCC_BDCR_LSEON BIT(0) -#define RCC_BDCR_LSEBYP BIT(1) -#define RCC_BDCR_LSERDY BIT(2) -#define RCC_BDCR_DIGBYP BIT(3) -#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) -#define RCC_BDCR_LSEDRV_SHIFT 4 -#define RCC_BDCR_LSECSSON BIT(8) -#define RCC_BDCR_LSECSSD BIT(9) -#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) -#define RCC_BDCR_RTCSRC_SHIFT 16 -#define RCC_BDCR_RTCCKEN BIT(20) -#define RCC_BDCR_VSWRST BIT(31) - -/* RCC_RDLSICR register fields */ -#define RCC_RDLSICR_LSION BIT(0) -#define RCC_RDLSICR_LSIRDY BIT(1) -#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) -#define RCC_RDLSICR_MRD_SHIFT 16 -#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) -#define RCC_RDLSICR_EADLY_SHIFT 24 -#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) -#define RCC_RDLSICR_SPARE_SHIFT 27 - -/* RCC_APB4RSTSETR register fields */ -#define RCC_APB4RSTSETR_LTDCRST BIT(0) -#define RCC_APB4RSTSETR_DSIRST BIT(4) -#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) -#define RCC_APB4RSTSETR_USBPHYRST BIT(16) - -/* RCC_APB4RSTCLRR register fields */ -#define RCC_APB4RSTCLRR_LTDCRST BIT(0) -#define RCC_APB4RSTCLRR_DSIRST BIT(4) -#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) -#define RCC_APB4RSTCLRR_USBPHYRST BIT(16) - -/* RCC_APB5RSTSETR register fields */ -#define RCC_APB5RSTSETR_SPI6RST BIT(0) -#define RCC_APB5RSTSETR_I2C4RST BIT(2) -#define RCC_APB5RSTSETR_I2C6RST BIT(3) -#define RCC_APB5RSTSETR_USART1RST BIT(4) -#define RCC_APB5RSTSETR_STGENRST BIT(20) - -/* RCC_APB5RSTCLRR register fields */ -#define RCC_APB5RSTCLRR_SPI6RST BIT(0) -#define RCC_APB5RSTCLRR_I2C4RST BIT(2) -#define RCC_APB5RSTCLRR_I2C6RST BIT(3) -#define RCC_APB5RSTCLRR_USART1RST BIT(4) -#define RCC_APB5RSTCLRR_STGENRST BIT(20) - -/* RCC_AHB5RSTSETR register fields */ -#define RCC_AHB5RSTSETR_GPIOZRST BIT(0) -#define RCC_AHB5RSTSETR_CRYP1RST BIT(4) -#define RCC_AHB5RSTSETR_HASH1RST BIT(5) -#define RCC_AHB5RSTSETR_RNG1RST BIT(6) -#define RCC_AHB5RSTSETR_AXIMCRST BIT(16) - -/* RCC_AHB5RSTCLRR register fields */ -#define RCC_AHB5RSTCLRR_GPIOZRST BIT(0) -#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) -#define RCC_AHB5RSTCLRR_HASH1RST BIT(5) -#define RCC_AHB5RSTCLRR_RNG1RST BIT(6) -#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) - -/* RCC_AHB6RSTSETR register fields */ -#define RCC_AHB6RSTSETR_GPURST BIT(5) -#define RCC_AHB6RSTSETR_ETHMACRST BIT(10) -#define RCC_AHB6RSTSETR_FMCRST BIT(12) -#define RCC_AHB6RSTSETR_QSPIRST BIT(14) -#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) -#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) -#define RCC_AHB6RSTSETR_CRC1RST BIT(20) -#define RCC_AHB6RSTSETR_USBHRST BIT(24) - -/* RCC_AHB6RSTCLRR register fields */ -#define RCC_AHB6RSTCLRR_ETHMACRST BIT(10) -#define RCC_AHB6RSTCLRR_FMCRST BIT(12) -#define RCC_AHB6RSTCLRR_QSPIRST BIT(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) -#define RCC_AHB6RSTCLRR_CRC1RST BIT(20) -#define RCC_AHB6RSTCLRR_USBHRST BIT(24) - -/* RCC_TZAHB6RSTSETR register fields */ -#define RCC_TZAHB6RSTSETR_MDMARST BIT(0) - -/* RCC_TZAHB6RSTCLRR register fields */ -#define RCC_TZAHB6RSTCLRR_MDMARST BIT(0) - -/* RCC_MP_APB4ENSETR register fields */ -#define RCC_MP_APB4ENSETR_LTDCEN BIT(0) -#define RCC_MP_APB4ENSETR_DSIEN BIT(4) -#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) -#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) -#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) -#define RCC_MP_APB4ENSETR_STGENROEN BIT(20) - -/* RCC_MP_APB4ENCLRR register fields */ -#define RCC_MP_APB4ENCLRR_LTDCEN BIT(0) -#define RCC_MP_APB4ENCLRR_DSIEN BIT(4) -#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) -#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) - -/* RCC_MP_APB5ENSETR register fields */ -#define RCC_MP_APB5ENSETR_SPI6EN BIT(0) -#define RCC_MP_APB5ENSETR_I2C4EN BIT(2) -#define RCC_MP_APB5ENSETR_I2C6EN BIT(3) -#define RCC_MP_APB5ENSETR_USART1EN BIT(4) -#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) -#define RCC_MP_APB5ENSETR_TZC1EN BIT(11) -#define RCC_MP_APB5ENSETR_TZC2EN BIT(12) -#define RCC_MP_APB5ENSETR_TZPCEN BIT(13) -#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) -#define RCC_MP_APB5ENSETR_BSECEN BIT(16) -#define RCC_MP_APB5ENSETR_STGENEN BIT(20) - -/* RCC_MP_APB5ENCLRR register fields */ -#define RCC_MP_APB5ENCLRR_SPI6EN BIT(0) -#define RCC_MP_APB5ENCLRR_I2C4EN BIT(2) -#define RCC_MP_APB5ENCLRR_I2C6EN BIT(3) -#define RCC_MP_APB5ENCLRR_USART1EN BIT(4) -#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) -#define RCC_MP_APB5ENCLRR_TZC1EN BIT(11) -#define RCC_MP_APB5ENCLRR_TZC2EN BIT(12) -#define RCC_MP_APB5ENCLRR_TZPCEN BIT(13) -#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) -#define RCC_MP_APB5ENCLRR_BSECEN BIT(16) -#define RCC_MP_APB5ENCLRR_STGENEN BIT(20) - -/* RCC_MP_AHB5ENSETR register fields */ -#define RCC_MP_AHB5ENSETR_GPIOZEN BIT(0) -#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) -#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) -#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) -#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) -#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) - -/* RCC_MP_AHB5ENCLRR register fields */ -#define RCC_MP_AHB5ENCLRR_GPIOZEN BIT(0) -#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) -#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) -#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) -#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) -#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) - -/* RCC_MP_AHB6ENSETR register fields */ -#define RCC_MP_AHB6ENSETR_MDMAEN BIT(0) -#define RCC_MP_AHB6ENSETR_GPUEN BIT(5) -#define RCC_MP_AHB6ENSETR_ETHCKEN BIT(7) -#define RCC_MP_AHB6ENSETR_ETHTXEN BIT(8) -#define RCC_MP_AHB6ENSETR_ETHRXEN BIT(9) -#define RCC_MP_AHB6ENSETR_ETHMACEN BIT(10) -#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) -#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) -#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) -#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) -#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) -#define RCC_MP_AHB6ENSETR_USBHEN BIT(24) - -/* RCC_MP_AHB6ENCLRR register fields */ -#define RCC_MP_AHB6ENCLRR_MDMAEN BIT(0) -#define RCC_MP_AHB6ENCLRR_GPUEN BIT(5) -#define RCC_MP_AHB6ENCLRR_ETHCKEN BIT(7) -#define RCC_MP_AHB6ENCLRR_ETHTXEN BIT(8) -#define RCC_MP_AHB6ENCLRR_ETHRXEN BIT(9) -#define RCC_MP_AHB6ENCLRR_ETHMACEN BIT(10) -#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) -#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) -#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) -#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) -#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) -#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) - -/* RCC_MP_TZAHB6ENSETR register fields */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN BIT(0) - -/* RCC_MP_TZAHB6ENCLRR register fields */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN BIT(0) - -/* RCC_MC_APB4ENSETR register fields */ -#define RCC_MC_APB4ENSETR_LTDCEN BIT(0) -#define RCC_MC_APB4ENSETR_DSIEN BIT(4) -#define RCC_MC_APB4ENSETR_DDRPERFMEN BIT(8) -#define RCC_MC_APB4ENSETR_USBPHYEN BIT(16) -#define RCC_MC_APB4ENSETR_STGENROEN BIT(20) - -/* RCC_MC_APB4ENCLRR register fields */ -#define RCC_MC_APB4ENCLRR_LTDCEN BIT(0) -#define RCC_MC_APB4ENCLRR_DSIEN BIT(4) -#define RCC_MC_APB4ENCLRR_DDRPERFMEN BIT(8) -#define RCC_MC_APB4ENCLRR_USBPHYEN BIT(16) -#define RCC_MC_APB4ENCLRR_STGENROEN BIT(20) - -/* RCC_MC_APB5ENSETR register fields */ -#define RCC_MC_APB5ENSETR_SPI6EN BIT(0) -#define RCC_MC_APB5ENSETR_I2C4EN BIT(2) -#define RCC_MC_APB5ENSETR_I2C6EN BIT(3) -#define RCC_MC_APB5ENSETR_USART1EN BIT(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN BIT(8) -#define RCC_MC_APB5ENSETR_TZC1EN BIT(11) -#define RCC_MC_APB5ENSETR_TZC2EN BIT(12) -#define RCC_MC_APB5ENSETR_TZPCEN BIT(13) -#define RCC_MC_APB5ENSETR_BSECEN BIT(16) -#define RCC_MC_APB5ENSETR_STGENEN BIT(20) - -/* RCC_MC_APB5ENCLRR register fields */ -#define RCC_MC_APB5ENCLRR_SPI6EN BIT(0) -#define RCC_MC_APB5ENCLRR_I2C4EN BIT(2) -#define RCC_MC_APB5ENCLRR_I2C6EN BIT(3) -#define RCC_MC_APB5ENCLRR_USART1EN BIT(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN BIT(8) -#define RCC_MC_APB5ENCLRR_TZC1EN BIT(11) -#define RCC_MC_APB5ENCLRR_TZC2EN BIT(12) -#define RCC_MC_APB5ENCLRR_TZPCEN BIT(13) -#define RCC_MC_APB5ENCLRR_BSECEN BIT(16) -#define RCC_MC_APB5ENCLRR_STGENEN BIT(20) - -/* RCC_MC_AHB5ENSETR register fields */ -#define RCC_MC_AHB5ENSETR_GPIOZEN BIT(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN BIT(4) -#define RCC_MC_AHB5ENSETR_HASH1EN BIT(5) -#define RCC_MC_AHB5ENSETR_RNG1EN BIT(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN BIT(8) - -/* RCC_MC_AHB5ENCLRR register fields */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN BIT(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN BIT(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN BIT(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN BIT(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN BIT(8) - -/* RCC_MC_AHB6ENSETR register fields */ -#define RCC_MC_AHB6ENSETR_MDMAEN BIT(0) -#define RCC_MC_AHB6ENSETR_GPUEN BIT(5) -#define RCC_MC_AHB6ENSETR_ETHCKEN BIT(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN BIT(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN BIT(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN BIT(10) -#define RCC_MC_AHB6ENSETR_FMCEN BIT(12) -#define RCC_MC_AHB6ENSETR_QSPIEN BIT(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN BIT(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN BIT(17) -#define RCC_MC_AHB6ENSETR_CRC1EN BIT(20) -#define RCC_MC_AHB6ENSETR_USBHEN BIT(24) - -/* RCC_MC_AHB6ENCLRR register fields */ -#define RCC_MC_AHB6ENCLRR_MDMAEN BIT(0) -#define RCC_MC_AHB6ENCLRR_GPUEN BIT(5) -#define RCC_MC_AHB6ENCLRR_ETHCKEN BIT(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN BIT(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN BIT(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN BIT(10) -#define RCC_MC_AHB6ENCLRR_FMCEN BIT(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN BIT(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN BIT(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN BIT(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN BIT(20) -#define RCC_MC_AHB6ENCLRR_USBHEN BIT(24) - -/* RCC_MP_APB4LPENSETR register fields */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN BIT(0) -#define RCC_MP_APB4LPENSETR_DSILPEN BIT(4) -#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) - -/* RCC_MP_APB4LPENCLRR register fields */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN BIT(0) -#define RCC_MP_APB4LPENCLRR_DSILPEN BIT(4) -#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) - -/* RCC_MP_APB5LPENSETR register fields */ -#define RCC_MP_APB5LPENSETR_SPI6LPEN BIT(0) -#define RCC_MP_APB5LPENSETR_I2C4LPEN BIT(2) -#define RCC_MP_APB5LPENSETR_I2C6LPEN BIT(3) -#define RCC_MP_APB5LPENSETR_USART1LPEN BIT(4) -#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) -#define RCC_MP_APB5LPENSETR_TZC1LPEN BIT(11) -#define RCC_MP_APB5LPENSETR_TZC2LPEN BIT(12) -#define RCC_MP_APB5LPENSETR_TZPCLPEN BIT(13) -#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) -#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) -#define RCC_MP_APB5LPENSETR_STGENLPEN BIT(20) -#define RCC_MP_APB5LPENSETR_STGENSTPEN BIT(21) - -/* RCC_MP_APB5LPENCLRR register fields */ -#define RCC_MP_APB5LPENCLRR_SPI6LPEN BIT(0) -#define RCC_MP_APB5LPENCLRR_I2C4LPEN BIT(2) -#define RCC_MP_APB5LPENCLRR_I2C6LPEN BIT(3) -#define RCC_MP_APB5LPENCLRR_USART1LPEN BIT(4) -#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) -#define RCC_MP_APB5LPENCLRR_TZC1LPEN BIT(11) -#define RCC_MP_APB5LPENCLRR_TZC2LPEN BIT(12) -#define RCC_MP_APB5LPENCLRR_TZPCLPEN BIT(13) -#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) -#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) -#define RCC_MP_APB5LPENCLRR_STGENLPEN BIT(20) -#define RCC_MP_APB5LPENCLRR_STGENSTPEN BIT(21) - -/* RCC_MP_AHB5LPENSETR register fields */ -#define RCC_MP_AHB5LPENSETR_GPIOZLPEN BIT(0) -#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) -#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) -#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) -#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) - -/* RCC_MP_AHB5LPENCLRR register fields */ -#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN BIT(0) -#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) -#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) -#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) -#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) - -/* RCC_MP_AHB6LPENSETR register fields */ -#define RCC_MP_AHB6LPENSETR_MDMALPEN BIT(0) -#define RCC_MP_AHB6LPENSETR_GPULPEN BIT(5) -#define RCC_MP_AHB6LPENSETR_ETHCKLPEN BIT(7) -#define RCC_MP_AHB6LPENSETR_ETHTXLPEN BIT(8) -#define RCC_MP_AHB6LPENSETR_ETHRXLPEN BIT(9) -#define RCC_MP_AHB6LPENSETR_ETHMACLPEN BIT(10) -#define RCC_MP_AHB6LPENSETR_ETHSTPEN BIT(11) -#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) -#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) -#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) -#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) -#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) -#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) - -/* RCC_MP_AHB6LPENCLRR register fields */ -#define RCC_MP_AHB6LPENCLRR_MDMALPEN BIT(0) -#define RCC_MP_AHB6LPENCLRR_GPULPEN BIT(5) -#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN BIT(7) -#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN BIT(8) -#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN BIT(9) -#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN BIT(10) -#define RCC_MP_AHB6LPENCLRR_ETHSTPEN BIT(11) -#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) -#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) -#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) -#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) -#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) -#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) - -/* RCC_MP_TZAHB6LPENSETR register fields */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN BIT(0) - -/* RCC_MP_TZAHB6LPENCLRR register fields */ -#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN BIT(0) - -/* RCC_MC_APB4LPENSETR register fields */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN BIT(0) -#define RCC_MC_APB4LPENSETR_DSILPEN BIT(4) -#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN BIT(8) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN BIT(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN BIT(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN BIT(21) - -/* RCC_MC_APB4LPENCLRR register fields */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN BIT(0) -#define RCC_MC_APB4LPENCLRR_DSILPEN BIT(4) -#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN BIT(8) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN BIT(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN BIT(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN BIT(21) - -/* RCC_MC_APB5LPENSETR register fields */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN BIT(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN BIT(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN BIT(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN BIT(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN BIT(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN BIT(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN BIT(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN BIT(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN BIT(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN BIT(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN BIT(21) - -/* RCC_MC_APB5LPENCLRR register fields */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN BIT(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN BIT(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN BIT(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN BIT(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN BIT(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN BIT(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN BIT(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN BIT(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN BIT(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN BIT(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN BIT(21) - -/* RCC_MC_AHB5LPENSETR register fields */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN BIT(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN BIT(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN BIT(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN BIT(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN BIT(8) - -/* RCC_MC_AHB5LPENCLRR register fields */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN BIT(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN BIT(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN BIT(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN BIT(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) - -/* RCC_MC_AHB6LPENSETR register fields */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN BIT(0) -#define RCC_MC_AHB6LPENSETR_GPULPEN BIT(5) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN BIT(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN BIT(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN BIT(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN BIT(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN BIT(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN BIT(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN BIT(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN BIT(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN BIT(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN BIT(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN BIT(24) - -/* RCC_MC_AHB6LPENCLRR register fields */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN BIT(0) -#define RCC_MC_AHB6LPENCLRR_GPULPEN BIT(5) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN BIT(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN BIT(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN BIT(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN BIT(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN BIT(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN BIT(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN BIT(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN BIT(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN BIT(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN BIT(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN BIT(24) - -/* RCC_BR_RSTSCLRR register fields */ -#define RCC_BR_RSTSCLRR_PORRSTF BIT(0) -#define RCC_BR_RSTSCLRR_BORRSTF BIT(1) -#define RCC_BR_RSTSCLRR_PADRSTF BIT(2) -#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) -#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) -#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) -#define RCC_BR_RSTSCLRR_MCSYSRSTF BIT(7) -#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) -#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) -#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) -#define RCC_BR_RSTSCLRR_MPUP1RSTF BIT(14) - -/* RCC_MP_GRSTCSETR register fields */ -#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) -#define RCC_MP_GRSTCSETR_MCURST BIT(1) -#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) -#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) - -/* RCC_MP_RSTSCLRR register fields */ -#define RCC_MP_RSTSCLRR_PORRSTF BIT(0) -#define RCC_MP_RSTSCLRR_BORRSTF BIT(1) -#define RCC_MP_RSTSCLRR_PADRSTF BIT(2) -#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) -#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) -#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) -#define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7) -#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) -#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) -#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) -#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) -#define RCC_MP_RSTSCLRR_MPUP1RSTF BIT(14) -#define RCC_MP_RSTSCLRR_SPARE BIT(15) - -/* RCC_MP_IWDGFZSETR register fields */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) - -/* RCC_MP_IWDGFZCLRR register fields */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) - -/* RCC_MP_CIER register fields */ -#define RCC_MP_CIER_LSIRDYIE BIT(0) -#define RCC_MP_CIER_LSERDYIE BIT(1) -#define RCC_MP_CIER_HSIRDYIE BIT(2) -#define RCC_MP_CIER_HSERDYIE BIT(3) -#define RCC_MP_CIER_CSIRDYIE BIT(4) -#define RCC_MP_CIER_PLL1DYIE BIT(8) -#define RCC_MP_CIER_PLL2DYIE BIT(9) -#define RCC_MP_CIER_PLL3DYIE BIT(10) -#define RCC_MP_CIER_PLL4DYIE BIT(11) -#define RCC_MP_CIER_LSECSSIE BIT(16) -#define RCC_MP_CIER_WKUPIE BIT(20) - -/* RCC_MP_CIFR register fields */ -#define RCC_MP_CIFR_MASK U(0x110F1F) -#define RCC_MP_CIFR_LSIRDYF BIT(0) -#define RCC_MP_CIFR_LSERDYF BIT(1) -#define RCC_MP_CIFR_HSIRDYF BIT(2) -#define RCC_MP_CIFR_HSERDYF BIT(3) -#define RCC_MP_CIFR_CSIRDYF BIT(4) -#define RCC_MP_CIFR_PLL1DYF BIT(8) -#define RCC_MP_CIFR_PLL2DYF BIT(9) -#define RCC_MP_CIFR_PLL3DYF BIT(10) -#define RCC_MP_CIFR_PLL4DYF BIT(11) -#define RCC_MP_CIFR_LSECSSF BIT(16) -#define RCC_MP_CIFR_WKUPF BIT(20) - -/* RCC_PWRLPDLYCR register fields */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) -#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 -#define RCC_PWRLPDLYCR_MCTMPSKP BIT(24) - -/* RCC_MP_RSTSSETR register fields */ -#define RCC_MP_RSTSSETR_PORRSTF BIT(0) -#define RCC_MP_RSTSSETR_BORRSTF BIT(1) -#define RCC_MP_RSTSSETR_PADRSTF BIT(2) -#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) -#define RCC_MP_RSTSSETR_VCORERSTF BIT(4) -#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) -#define RCC_MP_RSTSSETR_MCSYSRSTF BIT(7) -#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) -#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) -#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) -#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) -#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) -#define RCC_MP_RSTSSETR_MPUP1RSTF BIT(14) -#define RCC_MP_RSTSSETR_SPARE BIT(15) - -/* RCC_MCO1CFGR register fields */ -#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) -#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 -#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) -#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 -#define RCC_MCO1CFGR_MCO1ON BIT(12) - -/* RCC_MCO2CFGR register fields */ -#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) -#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 -#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) -#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 -#define RCC_MCO2CFGR_MCO2ON BIT(12) - -/* RCC_OCRDYR register fields */ -#define RCC_OCRDYR_HSIRDY BIT(0) -#define RCC_OCRDYR_HSIDIVRDY BIT(2) -#define RCC_OCRDYR_CSIRDY BIT(4) -#define RCC_OCRDYR_HSERDY BIT(8) -#define RCC_OCRDYR_MPUCKRDY BIT(23) -#define RCC_OCRDYR_AXICKRDY BIT(24) -#define RCC_OCRDYR_CKREST BIT(25) - -/* RCC_DBGCFGR register fields */ -#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) -#define RCC_DBGCFGR_TRACEDIV_SHIFT 0 -#define RCC_DBGCFGR_DBGCKEN BIT(8) -#define RCC_DBGCFGR_TRACECKEN BIT(9) -#define RCC_DBGCFGR_DBGRST BIT(12) - -/* RCC_RCK3SELR register fields */ -#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) -#define RCC_RCK3SELR_PLL3SRC_SHIFT 0 -#define RCC_RCK3SELR_PLL3SRCRDY BIT(31) - -/* RCC_RCK4SELR register fields */ -#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) -#define RCC_RCK4SELR_PLL4SRC_SHIFT 0 -#define RCC_RCK4SELR_PLL4SRCRDY BIT(31) - -/* RCC_TIMG1PRER register fields */ -#define RCC_TIMG1PRER_TIMG1PRE BIT(0) -#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) - -/* RCC_TIMG2PRER register fields */ -#define RCC_TIMG2PRER_TIMG2PRE BIT(0) -#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) - -/* RCC_MCUDIVR register fields */ -#define RCC_MCUDIVR_MCUDIV_MASK GENMASK(3, 0) -#define RCC_MCUDIVR_MCUDIV_SHIFT 0 -#define RCC_MCUDIVR_MCUDIVRDY BIT(31) - -/* RCC_APB1DIVR register fields */ -#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) -#define RCC_APB1DIVR_APB1DIV_SHIFT 0 -#define RCC_APB1DIVR_APB1DIVRDY BIT(31) - -/* RCC_APB2DIVR register fields */ -#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) -#define RCC_APB2DIVR_APB2DIV_SHIFT 0 -#define RCC_APB2DIVR_APB2DIVRDY BIT(31) - -/* RCC_APB3DIVR register fields */ -#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) -#define RCC_APB3DIVR_APB3DIV_SHIFT 0 -#define RCC_APB3DIVR_APB3DIVRDY BIT(31) - -/* RCC_PLL3CR register fields */ -#define RCC_PLL3CR_PLLON BIT(0) -#define RCC_PLL3CR_PLL3RDY BIT(1) -#define RCC_PLL3CR_SSCG_CTRL BIT(2) -#define RCC_PLL3CR_DIVPEN BIT(4) -#define RCC_PLL3CR_DIVQEN BIT(5) -#define RCC_PLL3CR_DIVREN BIT(6) - -/* RCC_PLL3CFGR1 register fields */ -#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) -#define RCC_PLL3CFGR1_DIVN_SHIFT 0 -#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) -#define RCC_PLL3CFGR1_DIVM3_SHIFT 16 -#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) -#define RCC_PLL3CFGR1_IFRGE_SHIFT 24 - -/* RCC_PLL3CFGR2 register fields */ -#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) -#define RCC_PLL3CFGR2_DIVP_SHIFT 0 -#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) -#define RCC_PLL3CFGR2_DIVQ_SHIFT 8 -#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) -#define RCC_PLL3CFGR2_DIVR_SHIFT 16 - -/* RCC_PLL3FRACR register fields */ -#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) -#define RCC_PLL3FRACR_FRACV_SHIFT 3 -#define RCC_PLL3FRACR_FRACLE BIT(16) - -/* RCC_PLL3CSGR register fields */ -#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) -#define RCC_PLL3CSGR_MOD_PER_SHIFT 0 -#define RCC_PLL3CSGR_TPDFN_DIS BIT(13) -#define RCC_PLL3CSGR_RPDFN_DIS BIT(14) -#define RCC_PLL3CSGR_SSCG_MODE BIT(15) -#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) -#define RCC_PLL3CSGR_INC_STEP_SHIFT 16 - -/* RCC_PLL4CR register fields */ -#define RCC_PLL4CR_PLLON BIT(0) -#define RCC_PLL4CR_PLL4RDY BIT(1) -#define RCC_PLL4CR_SSCG_CTRL BIT(2) -#define RCC_PLL4CR_DIVPEN BIT(4) -#define RCC_PLL4CR_DIVQEN BIT(5) -#define RCC_PLL4CR_DIVREN BIT(6) - -/* RCC_PLL4CFGR1 register fields */ -#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) -#define RCC_PLL4CFGR1_DIVN_SHIFT 0 -#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) -#define RCC_PLL4CFGR1_DIVM4_SHIFT 16 -#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) -#define RCC_PLL4CFGR1_IFRGE_SHIFT 24 - -/* RCC_PLL4CFGR2 register fields */ -#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) -#define RCC_PLL4CFGR2_DIVP_SHIFT 0 -#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) -#define RCC_PLL4CFGR2_DIVQ_SHIFT 8 -#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) -#define RCC_PLL4CFGR2_DIVR_SHIFT 16 - -/* RCC_PLL4FRACR register fields */ -#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) -#define RCC_PLL4FRACR_FRACV_SHIFT 3 -#define RCC_PLL4FRACR_FRACLE BIT(16) - -/* RCC_PLL4CSGR register fields */ -#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) -#define RCC_PLL4CSGR_MOD_PER_SHIFT 0 -#define RCC_PLL4CSGR_TPDFN_DIS BIT(13) -#define RCC_PLL4CSGR_RPDFN_DIS BIT(14) -#define RCC_PLL4CSGR_SSCG_MODE BIT(15) -#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) -#define RCC_PLL4CSGR_INC_STEP_SHIFT 16 - -/* RCC_I2C12CKSELR register fields */ -#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) -#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 - -/* RCC_I2C35CKSELR register fields */ -#define RCC_I2C35CKSELR_I2C35SRC_MASK GENMASK(2, 0) -#define RCC_I2C35CKSELR_I2C35SRC_SHIFT 0 - -/* RCC_SAI1CKSELR register fields */ -#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) -#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 - -/* RCC_SAI2CKSELR register fields */ -#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) -#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 - -/* RCC_SAI3CKSELR register fields */ -#define RCC_SAI3CKSELR_SAI3SRC_MASK GENMASK(2, 0) -#define RCC_SAI3CKSELR_SAI3SRC_SHIFT 0 - -/* RCC_SAI4CKSELR register fields */ -#define RCC_SAI4CKSELR_SAI4SRC_MASK GENMASK(2, 0) -#define RCC_SAI4CKSELR_SAI4SRC_SHIFT 0 - -/* RCC_SPI2S1CKSELR register fields */ -#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) -#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 - -/* RCC_SPI2S23CKSELR register fields */ -#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) -#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 - -/* RCC_SPI45CKSELR register fields */ -#define RCC_SPI45CKSELR_SPI45SRC_MASK GENMASK(2, 0) -#define RCC_SPI45CKSELR_SPI45SRC_SHIFT 0 - -/* RCC_UART6CKSELR register fields */ -#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) -#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 - -/* RCC_UART24CKSELR register fields */ -#define RCC_UART24CKSELR_HSI 0x00000002 -#define RCC_UART24CKSELR_UART24SRC_MASK GENMASK(2, 0) -#define RCC_UART24CKSELR_UART24SRC_SHIFT 0 - -/* RCC_UART35CKSELR register fields */ -#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) -#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 - -/* RCC_UART78CKSELR register fields */ -#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) -#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 - -/* RCC_SDMMC12CKSELR register fields */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_MASK GENMASK(2, 0) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_SHIFT 0 - -/* RCC_SDMMC3CKSELR register fields */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_MASK GENMASK(2, 0) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_SHIFT 0 - -/* RCC_ETHCKSELR register fields */ -#define RCC_ETHCKSELR_ETHSRC_MASK GENMASK(1, 0) -#define RCC_ETHCKSELR_ETHSRC_SHIFT 0 -#define RCC_ETHCKSELR_ETHPTPDIV_MASK GENMASK(7, 4) -#define RCC_ETHCKSELR_ETHPTPDIV_SHIFT 4 - -/* RCC_QSPICKSELR register fields */ -#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) -#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 - -/* RCC_FMCCKSELR register fields */ -#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) -#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 - -/* RCC_FDCANCKSELR register fields */ -#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) -#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 - -/* RCC_SPDIFCKSELR register fields */ -#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) -#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 - -/* RCC_CECCKSELR register fields */ -#define RCC_CECCKSELR_CECSRC_MASK GENMASK(1, 0) -#define RCC_CECCKSELR_CECSRC_SHIFT 0 - -/* RCC_USBCKSELR register fields */ -#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) -#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 -#define RCC_USBCKSELR_USBOSRC BIT(4) -#define RCC_USBCKSELR_USBOSRC_MASK BIT(4) -#define RCC_USBCKSELR_USBOSRC_SHIFT 4 - -/* RCC_RNG2CKSELR register fields */ -#define RCC_RNG2CKSELR_RNG2SRC_MASK GENMASK(1, 0) -#define RCC_RNG2CKSELR_RNG2SRC_SHIFT 0 - -/* RCC_DSICKSELR register fields */ -#define RCC_DSICKSELR_DSISRC BIT(0) - -/* RCC_ADCCKSELR register fields */ -#define RCC_ADCCKSELR_ADCSRC_MASK GENMASK(1, 0) -#define RCC_ADCCKSELR_ADCSRC_SHIFT 0 - -/* RCC_LPTIM45CKSELR register fields */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 - -/* RCC_LPTIM23CKSELR register fields */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_MASK GENMASK(2, 0) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_SHIFT 0 - -/* RCC_LPTIM1CKSELR register fields */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 - -/* RCC_APB1RSTSETR register fields */ -#define RCC_APB1RSTSETR_TIM2RST BIT(0) -#define RCC_APB1RSTSETR_TIM3RST BIT(1) -#define RCC_APB1RSTSETR_TIM4RST BIT(2) -#define RCC_APB1RSTSETR_TIM5RST BIT(3) -#define RCC_APB1RSTSETR_TIM6RST BIT(4) -#define RCC_APB1RSTSETR_TIM7RST BIT(5) -#define RCC_APB1RSTSETR_TIM12RST BIT(6) -#define RCC_APB1RSTSETR_TIM13RST BIT(7) -#define RCC_APB1RSTSETR_TIM14RST BIT(8) -#define RCC_APB1RSTSETR_LPTIM1RST BIT(9) -#define RCC_APB1RSTSETR_SPI2RST BIT(11) -#define RCC_APB1RSTSETR_SPI3RST BIT(12) -#define RCC_APB1RSTSETR_USART2RST BIT(14) -#define RCC_APB1RSTSETR_USART3RST BIT(15) -#define RCC_APB1RSTSETR_UART4RST BIT(16) -#define RCC_APB1RSTSETR_UART5RST BIT(17) -#define RCC_APB1RSTSETR_UART7RST BIT(18) -#define RCC_APB1RSTSETR_UART8RST BIT(19) -#define RCC_APB1RSTSETR_I2C1RST BIT(21) -#define RCC_APB1RSTSETR_I2C2RST BIT(22) -#define RCC_APB1RSTSETR_I2C3RST BIT(23) -#define RCC_APB1RSTSETR_I2C5RST BIT(24) -#define RCC_APB1RSTSETR_SPDIFRST BIT(26) -#define RCC_APB1RSTSETR_CECRST BIT(27) -#define RCC_APB1RSTSETR_DAC12RST BIT(29) -#define RCC_APB1RSTSETR_MDIOSRST BIT(31) - -/* RCC_APB1RSTCLRR register fields */ -#define RCC_APB1RSTCLRR_TIM2RST BIT(0) -#define RCC_APB1RSTCLRR_TIM3RST BIT(1) -#define RCC_APB1RSTCLRR_TIM4RST BIT(2) -#define RCC_APB1RSTCLRR_TIM5RST BIT(3) -#define RCC_APB1RSTCLRR_TIM6RST BIT(4) -#define RCC_APB1RSTCLRR_TIM7RST BIT(5) -#define RCC_APB1RSTCLRR_TIM12RST BIT(6) -#define RCC_APB1RSTCLRR_TIM13RST BIT(7) -#define RCC_APB1RSTCLRR_TIM14RST BIT(8) -#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) -#define RCC_APB1RSTCLRR_SPI2RST BIT(11) -#define RCC_APB1RSTCLRR_SPI3RST BIT(12) -#define RCC_APB1RSTCLRR_USART2RST BIT(14) -#define RCC_APB1RSTCLRR_USART3RST BIT(15) -#define RCC_APB1RSTCLRR_UART4RST BIT(16) -#define RCC_APB1RSTCLRR_UART5RST BIT(17) -#define RCC_APB1RSTCLRR_UART7RST BIT(18) -#define RCC_APB1RSTCLRR_UART8RST BIT(19) -#define RCC_APB1RSTCLRR_I2C1RST BIT(21) -#define RCC_APB1RSTCLRR_I2C2RST BIT(22) -#define RCC_APB1RSTCLRR_I2C3RST BIT(23) -#define RCC_APB1RSTCLRR_I2C5RST BIT(24) -#define RCC_APB1RSTCLRR_SPDIFRST BIT(26) -#define RCC_APB1RSTCLRR_CECRST BIT(27) -#define RCC_APB1RSTCLRR_DAC12RST BIT(29) -#define RCC_APB1RSTCLRR_MDIOSRST BIT(31) - -/* RCC_APB2RSTSETR register fields */ -#define RCC_APB2RSTSETR_TIM1RST BIT(0) -#define RCC_APB2RSTSETR_TIM8RST BIT(1) -#define RCC_APB2RSTSETR_TIM15RST BIT(2) -#define RCC_APB2RSTSETR_TIM16RST BIT(3) -#define RCC_APB2RSTSETR_TIM17RST BIT(4) -#define RCC_APB2RSTSETR_SPI1RST BIT(8) -#define RCC_APB2RSTSETR_SPI4RST BIT(9) -#define RCC_APB2RSTSETR_SPI5RST BIT(10) -#define RCC_APB2RSTSETR_USART6RST BIT(13) -#define RCC_APB2RSTSETR_SAI1RST BIT(16) -#define RCC_APB2RSTSETR_SAI2RST BIT(17) -#define RCC_APB2RSTSETR_SAI3RST BIT(18) -#define RCC_APB2RSTSETR_DFSDMRST BIT(20) -#define RCC_APB2RSTSETR_FDCANRST BIT(24) - -/* RCC_APB2RSTCLRR register fields */ -#define RCC_APB2RSTCLRR_TIM1RST BIT(0) -#define RCC_APB2RSTCLRR_TIM8RST BIT(1) -#define RCC_APB2RSTCLRR_TIM15RST BIT(2) -#define RCC_APB2RSTCLRR_TIM16RST BIT(3) -#define RCC_APB2RSTCLRR_TIM17RST BIT(4) -#define RCC_APB2RSTCLRR_SPI1RST BIT(8) -#define RCC_APB2RSTCLRR_SPI4RST BIT(9) -#define RCC_APB2RSTCLRR_SPI5RST BIT(10) -#define RCC_APB2RSTCLRR_USART6RST BIT(13) -#define RCC_APB2RSTCLRR_SAI1RST BIT(16) -#define RCC_APB2RSTCLRR_SAI2RST BIT(17) -#define RCC_APB2RSTCLRR_SAI3RST BIT(18) -#define RCC_APB2RSTCLRR_DFSDMRST BIT(20) -#define RCC_APB2RSTCLRR_FDCANRST BIT(24) - -/* RCC_APB3RSTSETR register fields */ -#define RCC_APB3RSTSETR_LPTIM2RST BIT(0) -#define RCC_APB3RSTSETR_LPTIM3RST BIT(1) -#define RCC_APB3RSTSETR_LPTIM4RST BIT(2) -#define RCC_APB3RSTSETR_LPTIM5RST BIT(3) -#define RCC_APB3RSTSETR_SAI4RST BIT(8) -#define RCC_APB3RSTSETR_SYSCFGRST BIT(11) -#define RCC_APB3RSTSETR_VREFRST BIT(13) -#define RCC_APB3RSTSETR_TMPSENSRST BIT(16) -#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) - -/* RCC_APB3RSTCLRR register fields */ -#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) -#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) -#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) -#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) -#define RCC_APB3RSTCLRR_SAI4RST BIT(8) -#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) -#define RCC_APB3RSTCLRR_VREFRST BIT(13) -#define RCC_APB3RSTCLRR_TMPSENSRST BIT(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) - -/* RCC_AHB2RSTSETR register fields */ -#define RCC_AHB2RSTSETR_DMA1RST BIT(0) -#define RCC_AHB2RSTSETR_DMA2RST BIT(1) -#define RCC_AHB2RSTSETR_DMAMUXRST BIT(2) -#define RCC_AHB2RSTSETR_ADC12RST BIT(5) -#define RCC_AHB2RSTSETR_USBORST BIT(8) -#define RCC_AHB2RSTSETR_SDMMC3RST BIT(16) - -/* RCC_AHB2RSTCLRR register fields */ -#define RCC_AHB2RSTCLRR_DMA1RST BIT(0) -#define RCC_AHB2RSTCLRR_DMA2RST BIT(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST BIT(2) -#define RCC_AHB2RSTCLRR_ADC12RST BIT(5) -#define RCC_AHB2RSTCLRR_USBORST BIT(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST BIT(16) - -/* RCC_AHB3RSTSETR register fields */ -#define RCC_AHB3RSTSETR_DCMIRST BIT(0) -#define RCC_AHB3RSTSETR_CRYP2RST BIT(4) -#define RCC_AHB3RSTSETR_HASH2RST BIT(5) -#define RCC_AHB3RSTSETR_RNG2RST BIT(6) -#define RCC_AHB3RSTSETR_CRC2RST BIT(7) -#define RCC_AHB3RSTSETR_HSEMRST BIT(11) -#define RCC_AHB3RSTSETR_IPCCRST BIT(12) - -/* RCC_AHB3RSTCLRR register fields */ -#define RCC_AHB3RSTCLRR_DCMIRST BIT(0) -#define RCC_AHB3RSTCLRR_CRYP2RST BIT(4) -#define RCC_AHB3RSTCLRR_HASH2RST BIT(5) -#define RCC_AHB3RSTCLRR_RNG2RST BIT(6) -#define RCC_AHB3RSTCLRR_CRC2RST BIT(7) -#define RCC_AHB3RSTCLRR_HSEMRST BIT(11) -#define RCC_AHB3RSTCLRR_IPCCRST BIT(12) - -/* RCC_AHB4RSTSETR register fields */ -#define RCC_AHB4RSTSETR_GPIOARST BIT(0) -#define RCC_AHB4RSTSETR_GPIOBRST BIT(1) -#define RCC_AHB4RSTSETR_GPIOCRST BIT(2) -#define RCC_AHB4RSTSETR_GPIODRST BIT(3) -#define RCC_AHB4RSTSETR_GPIOERST BIT(4) -#define RCC_AHB4RSTSETR_GPIOFRST BIT(5) -#define RCC_AHB4RSTSETR_GPIOGRST BIT(6) -#define RCC_AHB4RSTSETR_GPIOHRST BIT(7) -#define RCC_AHB4RSTSETR_GPIOIRST BIT(8) -#define RCC_AHB4RSTSETR_GPIOJRST BIT(9) -#define RCC_AHB4RSTSETR_GPIOKRST BIT(10) - -/* RCC_AHB4RSTCLRR register fields */ -#define RCC_AHB4RSTCLRR_GPIOARST BIT(0) -#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) -#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) -#define RCC_AHB4RSTCLRR_GPIODRST BIT(3) -#define RCC_AHB4RSTCLRR_GPIOERST BIT(4) -#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) -#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) -#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) -#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) -#define RCC_AHB4RSTCLRR_GPIOJRST BIT(9) -#define RCC_AHB4RSTCLRR_GPIOKRST BIT(10) - -/* RCC_MP_APB1ENSETR register fields */ -#define RCC_MP_APB1ENSETR_TIM2EN BIT(0) -#define RCC_MP_APB1ENSETR_TIM3EN BIT(1) -#define RCC_MP_APB1ENSETR_TIM4EN BIT(2) -#define RCC_MP_APB1ENSETR_TIM5EN BIT(3) -#define RCC_MP_APB1ENSETR_TIM6EN BIT(4) -#define RCC_MP_APB1ENSETR_TIM7EN BIT(5) -#define RCC_MP_APB1ENSETR_TIM12EN BIT(6) -#define RCC_MP_APB1ENSETR_TIM13EN BIT(7) -#define RCC_MP_APB1ENSETR_TIM14EN BIT(8) -#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) -#define RCC_MP_APB1ENSETR_SPI2EN BIT(11) -#define RCC_MP_APB1ENSETR_SPI3EN BIT(12) -#define RCC_MP_APB1ENSETR_USART2EN BIT(14) -#define RCC_MP_APB1ENSETR_USART3EN BIT(15) -#define RCC_MP_APB1ENSETR_UART4EN BIT(16) -#define RCC_MP_APB1ENSETR_UART5EN BIT(17) -#define RCC_MP_APB1ENSETR_UART7EN BIT(18) -#define RCC_MP_APB1ENSETR_UART8EN BIT(19) -#define RCC_MP_APB1ENSETR_I2C1EN BIT(21) -#define RCC_MP_APB1ENSETR_I2C2EN BIT(22) -#define RCC_MP_APB1ENSETR_I2C3EN BIT(23) -#define RCC_MP_APB1ENSETR_I2C5EN BIT(24) -#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) -#define RCC_MP_APB1ENSETR_CECEN BIT(27) -#define RCC_MP_APB1ENSETR_DAC12EN BIT(29) -#define RCC_MP_APB1ENSETR_MDIOSEN BIT(31) - -/* RCC_MP_APB1ENCLRR register fields */ -#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) -#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) -#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) -#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) -#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) -#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) -#define RCC_MP_APB1ENCLRR_TIM12EN BIT(6) -#define RCC_MP_APB1ENCLRR_TIM13EN BIT(7) -#define RCC_MP_APB1ENCLRR_TIM14EN BIT(8) -#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) -#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) -#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) -#define RCC_MP_APB1ENCLRR_USART2EN BIT(14) -#define RCC_MP_APB1ENCLRR_USART3EN BIT(15) -#define RCC_MP_APB1ENCLRR_UART4EN BIT(16) -#define RCC_MP_APB1ENCLRR_UART5EN BIT(17) -#define RCC_MP_APB1ENCLRR_UART7EN BIT(18) -#define RCC_MP_APB1ENCLRR_UART8EN BIT(19) -#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) -#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) -#define RCC_MP_APB1ENCLRR_I2C3EN BIT(23) -#define RCC_MP_APB1ENCLRR_I2C5EN BIT(24) -#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) -#define RCC_MP_APB1ENCLRR_CECEN BIT(27) -#define RCC_MP_APB1ENCLRR_DAC12EN BIT(29) -#define RCC_MP_APB1ENCLRR_MDIOSEN BIT(31) - -/* RCC_MP_APB2ENSETR register fields */ -#define RCC_MP_APB2ENSETR_TIM1EN BIT(0) -#define RCC_MP_APB2ENSETR_TIM8EN BIT(1) -#define RCC_MP_APB2ENSETR_TIM15EN BIT(2) -#define RCC_MP_APB2ENSETR_TIM16EN BIT(3) -#define RCC_MP_APB2ENSETR_TIM17EN BIT(4) -#define RCC_MP_APB2ENSETR_SPI1EN BIT(8) -#define RCC_MP_APB2ENSETR_SPI4EN BIT(9) -#define RCC_MP_APB2ENSETR_SPI5EN BIT(10) -#define RCC_MP_APB2ENSETR_USART6EN BIT(13) -#define RCC_MP_APB2ENSETR_SAI1EN BIT(16) -#define RCC_MP_APB2ENSETR_SAI2EN BIT(17) -#define RCC_MP_APB2ENSETR_SAI3EN BIT(18) -#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) -#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) -#define RCC_MP_APB2ENSETR_FDCANEN BIT(24) - -/* RCC_MP_APB2ENCLRR register fields */ -#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) -#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) -#define RCC_MP_APB2ENCLRR_TIM15EN BIT(2) -#define RCC_MP_APB2ENCLRR_TIM16EN BIT(3) -#define RCC_MP_APB2ENCLRR_TIM17EN BIT(4) -#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) -#define RCC_MP_APB2ENCLRR_SPI4EN BIT(9) -#define RCC_MP_APB2ENCLRR_SPI5EN BIT(10) -#define RCC_MP_APB2ENCLRR_USART6EN BIT(13) -#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) -#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) -#define RCC_MP_APB2ENCLRR_SAI3EN BIT(18) -#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) -#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) -#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) - -/* RCC_MP_APB3ENSETR register fields */ -#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) -#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) -#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) -#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) -#define RCC_MP_APB3ENSETR_SAI4EN BIT(8) -#define RCC_MP_APB3ENSETR_SYSCFGEN BIT(11) -#define RCC_MP_APB3ENSETR_VREFEN BIT(13) -#define RCC_MP_APB3ENSETR_TMPSENSEN BIT(16) -#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) -#define RCC_MP_APB3ENSETR_HDPEN BIT(20) - -/* RCC_MP_APB3ENCLRR register fields */ -#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) -#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) -#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) -#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) -#define RCC_MP_APB3ENCLRR_SAI4EN BIT(8) -#define RCC_MP_APB3ENCLRR_SYSCFGEN BIT(11) -#define RCC_MP_APB3ENCLRR_VREFEN BIT(13) -#define RCC_MP_APB3ENCLRR_TMPSENSEN BIT(16) -#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) -#define RCC_MP_APB3ENCLRR_HDPEN BIT(20) - -/* RCC_MP_AHB2ENSETR register fields */ -#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) -#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) -#define RCC_MP_AHB2ENSETR_DMAMUXEN BIT(2) -#define RCC_MP_AHB2ENSETR_ADC12EN BIT(5) -#define RCC_MP_AHB2ENSETR_USBOEN BIT(8) -#define RCC_MP_AHB2ENSETR_SDMMC3EN BIT(16) - -/* RCC_MP_AHB2ENCLRR register fields */ -#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) -#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) -#define RCC_MP_AHB2ENCLRR_DMAMUXEN BIT(2) -#define RCC_MP_AHB2ENCLRR_ADC12EN BIT(5) -#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) -#define RCC_MP_AHB2ENCLRR_SDMMC3EN BIT(16) - -/* RCC_MP_AHB3ENSETR register fields */ -#define RCC_MP_AHB3ENSETR_DCMIEN BIT(0) -#define RCC_MP_AHB3ENSETR_CRYP2EN BIT(4) -#define RCC_MP_AHB3ENSETR_HASH2EN BIT(5) -#define RCC_MP_AHB3ENSETR_RNG2EN BIT(6) -#define RCC_MP_AHB3ENSETR_CRC2EN BIT(7) -#define RCC_MP_AHB3ENSETR_HSEMEN BIT(11) -#define RCC_MP_AHB3ENSETR_IPCCEN BIT(12) - -/* RCC_MP_AHB3ENCLRR register fields */ -#define RCC_MP_AHB3ENCLRR_DCMIEN BIT(0) -#define RCC_MP_AHB3ENCLRR_CRYP2EN BIT(4) -#define RCC_MP_AHB3ENCLRR_HASH2EN BIT(5) -#define RCC_MP_AHB3ENCLRR_RNG2EN BIT(6) -#define RCC_MP_AHB3ENCLRR_CRC2EN BIT(7) -#define RCC_MP_AHB3ENCLRR_HSEMEN BIT(11) -#define RCC_MP_AHB3ENCLRR_IPCCEN BIT(12) - -/* RCC_MP_AHB4ENSETR register fields */ -#define RCC_MP_AHB4ENSETR_GPIOAEN BIT(0) -#define RCC_MP_AHB4ENSETR_GPIOBEN BIT(1) -#define RCC_MP_AHB4ENSETR_GPIOCEN BIT(2) -#define RCC_MP_AHB4ENSETR_GPIODEN BIT(3) -#define RCC_MP_AHB4ENSETR_GPIOEEN BIT(4) -#define RCC_MP_AHB4ENSETR_GPIOFEN BIT(5) -#define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6) -#define RCC_MP_AHB4ENSETR_GPIOHEN BIT(7) -#define RCC_MP_AHB4ENSETR_GPIOIEN BIT(8) -#define RCC_MP_AHB4ENSETR_GPIOJEN BIT(9) -#define RCC_MP_AHB4ENSETR_GPIOKEN BIT(10) - -/* RCC_MP_AHB4ENCLRR register fields */ -#define RCC_MP_AHB4ENCLRR_GPIOAEN BIT(0) -#define RCC_MP_AHB4ENCLRR_GPIOBEN BIT(1) -#define RCC_MP_AHB4ENCLRR_GPIOCEN BIT(2) -#define RCC_MP_AHB4ENCLRR_GPIODEN BIT(3) -#define RCC_MP_AHB4ENCLRR_GPIOEEN BIT(4) -#define RCC_MP_AHB4ENCLRR_GPIOFEN BIT(5) -#define RCC_MP_AHB4ENCLRR_GPIOGEN BIT(6) -#define RCC_MP_AHB4ENCLRR_GPIOHEN BIT(7) -#define RCC_MP_AHB4ENCLRR_GPIOIEN BIT(8) -#define RCC_MP_AHB4ENCLRR_GPIOJEN BIT(9) -#define RCC_MP_AHB4ENCLRR_GPIOKEN BIT(10) - -/* RCC_MP_MLAHBENSETR register fields */ -#define RCC_MP_MLAHBENSETR_RETRAMEN BIT(4) - -/* RCC_MP_MLAHBENCLRR register fields */ -#define RCC_MP_MLAHBENCLRR_RETRAMEN BIT(4) - -/* RCC_MC_APB1ENSETR register fields */ -#define RCC_MC_APB1ENSETR_TIM2EN BIT(0) -#define RCC_MC_APB1ENSETR_TIM3EN BIT(1) -#define RCC_MC_APB1ENSETR_TIM4EN BIT(2) -#define RCC_MC_APB1ENSETR_TIM5EN BIT(3) -#define RCC_MC_APB1ENSETR_TIM6EN BIT(4) -#define RCC_MC_APB1ENSETR_TIM7EN BIT(5) -#define RCC_MC_APB1ENSETR_TIM12EN BIT(6) -#define RCC_MC_APB1ENSETR_TIM13EN BIT(7) -#define RCC_MC_APB1ENSETR_TIM14EN BIT(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN BIT(9) -#define RCC_MC_APB1ENSETR_SPI2EN BIT(11) -#define RCC_MC_APB1ENSETR_SPI3EN BIT(12) -#define RCC_MC_APB1ENSETR_USART2EN BIT(14) -#define RCC_MC_APB1ENSETR_USART3EN BIT(15) -#define RCC_MC_APB1ENSETR_UART4EN BIT(16) -#define RCC_MC_APB1ENSETR_UART5EN BIT(17) -#define RCC_MC_APB1ENSETR_UART7EN BIT(18) -#define RCC_MC_APB1ENSETR_UART8EN BIT(19) -#define RCC_MC_APB1ENSETR_I2C1EN BIT(21) -#define RCC_MC_APB1ENSETR_I2C2EN BIT(22) -#define RCC_MC_APB1ENSETR_I2C3EN BIT(23) -#define RCC_MC_APB1ENSETR_I2C5EN BIT(24) -#define RCC_MC_APB1ENSETR_SPDIFEN BIT(26) -#define RCC_MC_APB1ENSETR_CECEN BIT(27) -#define RCC_MC_APB1ENSETR_WWDG1EN BIT(28) -#define RCC_MC_APB1ENSETR_DAC12EN BIT(29) -#define RCC_MC_APB1ENSETR_MDIOSEN BIT(31) - -/* RCC_MC_APB1ENCLRR register fields */ -#define RCC_MC_APB1ENCLRR_TIM2EN BIT(0) -#define RCC_MC_APB1ENCLRR_TIM3EN BIT(1) -#define RCC_MC_APB1ENCLRR_TIM4EN BIT(2) -#define RCC_MC_APB1ENCLRR_TIM5EN BIT(3) -#define RCC_MC_APB1ENCLRR_TIM6EN BIT(4) -#define RCC_MC_APB1ENCLRR_TIM7EN BIT(5) -#define RCC_MC_APB1ENCLRR_TIM12EN BIT(6) -#define RCC_MC_APB1ENCLRR_TIM13EN BIT(7) -#define RCC_MC_APB1ENCLRR_TIM14EN BIT(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN BIT(9) -#define RCC_MC_APB1ENCLRR_SPI2EN BIT(11) -#define RCC_MC_APB1ENCLRR_SPI3EN BIT(12) -#define RCC_MC_APB1ENCLRR_USART2EN BIT(14) -#define RCC_MC_APB1ENCLRR_USART3EN BIT(15) -#define RCC_MC_APB1ENCLRR_UART4EN BIT(16) -#define RCC_MC_APB1ENCLRR_UART5EN BIT(17) -#define RCC_MC_APB1ENCLRR_UART7EN BIT(18) -#define RCC_MC_APB1ENCLRR_UART8EN BIT(19) -#define RCC_MC_APB1ENCLRR_I2C1EN BIT(21) -#define RCC_MC_APB1ENCLRR_I2C2EN BIT(22) -#define RCC_MC_APB1ENCLRR_I2C3EN BIT(23) -#define RCC_MC_APB1ENCLRR_I2C5EN BIT(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN BIT(26) -#define RCC_MC_APB1ENCLRR_CECEN BIT(27) -#define RCC_MC_APB1ENCLRR_DAC12EN BIT(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN BIT(31) - -/* RCC_MC_APB2ENSETR register fields */ -#define RCC_MC_APB2ENSETR_TIM1EN BIT(0) -#define RCC_MC_APB2ENSETR_TIM8EN BIT(1) -#define RCC_MC_APB2ENSETR_TIM15EN BIT(2) -#define RCC_MC_APB2ENSETR_TIM16EN BIT(3) -#define RCC_MC_APB2ENSETR_TIM17EN BIT(4) -#define RCC_MC_APB2ENSETR_SPI1EN BIT(8) -#define RCC_MC_APB2ENSETR_SPI4EN BIT(9) -#define RCC_MC_APB2ENSETR_SPI5EN BIT(10) -#define RCC_MC_APB2ENSETR_USART6EN BIT(13) -#define RCC_MC_APB2ENSETR_SAI1EN BIT(16) -#define RCC_MC_APB2ENSETR_SAI2EN BIT(17) -#define RCC_MC_APB2ENSETR_SAI3EN BIT(18) -#define RCC_MC_APB2ENSETR_DFSDMEN BIT(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN BIT(21) -#define RCC_MC_APB2ENSETR_FDCANEN BIT(24) - -/* RCC_MC_APB2ENCLRR register fields */ -#define RCC_MC_APB2ENCLRR_TIM1EN BIT(0) -#define RCC_MC_APB2ENCLRR_TIM8EN BIT(1) -#define RCC_MC_APB2ENCLRR_TIM15EN BIT(2) -#define RCC_MC_APB2ENCLRR_TIM16EN BIT(3) -#define RCC_MC_APB2ENCLRR_TIM17EN BIT(4) -#define RCC_MC_APB2ENCLRR_SPI1EN BIT(8) -#define RCC_MC_APB2ENCLRR_SPI4EN BIT(9) -#define RCC_MC_APB2ENCLRR_SPI5EN BIT(10) -#define RCC_MC_APB2ENCLRR_USART6EN BIT(13) -#define RCC_MC_APB2ENCLRR_SAI1EN BIT(16) -#define RCC_MC_APB2ENCLRR_SAI2EN BIT(17) -#define RCC_MC_APB2ENCLRR_SAI3EN BIT(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN BIT(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN BIT(21) -#define RCC_MC_APB2ENCLRR_FDCANEN BIT(24) - -/* RCC_MC_APB3ENSETR register fields */ -#define RCC_MC_APB3ENSETR_LPTIM2EN BIT(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN BIT(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN BIT(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN BIT(3) -#define RCC_MC_APB3ENSETR_SAI4EN BIT(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN BIT(11) -#define RCC_MC_APB3ENSETR_VREFEN BIT(13) -#define RCC_MC_APB3ENSETR_TMPSENSEN BIT(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN BIT(17) -#define RCC_MC_APB3ENSETR_HDPEN BIT(20) - -/* RCC_MC_APB3ENCLRR register fields */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN BIT(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN BIT(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN BIT(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN BIT(3) -#define RCC_MC_APB3ENCLRR_SAI4EN BIT(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN BIT(11) -#define RCC_MC_APB3ENCLRR_VREFEN BIT(13) -#define RCC_MC_APB3ENCLRR_TMPSENSEN BIT(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN BIT(17) -#define RCC_MC_APB3ENCLRR_HDPEN BIT(20) - -/* RCC_MC_AHB2ENSETR register fields */ -#define RCC_MC_AHB2ENSETR_DMA1EN BIT(0) -#define RCC_MC_AHB2ENSETR_DMA2EN BIT(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN BIT(2) -#define RCC_MC_AHB2ENSETR_ADC12EN BIT(5) -#define RCC_MC_AHB2ENSETR_USBOEN BIT(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN BIT(16) - -/* RCC_MC_AHB2ENCLRR register fields */ -#define RCC_MC_AHB2ENCLRR_DMA1EN BIT(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN BIT(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN BIT(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN BIT(5) -#define RCC_MC_AHB2ENCLRR_USBOEN BIT(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN BIT(16) - -/* RCC_MC_AHB3ENSETR register fields */ -#define RCC_MC_AHB3ENSETR_DCMIEN BIT(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN BIT(4) -#define RCC_MC_AHB3ENSETR_HASH2EN BIT(5) -#define RCC_MC_AHB3ENSETR_RNG2EN BIT(6) -#define RCC_MC_AHB3ENSETR_CRC2EN BIT(7) -#define RCC_MC_AHB3ENSETR_HSEMEN BIT(11) -#define RCC_MC_AHB3ENSETR_IPCCEN BIT(12) - -/* RCC_MC_AHB3ENCLRR register fields */ -#define RCC_MC_AHB3ENCLRR_DCMIEN BIT(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN BIT(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN BIT(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN BIT(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN BIT(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN BIT(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN BIT(12) - -/* RCC_MC_AHB4ENSETR register fields */ -#define RCC_MC_AHB4ENSETR_GPIOAEN BIT(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN BIT(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN BIT(2) -#define RCC_MC_AHB4ENSETR_GPIODEN BIT(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN BIT(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN BIT(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN BIT(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN BIT(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN BIT(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN BIT(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN BIT(10) - -/* RCC_MC_AHB4ENCLRR register fields */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN BIT(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN BIT(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN BIT(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN BIT(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN BIT(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN BIT(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN BIT(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN BIT(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN BIT(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN BIT(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN BIT(10) - -/* RCC_MC_AXIMENSETR register fields */ -#define RCC_MC_AXIMENSETR_SYSRAMEN BIT(0) - -/* RCC_MC_AXIMENCLRR register fields */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN BIT(0) - -/* RCC_MC_MLAHBENSETR register fields */ -#define RCC_MC_MLAHBENSETR_RETRAMEN BIT(4) - -/* RCC_MC_MLAHBENCLRR register fields */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN BIT(4) - -/* RCC_MP_APB1LPENSETR register fields */ -#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) -#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) -#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) -#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) -#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) -#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) -#define RCC_MP_APB1LPENSETR_TIM12LPEN BIT(6) -#define RCC_MP_APB1LPENSETR_TIM13LPEN BIT(7) -#define RCC_MP_APB1LPENSETR_TIM14LPEN BIT(8) -#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) -#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) -#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) -#define RCC_MP_APB1LPENSETR_USART2LPEN BIT(14) -#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) -#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) -#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) -#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) -#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) -#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) -#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) -#define RCC_MP_APB1LPENSETR_I2C3LPEN BIT(23) -#define RCC_MP_APB1LPENSETR_I2C5LPEN BIT(24) -#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) -#define RCC_MP_APB1LPENSETR_CECLPEN BIT(27) -#define RCC_MP_APB1LPENSETR_DAC12LPEN BIT(29) -#define RCC_MP_APB1LPENSETR_MDIOSLPEN BIT(31) - -/* RCC_MP_APB1LPENCLRR register fields */ -#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) -#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) -#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) -#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) -#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) -#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) -#define RCC_MP_APB1LPENCLRR_TIM12LPEN BIT(6) -#define RCC_MP_APB1LPENCLRR_TIM13LPEN BIT(7) -#define RCC_MP_APB1LPENCLRR_TIM14LPEN BIT(8) -#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) -#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) -#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) -#define RCC_MP_APB1LPENCLRR_USART2LPEN BIT(14) -#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) -#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) -#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) -#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) -#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) -#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) -#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) -#define RCC_MP_APB1LPENCLRR_I2C3LPEN BIT(23) -#define RCC_MP_APB1LPENCLRR_I2C5LPEN BIT(24) -#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) -#define RCC_MP_APB1LPENCLRR_CECLPEN BIT(27) -#define RCC_MP_APB1LPENCLRR_DAC12LPEN BIT(29) -#define RCC_MP_APB1LPENCLRR_MDIOSLPEN BIT(31) - -/* RCC_MP_APB2LPENSETR register fields */ -#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) -#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) -#define RCC_MP_APB2LPENSETR_TIM15LPEN BIT(2) -#define RCC_MP_APB2LPENSETR_TIM16LPEN BIT(3) -#define RCC_MP_APB2LPENSETR_TIM17LPEN BIT(4) -#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) -#define RCC_MP_APB2LPENSETR_SPI4LPEN BIT(9) -#define RCC_MP_APB2LPENSETR_SPI5LPEN BIT(10) -#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) -#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) -#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) -#define RCC_MP_APB2LPENSETR_SAI3LPEN BIT(18) -#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) -#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) -#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) - -/* RCC_MP_APB2LPENCLRR register fields */ -#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) -#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) -#define RCC_MP_APB2LPENCLRR_TIM15LPEN BIT(2) -#define RCC_MP_APB2LPENCLRR_TIM16LPEN BIT(3) -#define RCC_MP_APB2LPENCLRR_TIM17LPEN BIT(4) -#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) -#define RCC_MP_APB2LPENCLRR_SPI4LPEN BIT(9) -#define RCC_MP_APB2LPENCLRR_SPI5LPEN BIT(10) -#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) -#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) -#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) -#define RCC_MP_APB2LPENCLRR_SAI3LPEN BIT(18) -#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) -#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) -#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) - -/* RCC_MP_APB3LPENSETR register fields */ -#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) -#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) -#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) -#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) -#define RCC_MP_APB3LPENSETR_SAI4LPEN BIT(8) -#define RCC_MP_APB3LPENSETR_SYSCFGLPEN BIT(11) -#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) -#define RCC_MP_APB3LPENSETR_TMPSENSLPEN BIT(16) -#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) - -/* RCC_MP_APB3LPENCLRR register fields */ -#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) -#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) -#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) -#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) -#define RCC_MP_APB3LPENCLRR_SAI4LPEN BIT(8) -#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN BIT(11) -#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) -#define RCC_MP_APB3LPENCLRR_TMPSENSLPEN BIT(16) -#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) - -/* RCC_MP_AHB2LPENSETR register fields */ -#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) -#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) -#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN BIT(2) -#define RCC_MP_AHB2LPENSETR_ADC12LPEN BIT(5) -#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) -#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN BIT(16) - -/* RCC_MP_AHB2LPENCLRR register fields */ -#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) -#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) -#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN BIT(2) -#define RCC_MP_AHB2LPENCLRR_ADC12LPEN BIT(5) -#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) -#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN BIT(16) - -/* RCC_MP_AHB3LPENSETR register fields */ -#define RCC_MP_AHB3LPENSETR_DCMILPEN BIT(0) -#define RCC_MP_AHB3LPENSETR_CRYP2LPEN BIT(4) -#define RCC_MP_AHB3LPENSETR_HASH2LPEN BIT(5) -#define RCC_MP_AHB3LPENSETR_RNG2LPEN BIT(6) -#define RCC_MP_AHB3LPENSETR_CRC2LPEN BIT(7) -#define RCC_MP_AHB3LPENSETR_HSEMLPEN BIT(11) -#define RCC_MP_AHB3LPENSETR_IPCCLPEN BIT(12) - -/* RCC_MP_AHB3LPENCLRR register fields */ -#define RCC_MP_AHB3LPENCLRR_DCMILPEN BIT(0) -#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN BIT(4) -#define RCC_MP_AHB3LPENCLRR_HASH2LPEN BIT(5) -#define RCC_MP_AHB3LPENCLRR_RNG2LPEN BIT(6) -#define RCC_MP_AHB3LPENCLRR_CRC2LPEN BIT(7) -#define RCC_MP_AHB3LPENCLRR_HSEMLPEN BIT(11) -#define RCC_MP_AHB3LPENCLRR_IPCCLPEN BIT(12) - -/* RCC_MP_AHB4LPENSETR register fields */ -#define RCC_MP_AHB4LPENSETR_GPIOALPEN BIT(0) -#define RCC_MP_AHB4LPENSETR_GPIOBLPEN BIT(1) -#define RCC_MP_AHB4LPENSETR_GPIOCLPEN BIT(2) -#define RCC_MP_AHB4LPENSETR_GPIODLPEN BIT(3) -#define RCC_MP_AHB4LPENSETR_GPIOELPEN BIT(4) -#define RCC_MP_AHB4LPENSETR_GPIOFLPEN BIT(5) -#define RCC_MP_AHB4LPENSETR_GPIOGLPEN BIT(6) -#define RCC_MP_AHB4LPENSETR_GPIOHLPEN BIT(7) -#define RCC_MP_AHB4LPENSETR_GPIOILPEN BIT(8) -#define RCC_MP_AHB4LPENSETR_GPIOJLPEN BIT(9) -#define RCC_MP_AHB4LPENSETR_GPIOKLPEN BIT(10) - -/* RCC_MP_AHB4LPENCLRR register fields */ -#define RCC_MP_AHB4LPENCLRR_GPIOALPEN BIT(0) -#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN BIT(1) -#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN BIT(2) -#define RCC_MP_AHB4LPENCLRR_GPIODLPEN BIT(3) -#define RCC_MP_AHB4LPENCLRR_GPIOELPEN BIT(4) -#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN BIT(5) -#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN BIT(6) -#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN BIT(7) -#define RCC_MP_AHB4LPENCLRR_GPIOILPEN BIT(8) -#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN BIT(9) -#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN BIT(10) - -/* RCC_MP_AXIMLPENSETR register fields */ -#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN BIT(0) - -/* RCC_MP_AXIMLPENCLRR register fields */ -#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN BIT(0) - -/* RCC_MP_MLAHBLPENSETR register fields */ -#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) -#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) -#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN BIT(2) -#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN BIT(4) - -/* RCC_MP_MLAHBLPENCLRR register fields */ -#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) -#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) -#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN BIT(2) -#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN BIT(4) - -/* RCC_MC_APB1LPENSETR register fields */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN BIT(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN BIT(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN BIT(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN BIT(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN BIT(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN BIT(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN BIT(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN BIT(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN BIT(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN BIT(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN BIT(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN BIT(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN BIT(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN BIT(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN BIT(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN BIT(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN BIT(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN BIT(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN BIT(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN BIT(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN BIT(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN BIT(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN BIT(26) -#define RCC_MC_APB1LPENSETR_CECLPEN BIT(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN BIT(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN BIT(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN BIT(31) - -/* RCC_MC_APB1LPENCLRR register fields */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN BIT(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN BIT(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN BIT(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN BIT(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN BIT(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN BIT(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN BIT(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN BIT(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN BIT(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN BIT(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN BIT(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN BIT(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN BIT(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN BIT(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN BIT(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN BIT(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN BIT(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN BIT(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN BIT(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN BIT(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN BIT(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN BIT(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN BIT(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN BIT(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN BIT(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN BIT(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN BIT(31) - -/* RCC_MC_APB2LPENSETR register fields */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN BIT(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN BIT(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN BIT(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN BIT(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN BIT(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN BIT(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN BIT(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN BIT(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN BIT(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN BIT(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN BIT(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN BIT(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN BIT(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN BIT(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN BIT(24) - -/* RCC_MC_APB2LPENCLRR register fields */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN BIT(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN BIT(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN BIT(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN BIT(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN BIT(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN BIT(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN BIT(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN BIT(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN BIT(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN BIT(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN BIT(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN BIT(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN BIT(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN BIT(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN BIT(24) - -/* RCC_MC_APB3LPENSETR register fields */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN BIT(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN BIT(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN BIT(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN BIT(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN BIT(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN BIT(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN BIT(13) -#define RCC_MC_APB3LPENSETR_TMPSENSLPEN BIT(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN BIT(17) - -/* RCC_MC_APB3LPENCLRR register fields */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN BIT(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN BIT(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN BIT(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN BIT(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN BIT(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN BIT(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN BIT(13) -#define RCC_MC_APB3LPENCLRR_TMPSENSLPEN BIT(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN BIT(17) - -/* RCC_MC_AHB2LPENSETR register fields */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN BIT(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN BIT(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN BIT(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN BIT(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN BIT(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN BIT(16) - -/* RCC_MC_AHB2LPENCLRR register fields */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN BIT(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN BIT(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN BIT(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN BIT(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN BIT(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN BIT(16) - -/* RCC_MC_AHB3LPENSETR register fields */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN BIT(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN BIT(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN BIT(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN BIT(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN BIT(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN BIT(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN BIT(12) - -/* RCC_MC_AHB3LPENCLRR register fields */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN BIT(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN BIT(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN BIT(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN BIT(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN BIT(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN BIT(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN BIT(12) - -/* RCC_MC_AHB4LPENSETR register fields */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN BIT(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN BIT(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN BIT(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN BIT(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN BIT(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN BIT(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN BIT(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN BIT(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN BIT(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN BIT(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN BIT(10) - -/* RCC_MC_AHB4LPENCLRR register fields */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN BIT(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN BIT(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN BIT(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN BIT(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN BIT(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN BIT(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN BIT(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN BIT(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN BIT(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN BIT(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN BIT(10) - -/* RCC_MC_AXIMLPENSETR register fields */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN BIT(0) - -/* RCC_MC_AXIMLPENCLRR register fields */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN BIT(0) - -/* RCC_MC_MLAHBLPENSETR register fields */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN BIT(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN BIT(1) -#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN BIT(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN BIT(4) - -/* RCC_MC_MLAHBLPENCLRR register fields */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN BIT(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN BIT(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN BIT(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN BIT(4) - -/* RCC_MC_RSTSCLRR register fields */ -#define RCC_MC_RSTSCLRR_PORRSTF BIT(0) -#define RCC_MC_RSTSCLRR_BORRSTF BIT(1) -#define RCC_MC_RSTSCLRR_PADRSTF BIT(2) -#define RCC_MC_RSTSCLRR_HCSSRSTF BIT(3) -#define RCC_MC_RSTSCLRR_VCORERSTF BIT(4) -#define RCC_MC_RSTSCLRR_MCURSTF BIT(5) -#define RCC_MC_RSTSCLRR_MPSYSRSTF BIT(6) -#define RCC_MC_RSTSCLRR_MCSYSRSTF BIT(7) -#define RCC_MC_RSTSCLRR_IWDG1RSTF BIT(8) -#define RCC_MC_RSTSCLRR_IWDG2RSTF BIT(9) -#define RCC_MC_RSTSCLRR_WWDG1RSTF BIT(10) - -/* RCC_MC_CIER register fields */ -#define RCC_MC_CIER_LSIRDYIE BIT(0) -#define RCC_MC_CIER_LSERDYIE BIT(1) -#define RCC_MC_CIER_HSIRDYIE BIT(2) -#define RCC_MC_CIER_HSERDYIE BIT(3) -#define RCC_MC_CIER_CSIRDYIE BIT(4) -#define RCC_MC_CIER_PLL1DYIE BIT(8) -#define RCC_MC_CIER_PLL2DYIE BIT(9) -#define RCC_MC_CIER_PLL3DYIE BIT(10) -#define RCC_MC_CIER_PLL4DYIE BIT(11) -#define RCC_MC_CIER_LSECSSIE BIT(16) -#define RCC_MC_CIER_WKUPIE BIT(20) - -/* RCC_MC_CIFR register fields */ -#define RCC_MC_CIFR_LSIRDYF BIT(0) -#define RCC_MC_CIFR_LSERDYF BIT(1) -#define RCC_MC_CIFR_HSIRDYF BIT(2) -#define RCC_MC_CIFR_HSERDYF BIT(3) -#define RCC_MC_CIFR_CSIRDYF BIT(4) -#define RCC_MC_CIFR_PLL1DYF BIT(8) -#define RCC_MC_CIFR_PLL2DYF BIT(9) -#define RCC_MC_CIFR_PLL3DYF BIT(10) -#define RCC_MC_CIFR_PLL4DYF BIT(11) -#define RCC_MC_CIFR_LSECSSF BIT(16) -#define RCC_MC_CIFR_WKUPF BIT(20) - -/* RCC_VERR register fields */ -#define RCC_VERR_MINREV_MASK GENMASK(3, 0) -#define RCC_VERR_MINREV_SHIFT 0 -#define RCC_VERR_MAJREV_MASK GENMASK(7, 4) -#define RCC_VERR_MAJREV_SHIFT 4 - -/* Used for RCC_OCENSETR and RCC_OCENCLRR registers */ -#define RCC_OCENR_HSION BIT(0) -#define RCC_OCENR_HSIKERON BIT(1) -#define RCC_OCENR_CSION BIT(4) -#define RCC_OCENR_CSIKERON BIT(5) -#define RCC_OCENR_DIGBYP BIT(7) -#define RCC_OCENR_HSEON BIT(8) -#define RCC_OCENR_HSEKERON BIT(9) -#define RCC_OCENR_HSEBYP BIT(10) -#define RCC_OCENR_HSECSSON BIT(11) - -/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ -#define RCC_MP_ENCLRR_OFFSET U(4) - -/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ -#define RCC_RSTCLRR_OFFSET U(4) - -/* Used for most of DIVR register: max div for RTC */ -#define RCC_DIVR_DIV_MASK GENMASK(5, 0) -#define RCC_DIVR_DIVRDY BIT(31) - -/* Masks for specific DIVR registers */ -#define RCC_APBXDIV_MASK GENMASK(2, 0) -#define RCC_MPUDIV_MASK GENMASK(2, 0) -#define RCC_AXIDIV_MASK GENMASK(2, 0) -#define RCC_MCUDIV_MASK GENMASK(3, 0) - -/* Used for most of RCC_SELR registers */ -#define RCC_SELR_SRC_MASK GENMASK(2, 0) -#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) -#define RCC_SELR_SRCRDY BIT(31) - -/* Used for all RCC_PLLCR registers */ -#define RCC_PLLNCR_PLLON BIT(0) -#define RCC_PLLNCR_PLLRDY BIT(1) -#define RCC_PLLNCR_SSCG_CTRL BIT(2) -#define RCC_PLLNCR_DIVPEN BIT(4) -#define RCC_PLLNCR_DIVQEN BIT(5) -#define RCC_PLLNCR_DIVREN BIT(6) -#define RCC_PLLNCR_DIVEN_SHIFT 4 - -/* Used for all RCC_PLLCFGR1 registers */ -#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) -#define RCC_PLLNCFGR1_DIVM_SHIFT 16 -#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) -#define RCC_PLLNCFGR1_DIVN_SHIFT 0 - -/* Only for PLL3 and PLL4 */ -#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) -#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 - -/* Used for all RCC_PLLCFGR2 registers */ -#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) -#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) -#define RCC_PLLNCFGR2_DIVP_SHIFT 0 -#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) -#define RCC_PLLNCFGR2_DIVQ_SHIFT 8 -#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) -#define RCC_PLLNCFGR2_DIVR_SHIFT 16 - -/* Used for all RCC_PLLFRACR registers */ -#define RCC_PLLNFRACR_FRACV_SHIFT 3 -#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) -#define RCC_PLLNFRACR_FRACLE BIT(16) - -/* Used for all RCC_PLLCSGR registers */ -#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 -#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) -#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 -#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) -#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 -#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) - -/* Used for TIMER Prescaler */ -#define RCC_TIMGXPRER_TIMGXPRE BIT(0) - -/* Used for RCC_MCO related operations */ -#define RCC_MCOCFG_MCOON BIT(12) -#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) -#define RCC_MCOCFG_MCODIV_SHIFT 4 -#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) - -#endif /* STM32MP1_RCC_H */ +#if STM32MP13 +#include "stm32mp13_rcc.h" +#endif +#if STM32MP15 +#include "stm32mp15_rcc.h" +#endif diff --git a/include/drivers/st/stm32mp_pmic.h b/include/drivers/st/stm32mp_pmic.h index 4dfb038d6..303c57148 100644 --- a/include/drivers/st/stm32mp_pmic.h +++ b/include/drivers/st/stm32mp_pmic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -48,4 +48,11 @@ static inline void print_pmic_info_and_debug(void) */ int pmic_ddr_power_init(enum ddr_type ddr_type); +/* + * pmic_voltages_init - Update voltages for platform init + * + * Returns 0 on success, and negative values on errors + */ +int pmic_voltages_init(void); + #endif /* STM32MP_PMIC_H */ diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 67e66b23f..0d25dedbb 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -1,278 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved * Author: Gabriel Fernandez for STMicroelectronics. */ -#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ -#define _DT_BINDINGS_STM32MP1_CLKS_H_ - -/* OSCILLATOR clocks */ -#define CK_HSE 0 -#define CK_CSI 1 -#define CK_LSI 2 -#define CK_LSE 3 -#define CK_HSI 4 -#define CK_HSE_DIV2 5 - -/* Bus clocks */ -#define TIM2 6 -#define TIM3 7 -#define TIM4 8 -#define TIM5 9 -#define TIM6 10 -#define TIM7 11 -#define TIM12 12 -#define TIM13 13 -#define TIM14 14 -#define LPTIM1 15 -#define SPI2 16 -#define SPI3 17 -#define USART2 18 -#define USART3 19 -#define UART4 20 -#define UART5 21 -#define UART7 22 -#define UART8 23 -#define I2C1 24 -#define I2C2 25 -#define I2C3 26 -#define I2C5 27 -#define SPDIF 28 -#define CEC 29 -#define DAC12 30 -#define MDIO 31 -#define TIM1 32 -#define TIM8 33 -#define TIM15 34 -#define TIM16 35 -#define TIM17 36 -#define SPI1 37 -#define SPI4 38 -#define SPI5 39 -#define USART6 40 -#define SAI1 41 -#define SAI2 42 -#define SAI3 43 -#define DFSDM 44 -#define FDCAN 45 -#define LPTIM2 46 -#define LPTIM3 47 -#define LPTIM4 48 -#define LPTIM5 49 -#define SAI4 50 -#define SYSCFG 51 -#define VREF 52 -#define TMPSENS 53 -#define PMBCTRL 54 -#define HDP 55 -#define LTDC 56 -#define DSI 57 -#define IWDG2 58 -#define USBPHY 59 -#define STGENRO 60 -#define SPI6 61 -#define I2C4 62 -#define I2C6 63 -#define USART1 64 -#define RTCAPB 65 -#define TZC1 66 -#define TZPC 67 -#define IWDG1 68 -#define BSEC 69 -#define STGEN 70 -#define DMA1 71 -#define DMA2 72 -#define DMAMUX 73 -#define ADC12 74 -#define USBO 75 -#define SDMMC3 76 -#define DCMI 77 -#define CRYP2 78 -#define HASH2 79 -#define RNG2 80 -#define CRC2 81 -#define HSEM 82 -#define IPCC 83 -#define GPIOA 84 -#define GPIOB 85 -#define GPIOC 86 -#define GPIOD 87 -#define GPIOE 88 -#define GPIOF 89 -#define GPIOG 90 -#define GPIOH 91 -#define GPIOI 92 -#define GPIOJ 93 -#define GPIOK 94 -#define GPIOZ 95 -#define CRYP1 96 -#define HASH1 97 -#define RNG1 98 -#define BKPSRAM 99 -#define MDMA 100 -#define GPU 101 -#define ETHCK 102 -#define ETHTX 103 -#define ETHRX 104 -#define ETHMAC 105 -#define FMC 106 -#define QSPI 107 -#define SDMMC1 108 -#define SDMMC2 109 -#define CRC1 110 -#define USBH 111 -#define ETHSTP 112 -#define TZC2 113 - -/* Kernel clocks */ -#define SDMMC1_K 118 -#define SDMMC2_K 119 -#define SDMMC3_K 120 -#define FMC_K 121 -#define QSPI_K 122 -#define ETHCK_K 123 -#define RNG1_K 124 -#define RNG2_K 125 -#define GPU_K 126 -#define USBPHY_K 127 -#define STGEN_K 128 -#define SPDIF_K 129 -#define SPI1_K 130 -#define SPI2_K 131 -#define SPI3_K 132 -#define SPI4_K 133 -#define SPI5_K 134 -#define SPI6_K 135 -#define CEC_K 136 -#define I2C1_K 137 -#define I2C2_K 138 -#define I2C3_K 139 -#define I2C4_K 140 -#define I2C5_K 141 -#define I2C6_K 142 -#define LPTIM1_K 143 -#define LPTIM2_K 144 -#define LPTIM3_K 145 -#define LPTIM4_K 146 -#define LPTIM5_K 147 -#define USART1_K 148 -#define USART2_K 149 -#define USART3_K 150 -#define UART4_K 151 -#define UART5_K 152 -#define USART6_K 153 -#define UART7_K 154 -#define UART8_K 155 -#define DFSDM_K 156 -#define FDCAN_K 157 -#define SAI1_K 158 -#define SAI2_K 159 -#define SAI3_K 160 -#define SAI4_K 161 -#define ADC12_K 162 -#define DSI_K 163 -#define DSI_PX 164 -#define ADFSDM_K 165 -#define USBO_K 166 -#define LTDC_PX 167 -#define DAC12_K 168 -#define ETHPTP_K 169 - -/* PLL */ -#define PLL1 176 -#define PLL2 177 -#define PLL3 178 -#define PLL4 179 - -/* ODF */ -#define PLL1_P 180 -#define PLL1_Q 181 -#define PLL1_R 182 -#define PLL2_P 183 -#define PLL2_Q 184 -#define PLL2_R 185 -#define PLL3_P 186 -#define PLL3_Q 187 -#define PLL3_R 188 -#define PLL4_P 189 -#define PLL4_Q 190 -#define PLL4_R 191 - -/* AUX */ -#define RTC 192 - -/* MCLK */ -#define CK_PER 193 -#define CK_MPU 194 -#define CK_AXI 195 -#define CK_MCU 196 - -/* Time base */ -#define TIM2_K 197 -#define TIM3_K 198 -#define TIM4_K 199 -#define TIM5_K 200 -#define TIM6_K 201 -#define TIM7_K 202 -#define TIM12_K 203 -#define TIM13_K 204 -#define TIM14_K 205 -#define TIM1_K 206 -#define TIM8_K 207 -#define TIM15_K 208 -#define TIM16_K 209 -#define TIM17_K 210 - -/* MCO clocks */ -#define CK_MCO1 211 -#define CK_MCO2 212 - -/* TRACE & DEBUG clocks */ -#define CK_DBG 214 -#define CK_TRACE 215 - -/* DDR */ -#define DDRC1 220 -#define DDRC1LP 221 -#define DDRC2 222 -#define DDRC2LP 223 -#define DDRPHYC 224 -#define DDRPHYCLP 225 -#define DDRCAPB 226 -#define DDRCAPBLP 227 -#define AXIDCG 228 -#define DDRPHYCAPB 229 -#define DDRPHYCAPBLP 230 -#define DDRPERFM 231 - -#define STM32MP1_LAST_CLK 232 - -/* SCMI clock identifiers */ -#define CK_SCMI0_HSE 0 -#define CK_SCMI0_HSI 1 -#define CK_SCMI0_CSI 2 -#define CK_SCMI0_LSE 3 -#define CK_SCMI0_LSI 4 -#define CK_SCMI0_PLL2_Q 5 -#define CK_SCMI0_PLL2_R 6 -#define CK_SCMI0_MPU 7 -#define CK_SCMI0_AXI 8 -#define CK_SCMI0_BSEC 9 -#define CK_SCMI0_CRYP1 10 -#define CK_SCMI0_GPIOZ 11 -#define CK_SCMI0_HASH1 12 -#define CK_SCMI0_I2C4 13 -#define CK_SCMI0_I2C6 14 -#define CK_SCMI0_IWDG1 15 -#define CK_SCMI0_RNG1 16 -#define CK_SCMI0_RTC 17 -#define CK_SCMI0_RTCAPB 18 -#define CK_SCMI0_SPI6 19 -#define CK_SCMI0_USART1 20 - -#define CK_SCMI1_PLL3_Q 0 -#define CK_SCMI1_PLL3_R 1 -#define CK_SCMI1_MCU 2 - -#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ +#if STM32MP13 +#include "stm32mp13-clks.h" +#endif +#if STM32MP15 +#include "stm32mp15-clks.h" +#endif diff --git a/include/dt-bindings/clock/stm32mp1-clksrc.h b/include/dt-bindings/clock/stm32mp1-clksrc.h index 818f4b768..d02ddcd9a 100644 --- a/include/dt-bindings/clock/stm32mp1-clksrc.h +++ b/include/dt-bindings/clock/stm32mp1-clksrc.h @@ -1,283 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ /* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved */ -#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ -#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ - -/* PLL output is enable when x=1, with x=p,q or r */ -#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) - -/* st,clksrc: mandatory clock source */ - -#define CLK_MPU_HSI 0x00000200 -#define CLK_MPU_HSE 0x00000201 -#define CLK_MPU_PLL1P 0x00000202 -#define CLK_MPU_PLL1P_DIV 0x00000203 - -#define CLK_AXI_HSI 0x00000240 -#define CLK_AXI_HSE 0x00000241 -#define CLK_AXI_PLL2P 0x00000242 - -#define CLK_MCU_HSI 0x00000480 -#define CLK_MCU_HSE 0x00000481 -#define CLK_MCU_CSI 0x00000482 -#define CLK_MCU_PLL3P 0x00000483 - -#define CLK_PLL12_HSI 0x00000280 -#define CLK_PLL12_HSE 0x00000281 - -#define CLK_PLL3_HSI 0x00008200 -#define CLK_PLL3_HSE 0x00008201 -#define CLK_PLL3_CSI 0x00008202 - -#define CLK_PLL4_HSI 0x00008240 -#define CLK_PLL4_HSE 0x00008241 -#define CLK_PLL4_CSI 0x00008242 -#define CLK_PLL4_I2SCKIN 0x00008243 - -#define CLK_RTC_DISABLED 0x00001400 -#define CLK_RTC_LSE 0x00001401 -#define CLK_RTC_LSI 0x00001402 -#define CLK_RTC_HSE 0x00001403 - -#define CLK_MCO1_HSI 0x00008000 -#define CLK_MCO1_HSE 0x00008001 -#define CLK_MCO1_CSI 0x00008002 -#define CLK_MCO1_LSI 0x00008003 -#define CLK_MCO1_LSE 0x00008004 -#define CLK_MCO1_DISABLED 0x0000800F - -#define CLK_MCO2_MPU 0x00008040 -#define CLK_MCO2_AXI 0x00008041 -#define CLK_MCO2_MCU 0x00008042 -#define CLK_MCO2_PLL4P 0x00008043 -#define CLK_MCO2_HSE 0x00008044 -#define CLK_MCO2_HSI 0x00008045 -#define CLK_MCO2_DISABLED 0x0000804F - -/* st,pkcs: peripheral kernel clock source */ - -#define CLK_I2C12_PCLK1 0x00008C00 -#define CLK_I2C12_PLL4R 0x00008C01 -#define CLK_I2C12_HSI 0x00008C02 -#define CLK_I2C12_CSI 0x00008C03 -#define CLK_I2C12_DISABLED 0x00008C07 - -#define CLK_I2C35_PCLK1 0x00008C40 -#define CLK_I2C35_PLL4R 0x00008C41 -#define CLK_I2C35_HSI 0x00008C42 -#define CLK_I2C35_CSI 0x00008C43 -#define CLK_I2C35_DISABLED 0x00008C47 - -#define CLK_I2C46_PCLK5 0x00000C00 -#define CLK_I2C46_PLL3Q 0x00000C01 -#define CLK_I2C46_HSI 0x00000C02 -#define CLK_I2C46_CSI 0x00000C03 -#define CLK_I2C46_DISABLED 0x00000C07 - -#define CLK_SAI1_PLL4Q 0x00008C80 -#define CLK_SAI1_PLL3Q 0x00008C81 -#define CLK_SAI1_I2SCKIN 0x00008C82 -#define CLK_SAI1_CKPER 0x00008C83 -#define CLK_SAI1_PLL3R 0x00008C84 -#define CLK_SAI1_DISABLED 0x00008C87 - -#define CLK_SAI2_PLL4Q 0x00008CC0 -#define CLK_SAI2_PLL3Q 0x00008CC1 -#define CLK_SAI2_I2SCKIN 0x00008CC2 -#define CLK_SAI2_CKPER 0x00008CC3 -#define CLK_SAI2_SPDIF 0x00008CC4 -#define CLK_SAI2_PLL3R 0x00008CC5 -#define CLK_SAI2_DISABLED 0x00008CC7 - -#define CLK_SAI3_PLL4Q 0x00008D00 -#define CLK_SAI3_PLL3Q 0x00008D01 -#define CLK_SAI3_I2SCKIN 0x00008D02 -#define CLK_SAI3_CKPER 0x00008D03 -#define CLK_SAI3_PLL3R 0x00008D04 -#define CLK_SAI3_DISABLED 0x00008D07 - -#define CLK_SAI4_PLL4Q 0x00008D40 -#define CLK_SAI4_PLL3Q 0x00008D41 -#define CLK_SAI4_I2SCKIN 0x00008D42 -#define CLK_SAI4_CKPER 0x00008D43 -#define CLK_SAI4_PLL3R 0x00008D44 -#define CLK_SAI4_DISABLED 0x00008D47 - -#define CLK_SPI2S1_PLL4P 0x00008D80 -#define CLK_SPI2S1_PLL3Q 0x00008D81 -#define CLK_SPI2S1_I2SCKIN 0x00008D82 -#define CLK_SPI2S1_CKPER 0x00008D83 -#define CLK_SPI2S1_PLL3R 0x00008D84 -#define CLK_SPI2S1_DISABLED 0x00008D87 - -#define CLK_SPI2S23_PLL4P 0x00008DC0 -#define CLK_SPI2S23_PLL3Q 0x00008DC1 -#define CLK_SPI2S23_I2SCKIN 0x00008DC2 -#define CLK_SPI2S23_CKPER 0x00008DC3 -#define CLK_SPI2S23_PLL3R 0x00008DC4 -#define CLK_SPI2S23_DISABLED 0x00008DC7 - -#define CLK_SPI45_PCLK2 0x00008E00 -#define CLK_SPI45_PLL4Q 0x00008E01 -#define CLK_SPI45_HSI 0x00008E02 -#define CLK_SPI45_CSI 0x00008E03 -#define CLK_SPI45_HSE 0x00008E04 -#define CLK_SPI45_DISABLED 0x00008E07 - -#define CLK_SPI6_PCLK5 0x00000C40 -#define CLK_SPI6_PLL4Q 0x00000C41 -#define CLK_SPI6_HSI 0x00000C42 -#define CLK_SPI6_CSI 0x00000C43 -#define CLK_SPI6_HSE 0x00000C44 -#define CLK_SPI6_PLL3Q 0x00000C45 -#define CLK_SPI6_DISABLED 0x00000C47 - -#define CLK_UART6_PCLK2 0x00008E40 -#define CLK_UART6_PLL4Q 0x00008E41 -#define CLK_UART6_HSI 0x00008E42 -#define CLK_UART6_CSI 0x00008E43 -#define CLK_UART6_HSE 0x00008E44 -#define CLK_UART6_DISABLED 0x00008E47 - -#define CLK_UART24_PCLK1 0x00008E80 -#define CLK_UART24_PLL4Q 0x00008E81 -#define CLK_UART24_HSI 0x00008E82 -#define CLK_UART24_CSI 0x00008E83 -#define CLK_UART24_HSE 0x00008E84 -#define CLK_UART24_DISABLED 0x00008E87 - -#define CLK_UART35_PCLK1 0x00008EC0 -#define CLK_UART35_PLL4Q 0x00008EC1 -#define CLK_UART35_HSI 0x00008EC2 -#define CLK_UART35_CSI 0x00008EC3 -#define CLK_UART35_HSE 0x00008EC4 -#define CLK_UART35_DISABLED 0x00008EC7 - -#define CLK_UART78_PCLK1 0x00008F00 -#define CLK_UART78_PLL4Q 0x00008F01 -#define CLK_UART78_HSI 0x00008F02 -#define CLK_UART78_CSI 0x00008F03 -#define CLK_UART78_HSE 0x00008F04 -#define CLK_UART78_DISABLED 0x00008F07 - -#define CLK_UART1_PCLK5 0x00000C80 -#define CLK_UART1_PLL3Q 0x00000C81 -#define CLK_UART1_HSI 0x00000C82 -#define CLK_UART1_CSI 0x00000C83 -#define CLK_UART1_PLL4Q 0x00000C84 -#define CLK_UART1_HSE 0x00000C85 -#define CLK_UART1_DISABLED 0x00000C87 - -#define CLK_SDMMC12_HCLK6 0x00008F40 -#define CLK_SDMMC12_PLL3R 0x00008F41 -#define CLK_SDMMC12_PLL4P 0x00008F42 -#define CLK_SDMMC12_HSI 0x00008F43 -#define CLK_SDMMC12_DISABLED 0x00008F47 - -#define CLK_SDMMC3_HCLK2 0x00008F80 -#define CLK_SDMMC3_PLL3R 0x00008F81 -#define CLK_SDMMC3_PLL4P 0x00008F82 -#define CLK_SDMMC3_HSI 0x00008F83 -#define CLK_SDMMC3_DISABLED 0x00008F87 - -#define CLK_ETH_PLL4P 0x00008FC0 -#define CLK_ETH_PLL3Q 0x00008FC1 -#define CLK_ETH_DISABLED 0x00008FC3 - -#define CLK_QSPI_ACLK 0x00009000 -#define CLK_QSPI_PLL3R 0x00009001 -#define CLK_QSPI_PLL4P 0x00009002 -#define CLK_QSPI_CKPER 0x00009003 - -#define CLK_FMC_ACLK 0x00009040 -#define CLK_FMC_PLL3R 0x00009041 -#define CLK_FMC_PLL4P 0x00009042 -#define CLK_FMC_CKPER 0x00009043 - -#define CLK_FDCAN_HSE 0x000090C0 -#define CLK_FDCAN_PLL3Q 0x000090C1 -#define CLK_FDCAN_PLL4Q 0x000090C2 -#define CLK_FDCAN_PLL4R 0x000090C3 - -#define CLK_SPDIF_PLL4P 0x00009140 -#define CLK_SPDIF_PLL3Q 0x00009141 -#define CLK_SPDIF_HSI 0x00009142 -#define CLK_SPDIF_DISABLED 0x00009143 - -#define CLK_CEC_LSE 0x00009180 -#define CLK_CEC_LSI 0x00009181 -#define CLK_CEC_CSI_DIV122 0x00009182 -#define CLK_CEC_DISABLED 0x00009183 - -#define CLK_USBPHY_HSE 0x000091C0 -#define CLK_USBPHY_PLL4R 0x000091C1 -#define CLK_USBPHY_HSE_DIV2 0x000091C2 -#define CLK_USBPHY_DISABLED 0x000091C3 - -#define CLK_USBO_PLL4R 0x800091C0 -#define CLK_USBO_USBPHY 0x800091C1 - -#define CLK_RNG1_CSI 0x00000CC0 -#define CLK_RNG1_PLL4R 0x00000CC1 -#define CLK_RNG1_LSE 0x00000CC2 -#define CLK_RNG1_LSI 0x00000CC3 - -#define CLK_RNG2_CSI 0x00009200 -#define CLK_RNG2_PLL4R 0x00009201 -#define CLK_RNG2_LSE 0x00009202 -#define CLK_RNG2_LSI 0x00009203 - -#define CLK_CKPER_HSI 0x00000D00 -#define CLK_CKPER_CSI 0x00000D01 -#define CLK_CKPER_HSE 0x00000D02 -#define CLK_CKPER_DISABLED 0x00000D03 - -#define CLK_STGEN_HSI 0x00000D40 -#define CLK_STGEN_HSE 0x00000D41 -#define CLK_STGEN_DISABLED 0x00000D43 - -#define CLK_DSI_DSIPLL 0x00009240 -#define CLK_DSI_PLL4P 0x00009241 - -#define CLK_ADC_PLL4R 0x00009280 -#define CLK_ADC_CKPER 0x00009281 -#define CLK_ADC_PLL3Q 0x00009282 -#define CLK_ADC_DISABLED 0x00009283 - -#define CLK_LPTIM45_PCLK3 0x000092C0 -#define CLK_LPTIM45_PLL4P 0x000092C1 -#define CLK_LPTIM45_PLL3Q 0x000092C2 -#define CLK_LPTIM45_LSE 0x000092C3 -#define CLK_LPTIM45_LSI 0x000092C4 -#define CLK_LPTIM45_CKPER 0x000092C5 -#define CLK_LPTIM45_DISABLED 0x000092C7 - -#define CLK_LPTIM23_PCLK3 0x00009300 -#define CLK_LPTIM23_PLL4Q 0x00009301 -#define CLK_LPTIM23_CKPER 0x00009302 -#define CLK_LPTIM23_LSE 0x00009303 -#define CLK_LPTIM23_LSI 0x00009304 -#define CLK_LPTIM23_DISABLED 0x00009307 - -#define CLK_LPTIM1_PCLK1 0x00009340 -#define CLK_LPTIM1_PLL4P 0x00009341 -#define CLK_LPTIM1_PLL3Q 0x00009342 -#define CLK_LPTIM1_LSE 0x00009343 -#define CLK_LPTIM1_LSI 0x00009344 -#define CLK_LPTIM1_CKPER 0x00009345 -#define CLK_LPTIM1_DISABLED 0x00009347 - -/* define for st,pll /csg */ -#define SSCG_MODE_CENTER_SPREAD 0 -#define SSCG_MODE_DOWN_SPREAD 1 - -/* define for st,drive */ -#define LSEDRV_LOWEST 0 -#define LSEDRV_MEDIUM_LOW 1 -#define LSEDRV_MEDIUM_HIGH 2 -#define LSEDRV_HIGHEST 3 - +#if STM32MP13 +#include "stm32mp13-clksrc.h" +#endif +#if STM32MP15 +#include "stm32mp15-clksrc.h" #endif diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h new file mode 100644 index 000000000..1d5bb7838 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp13-clks.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ +#define _DT_BINDINGS_STM32MP13_CLKS_H_ + +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* PLL */ +#define PLL1 6 +#define PLL2 7 +#define PLL3 8 +#define PLL4 9 + +/* ODF */ +#define PLL1_P 10 +#define PLL1_Q 11 +#define PLL1_R 12 +#define PLL2_P 13 +#define PLL2_Q 14 +#define PLL2_R 15 +#define PLL3_P 16 +#define PLL3_Q 17 +#define PLL3_R 18 +#define PLL4_P 19 +#define PLL4_Q 20 +#define PLL4_R 21 + +#define PCLK1 22 +#define PCLK2 23 +#define PCLK3 24 +#define PCLK4 25 +#define PCLK5 26 +#define PCLK6 27 + +/* SYSTEM CLOCK */ +#define CK_PER 28 +#define CK_MPU 29 +#define CK_AXI 30 +#define CK_MLAHB 31 + +/* BASE TIMER */ +#define CK_TIMG1 32 +#define CK_TIMG2 33 +#define CK_TIMG3 34 + +/* AUX */ +#define RTC 35 + +/* TRACE & DEBUG clocks */ +#define CK_DBG 36 +#define CK_TRACE 37 + +/* MCO clocks */ +#define CK_MCO1 38 +#define CK_MCO2 39 + +/* IP clocks */ +#define SYSCFG 40 +#define VREF 41 +#define TMPSENS 42 +#define PMBCTRL 43 +#define HDP 44 +#define IWDG2 45 +#define STGENRO 46 +#define USART1 47 +#define RTCAPB 48 +#define TZC 49 +#define TZPC 50 +#define IWDG1 51 +#define BSEC 52 +#define DMA1 53 +#define DMA2 54 +#define DMAMUX1 55 +#define DMAMUX2 56 +#define GPIOA 57 +#define GPIOB 58 +#define GPIOC 59 +#define GPIOD 60 +#define GPIOE 61 +#define GPIOF 62 +#define GPIOG 63 +#define GPIOH 64 +#define GPIOI 65 +#define CRYP1 66 +#define HASH1 67 +#define BKPSRAM 68 +#define MDMA 69 +#define CRC1 70 +#define USBH 71 +#define DMA3 72 +#define TSC 73 +#define PKA 74 +#define AXIMC 75 +#define MCE 76 +#define ETH1TX 77 +#define ETH2TX 78 +#define ETH1RX 79 +#define ETH2RX 80 +#define ETH1MAC 81 +#define ETH2MAC 82 +#define ETH1STP 83 +#define ETH2STP 84 + +/* IP clocks with parents */ +#define SDMMC1_K 85 +#define SDMMC2_K 86 +#define ADC1_K 87 +#define ADC2_K 88 +#define FMC_K 89 +#define QSPI_K 90 +#define RNG1_K 91 +#define USBPHY_K 92 +#define STGEN_K 93 +#define SPDIF_K 94 +#define SPI1_K 95 +#define SPI2_K 96 +#define SPI3_K 97 +#define SPI4_K 98 +#define SPI5_K 99 +#define I2C1_K 100 +#define I2C2_K 101 +#define I2C3_K 102 +#define I2C4_K 103 +#define I2C5_K 104 +#define TIM2_K 105 +#define TIM3_K 106 +#define TIM4_K 107 +#define TIM5_K 108 +#define TIM6_K 109 +#define TIM7_K 110 +#define TIM12_K 111 +#define TIM13_K 112 +#define TIM14_K 113 +#define TIM1_K 114 +#define TIM8_K 115 +#define TIM15_K 116 +#define TIM16_K 117 +#define TIM17_K 118 +#define LPTIM1_K 119 +#define LPTIM2_K 120 +#define LPTIM3_K 121 +#define LPTIM4_K 122 +#define LPTIM5_K 123 +#define USART1_K 124 +#define USART2_K 125 +#define USART3_K 126 +#define UART4_K 127 +#define UART5_K 128 +#define USART6_K 129 +#define UART7_K 130 +#define UART8_K 131 +#define DFSDM_K 132 +#define FDCAN_K 133 +#define SAI1_K 134 +#define SAI2_K 135 +#define ADFSDM_K 136 +#define USBO_K 137 +#define LTDC_PX 138 +#define ETH1CK_K 139 +#define ETH1PTP_K 140 +#define ETH2CK_K 141 +#define ETH2PTP_K 142 +#define DCMIPP_K 143 +#define SAES_K 144 +#define DTS_K 145 + +/* DDR */ +#define DDRC1 146 +#define DDRC1LP 147 +#define DDRC2 148 +#define DDRC2LP 149 +#define DDRPHYC 150 +#define DDRPHYCLP 151 +#define DDRCAPB 152 +#define DDRCAPBLP 153 +#define AXIDCG 154 +#define DDRPHYCAPB 155 +#define DDRPHYCAPBLP 156 +#define DDRPERFM 157 + +#define ADC1 158 +#define ADC2 159 +#define SAI1 160 +#define SAI2 161 + +#define STM32MP1_LAST_CLK 162 + +/* SCMI clock identifiers */ +#define CK_SCMI0_HSE 0 +#define CK_SCMI0_HSI 1 +#define CK_SCMI0_CSI 2 +#define CK_SCMI0_LSE 3 +#define CK_SCMI0_LSI 4 +#define CK_SCMI0_HSE_DIV2 5 +#define CK_SCMI0_PLL2_Q 6 +#define CK_SCMI0_PLL2_R 7 +#define CK_SCMI0_PLL3_P 8 +#define CK_SCMI0_PLL3_Q 9 +#define CK_SCMI0_PLL3_R 10 +#define CK_SCMI0_PLL4_P 11 +#define CK_SCMI0_PLL4_Q 12 +#define CK_SCMI0_PLL4_R 13 +#define CK_SCMI0_MPU 14 +#define CK_SCMI0_AXI 15 +#define CK_SCMI0_MLAHB 16 +#define CK_SCMI0_CKPER 17 +#define CK_SCMI0_PCLK1 18 +#define CK_SCMI0_PCLK2 19 +#define CK_SCMI0_PCLK3 20 +#define CK_SCMI0_PCLK4 21 +#define CK_SCMI0_PCLK5 22 +#define CK_SCMI0_PCLK6 23 +#define CK_SCMI0_CKTIMG1 24 +#define CK_SCMI0_CKTIMG2 25 +#define CK_SCMI0_CKTIMG3 26 +#define CK_SCMI0_RTC 27 +#define CK_SCMI0_RTCAPB 28 +#define CK_SCMI0_BSEC 29 + +#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp13-clksrc.h b/include/dt-bindings/clock/stm32mp13-clksrc.h new file mode 100644 index 000000000..0d54ab98d --- /dev/null +++ b/include/dt-bindings/clock/stm32mp13-clksrc.h @@ -0,0 +1,394 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ +#define _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ + +#define CMD_DIV 0 +#define CMD_MUX 1 +#define CMD_CLK 2 +#define CMD_RESERVED1 3 + +#define CMD_SHIFT 26 +#define CMD_MASK 0xFC000000 +#define CMD_DATA_MASK 0x03FFFFFF + +#define DIV_ID_SHIFT 8 +#define DIV_ID_MASK 0x0000FF00 + +#define DIV_DIVN_SHIFT 0 +#define DIV_DIVN_MASK 0x000000FF + +#define MUX_ID_SHIFT 4 +#define MUX_ID_MASK 0x00000FF0 + +#define MUX_SEL_SHIFT 0 +#define MUX_SEL_MASK 0x0000000F + +#define CLK_ID_MASK GENMASK_32(19, 11) +#define CLK_ID_SHIFT 11 +#define CLK_ON_MASK 0x00000400 +#define CLK_ON_SHIFT 10 +#define CLK_DIV_MASK GENMASK_32(9, 4) +#define CLK_DIV_SHIFT 4 +#define CLK_SEL_MASK GENMASK_32(3, 0) +#define CLK_SEL_SHIFT 0 + +#define DIV_PLL1DIVP 0 +#define DIV_PLL2DIVP 1 +#define DIV_PLL2DIVQ 2 +#define DIV_PLL2DIVR 3 +#define DIV_PLL3DIVP 4 +#define DIV_PLL3DIVQ 5 +#define DIV_PLL3DIVR 6 +#define DIV_PLL4DIVP 7 +#define DIV_PLL4DIVQ 8 +#define DIV_PLL4DIVR 9 +#define DIV_MPU 10 +#define DIV_AXI 11 +#define DIV_MLAHB 12 +#define DIV_APB1 13 +#define DIV_APB2 14 +#define DIV_APB3 15 +#define DIV_APB4 16 +#define DIV_APB5 17 +#define DIV_APB6 18 +#define DIV_RTC 19 +#define DIV_MCO1 20 +#define DIV_MCO2 21 +#define DIV_HSI 22 +#define DIV_TRACE 23 +#define DIV_ETH1PTP 24 +#define DIV_ETH2PTP 25 +#define DIV_MAX 26 + +#define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ + ((div_id) << DIV_ID_SHIFT |\ + (div))) + +#define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ + ((mux_id) << MUX_ID_SHIFT |\ + (sel))) + +/* MCO output is enable */ +#define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\ + (((mco_id) << CLK_ID_SHIFT) |\ + (sel)) | CLK_ON_MASK) + +#define MCO_DISABLED(mco_id) ((CMD_CLK << CMD_SHIFT) |\ + ((mco_id) << CLK_ID_SHIFT)) + +/* CLK output is enable */ +#define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ + (((clk_id) << CLK_ID_SHIFT) |\ + (sel)) | CLK_ON_MASK) + +#define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\ + ((clk_id) << CLK_ID_SHIFT)) + +#define MUX_MPU 0 +#define MUX_AXI 1 +#define MUX_MLAHB 2 +#define MUX_PLL12 3 +#define MUX_PLL3 4 +#define MUX_PLL4 5 +#define MUX_RTC 6 +#define MUX_MCO1 7 +#define MUX_MCO2 8 +#define MUX_CKPER 9 +#define MUX_KERNEL_BEGIN 10 +#define MUX_ADC1 10 +#define MUX_ADC2 11 +#define MUX_DCMIPP 12 +#define MUX_ETH1 13 +#define MUX_ETH2 14 +#define MUX_FDCAN 15 +#define MUX_FMC 16 +#define MUX_I2C12 17 +#define MUX_I2C3 18 +#define MUX_I2C4 19 +#define MUX_I2C5 20 +#define MUX_LPTIM1 21 +#define MUX_LPTIM2 22 +#define MUX_LPTIM3 23 +#define MUX_LPTIM45 24 +#define MUX_QSPI 25 +#define MUX_RNG1 26 +#define MUX_SAES 27 +#define MUX_SAI1 28 +#define MUX_SAI2 29 +#define MUX_SDMMC1 30 +#define MUX_SDMMC2 31 +#define MUX_SPDIF 32 +#define MUX_SPI1 33 +#define MUX_SPI23 34 +#define MUX_SPI4 35 +#define MUX_SPI5 36 +#define MUX_STGEN 37 +#define MUX_UART1 38 +#define MUX_UART2 39 +#define MUX_UART35 40 +#define MUX_UART4 41 +#define MUX_UART6 42 +#define MUX_UART78 43 +#define MUX_USBO 44 +#define MUX_USBPHY 45 +#define MUX_MAX 46 + +#define CLK_MPU_HSI CLKSRC(MUX_MPU, 0) +#define CLK_MPU_HSE CLKSRC(MUX_MPU, 1) +#define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2) +#define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3) + +#define CLK_AXI_HSI CLKSRC(MUX_AXI, 0) +#define CLK_AXI_HSE CLKSRC(MUX_AXI, 1) +#define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2) + +#define CLK_MLAHBS_HSI CLKSRC(MUX_MLAHB, 0) +#define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1) +#define CLK_MLAHBS_CSI CLKSRC(MUX_MLAHB, 2) +#define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3) + +#define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0) +#define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1) + +#define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0) +#define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1) +#define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2) + +#define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0) +#define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1) +#define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2) + +#define CLK_RTC_DISABLED CLK_DISABLED(RTC) +#define CLK_RTC_LSE CLK_SRC(RTC, 1) +#define CLK_RTC_LSI CLK_SRC(RTC, 2) +#define CLK_RTC_HSE CLK_SRC(RTC, 3) + +#define CLK_MCO1_HSI CLK_SRC(CK_MCO1, 0) +#define CLK_MCO1_HSE CLK_SRC(CK_MCO1, 1) +#define CLK_MCO1_CSI CLK_SRC(CK_MCO1, 2) +#define CLK_MCO1_LSI CLK_SRC(CK_MCO1, 3) +#define CLK_MCO1_LSE CLK_SRC(CK_MCO1, 4) +#define CLK_MCO1_DISABLED CLK_DISABLED(CK_MCO1) + +#define CLK_MCO2_MPU CLK_SRC(CK_MCO2, 0) +#define CLK_MCO2_AXI CLK_SRC(CK_MCO2, 1) +#define CLK_MCO2_MLAHB CLK_SRC(CK_MCO2, 2) +#define CLK_MCO2_PLL4 CLK_SRC(CK_MCO2, 3) +#define CLK_MCO2_HSE CLK_SRC(CK_MCO2, 4) +#define CLK_MCO2_HSI CLK_SRC(CK_MCO2, 5) +#define CLK_MCO2_DISABLED CLK_DISABLED(CK_MCO2) + +#define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0) +#define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1) +#define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2) +#define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3) + +#define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0) +#define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1) +#define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2) +#define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3) + +#define CLK_I2C3_PCLK6 CLKSRC(MUX_I2C3, 0) +#define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1) +#define CLK_I2C3_HSI CLKSRC(MUX_I2C3, 2) +#define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3) + +#define CLK_I2C4_PCLK6 CLKSRC(MUX_I2C4, 0) +#define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1) +#define CLK_I2C4_HSI CLKSRC(MUX_I2C4, 2) +#define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3) + +#define CLK_I2C5_PCLK6 CLKSRC(MUX_I2C5, 0) +#define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1) +#define CLK_I2C5_HSI CLKSRC(MUX_I2C5, 2) +#define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3) + +#define CLK_SPI1_PLL4P CLKSRC(MUX_SPI1, 0) +#define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1) +#define CLK_SPI1_I2SCKIN CLKSRC(MUX_SPI1, 2) +#define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3) +#define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4) + +#define CLK_SPI23_PLL4P CLKSRC(MUX_SPI23, 0) +#define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1) +#define CLK_SPI23_I2SCKIN CLKSRC(MUX_SPI23, 2) +#define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3) +#define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4) + +#define CLK_SPI4_PCLK6 CLKSRC(MUX_SPI4, 0) +#define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1) +#define CLK_SPI4_HSI CLKSRC(MUX_SPI4, 2) +#define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3) +#define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4) +#define CLK_SPI4_I2SCKIN CLKSRC(MUX_SPI4, 5) + +#define CLK_SPI5_PCLK6 CLKSRC(MUX_SPI5, 0) +#define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1) +#define CLK_SPI5_HSI CLKSRC(MUX_SPI5, 2) +#define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3) +#define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4) + +#define CLK_UART1_PCLK6 CLKSRC(MUX_UART1, 0) +#define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1) +#define CLK_UART1_HSI CLKSRC(MUX_UART1, 2) +#define CLK_UART1_CSI CLKSRC(MUX_UART1, 3) +#define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4) +#define CLK_UART1_HSE CLKSRC(MUX_UART1, 5) + +#define CLK_UART2_PCLK6 CLKSRC(MUX_UART2, 0) +#define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1) +#define CLK_UART2_HSI CLKSRC(MUX_UART2, 2) +#define CLK_UART2_CSI CLKSRC(MUX_UART2, 3) +#define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4) +#define CLK_UART2_HSE CLKSRC(MUX_UART2, 5) + +#define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0) +#define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1) +#define CLK_UART35_HSI CLKSRC(MUX_UART35, 2) +#define CLK_UART35_CSI CLKSRC(MUX_UART35, 3) +#define CLK_UART35_HSE CLKSRC(MUX_UART35, 4) + +#define CLK_UART4_PCLK1 CLKSRC(MUX_UART4, 0) +#define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1) +#define CLK_UART4_HSI CLKSRC(MUX_UART4, 2) +#define CLK_UART4_CSI CLKSRC(MUX_UART4, 3) +#define CLK_UART4_HSE CLKSRC(MUX_UART4, 4) + +#define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0) +#define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1) +#define CLK_UART6_HSI CLKSRC(MUX_UART6, 2) +#define CLK_UART6_CSI CLKSRC(MUX_UART6, 3) +#define CLK_UART6_HSE CLKSRC(MUX_UART6, 4) + +#define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0) +#define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1) +#define CLK_UART78_HSI CLKSRC(MUX_UART78, 2) +#define CLK_UART78_CSI CLKSRC(MUX_UART78, 3) +#define CLK_UART78_HSE CLKSRC(MUX_UART78, 4) + +#define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0) +#define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1) +#define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2) +#define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3) +#define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4) +#define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5) + +#define CLK_LPTIM2_PCLK3 CLKSRC(MUX_LPTIM2, 0) +#define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1) +#define CLK_LPTIM2_CKPER CLKSRC(MUX_LPTIM2, 2) +#define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3) +#define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4) + +#define CLK_LPTIM3_PCLK3 CLKSRC(MUX_LPTIM3, 0) +#define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1) +#define CLK_LPTIM3_CKPER CLKSRC(MUX_LPTIM3, 2) +#define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3) +#define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4) + +#define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0) +#define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1) +#define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2) +#define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3) +#define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4) +#define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5) + +#define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0) +#define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1) +#define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2) +#define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3) +#define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4) + +#define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0) +#define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1) +#define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2) +#define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3) +#define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4) +#define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5) + +#define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0) +#define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1) +#define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2) +#define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3) + +#define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0) +#define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1) +#define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2) + +#define CLK_ADC1_PLL4R CLKSRC(MUX_ADC1, 0) +#define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1) +#define CLK_ADC1_PLL3Q CLKSRC(MUX_ADC1, 2) + +#define CLK_ADC2_PLL4R CLKSRC(MUX_ADC2, 0) +#define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1) +#define CLK_ADC2_PLL3Q CLKSRC(MUX_ADC2, 2) + +#define CLK_SDMMC1_HCLK6 CLKSRC(MUX_SDMMC1, 0) +#define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1) +#define CLK_SDMMC1_PLL4P CLKSRC(MUX_SDMMC1, 2) +#define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3) + +#define CLK_SDMMC2_HCLK6 CLKSRC(MUX_SDMMC2, 0) +#define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1) +#define CLK_SDMMC2_PLL4P CLKSRC(MUX_SDMMC2, 2) +#define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3) + +#define CLK_ETH1_PLL4P CLKSRC(MUX_ETH1, 0) +#define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1) + +#define CLK_ETH2_PLL4P CLKSRC(MUX_ETH2, 0) +#define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1) + +#define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0) +#define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1) +#define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2) + +#define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0) +#define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1) + +#define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0) +#define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1) +#define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2) +#define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3) + +#define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0) +#define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1) +#define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2) +#define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3) + +#define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0) +#define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1) +/* WARNING: POSITION 2 OF RNG1 MUX IS RESERVED */ +#define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3) + +#define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0) +#define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1) + +#define CLK_DCMIPP_ACLK CLKSRC(MUX_DCMIPP, 0) +#define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1) +#define CLK_DCMIPP_PLL4P CLKSRC(MUX_DCMIPP, 2) +#define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3) + +#define CLK_SAES_AXI CLKSRC(MUX_SAES, 0) +#define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1) +#define CLK_SAES_PLL4R CLKSRC(MUX_SAES, 2) +#define CLK_SAES_LSI CLKSRC(MUX_SAES, 3) + +/* PLL output is enable when x=1, with x=p,q or r */ +#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) + +/* define for st,pll /csg */ +#define SSCG_MODE_CENTER_SPREAD 0 +#define SSCG_MODE_DOWN_SPREAD 1 + +/* define for st,drive */ +#define LSEDRV_LOWEST 0 +#define LSEDRV_MEDIUM_LOW 1 +#define LSEDRV_MEDIUM_HIGH 2 +#define LSEDRV_HIGHEST 3 + +#endif /* _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ */ diff --git a/include/dt-bindings/clock/stm32mp15-clks.h b/include/dt-bindings/clock/stm32mp15-clks.h new file mode 100644 index 000000000..bef1368ee --- /dev/null +++ b/include/dt-bindings/clock/stm32mp15-clks.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ +#define _DT_BINDINGS_STM32MP1_CLKS_H_ + +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* Bus clocks */ +#define TIM2 6 +#define TIM3 7 +#define TIM4 8 +#define TIM5 9 +#define TIM6 10 +#define TIM7 11 +#define TIM12 12 +#define TIM13 13 +#define TIM14 14 +#define LPTIM1 15 +#define SPI2 16 +#define SPI3 17 +#define USART2 18 +#define USART3 19 +#define UART4 20 +#define UART5 21 +#define UART7 22 +#define UART8 23 +#define I2C1 24 +#define I2C2 25 +#define I2C3 26 +#define I2C5 27 +#define SPDIF 28 +#define CEC 29 +#define DAC12 30 +#define MDIO 31 +#define TIM1 32 +#define TIM8 33 +#define TIM15 34 +#define TIM16 35 +#define TIM17 36 +#define SPI1 37 +#define SPI4 38 +#define SPI5 39 +#define USART6 40 +#define SAI1 41 +#define SAI2 42 +#define SAI3 43 +#define DFSDM 44 +#define FDCAN 45 +#define LPTIM2 46 +#define LPTIM3 47 +#define LPTIM4 48 +#define LPTIM5 49 +#define SAI4 50 +#define SYSCFG 51 +#define VREF 52 +#define TMPSENS 53 +#define PMBCTRL 54 +#define HDP 55 +#define LTDC 56 +#define DSI 57 +#define IWDG2 58 +#define USBPHY 59 +#define STGENRO 60 +#define SPI6 61 +#define I2C4 62 +#define I2C6 63 +#define USART1 64 +#define RTCAPB 65 +#define TZC1 66 +#define TZPC 67 +#define IWDG1 68 +#define BSEC 69 +#define STGEN 70 +#define DMA1 71 +#define DMA2 72 +#define DMAMUX 73 +#define ADC12 74 +#define USBO 75 +#define SDMMC3 76 +#define DCMI 77 +#define CRYP2 78 +#define HASH2 79 +#define RNG2 80 +#define CRC2 81 +#define HSEM 82 +#define IPCC 83 +#define GPIOA 84 +#define GPIOB 85 +#define GPIOC 86 +#define GPIOD 87 +#define GPIOE 88 +#define GPIOF 89 +#define GPIOG 90 +#define GPIOH 91 +#define GPIOI 92 +#define GPIOJ 93 +#define GPIOK 94 +#define GPIOZ 95 +#define CRYP1 96 +#define HASH1 97 +#define RNG1 98 +#define BKPSRAM 99 +#define MDMA 100 +#define GPU 101 +#define ETHCK 102 +#define ETHTX 103 +#define ETHRX 104 +#define ETHMAC 105 +#define FMC 106 +#define QSPI 107 +#define SDMMC1 108 +#define SDMMC2 109 +#define CRC1 110 +#define USBH 111 +#define ETHSTP 112 +#define TZC2 113 + +/* Kernel clocks */ +#define SDMMC1_K 118 +#define SDMMC2_K 119 +#define SDMMC3_K 120 +#define FMC_K 121 +#define QSPI_K 122 +#define ETHCK_K 123 +#define RNG1_K 124 +#define RNG2_K 125 +#define GPU_K 126 +#define USBPHY_K 127 +#define STGEN_K 128 +#define SPDIF_K 129 +#define SPI1_K 130 +#define SPI2_K 131 +#define SPI3_K 132 +#define SPI4_K 133 +#define SPI5_K 134 +#define SPI6_K 135 +#define CEC_K 136 +#define I2C1_K 137 +#define I2C2_K 138 +#define I2C3_K 139 +#define I2C4_K 140 +#define I2C5_K 141 +#define I2C6_K 142 +#define LPTIM1_K 143 +#define LPTIM2_K 144 +#define LPTIM3_K 145 +#define LPTIM4_K 146 +#define LPTIM5_K 147 +#define USART1_K 148 +#define USART2_K 149 +#define USART3_K 150 +#define UART4_K 151 +#define UART5_K 152 +#define USART6_K 153 +#define UART7_K 154 +#define UART8_K 155 +#define DFSDM_K 156 +#define FDCAN_K 157 +#define SAI1_K 158 +#define SAI2_K 159 +#define SAI3_K 160 +#define SAI4_K 161 +#define ADC12_K 162 +#define DSI_K 163 +#define DSI_PX 164 +#define ADFSDM_K 165 +#define USBO_K 166 +#define LTDC_PX 167 +#define DAC12_K 168 +#define ETHPTP_K 169 + +/* PLL */ +#define PLL1 176 +#define PLL2 177 +#define PLL3 178 +#define PLL4 179 + +/* ODF */ +#define PLL1_P 180 +#define PLL1_Q 181 +#define PLL1_R 182 +#define PLL2_P 183 +#define PLL2_Q 184 +#define PLL2_R 185 +#define PLL3_P 186 +#define PLL3_Q 187 +#define PLL3_R 188 +#define PLL4_P 189 +#define PLL4_Q 190 +#define PLL4_R 191 + +/* AUX */ +#define RTC 192 + +/* MCLK */ +#define CK_PER 193 +#define CK_MPU 194 +#define CK_AXI 195 +#define CK_MCU 196 + +/* Time base */ +#define TIM2_K 197 +#define TIM3_K 198 +#define TIM4_K 199 +#define TIM5_K 200 +#define TIM6_K 201 +#define TIM7_K 202 +#define TIM12_K 203 +#define TIM13_K 204 +#define TIM14_K 205 +#define TIM1_K 206 +#define TIM8_K 207 +#define TIM15_K 208 +#define TIM16_K 209 +#define TIM17_K 210 + +/* MCO clocks */ +#define CK_MCO1 211 +#define CK_MCO2 212 + +/* TRACE & DEBUG clocks */ +#define CK_DBG 214 +#define CK_TRACE 215 + +/* DDR */ +#define DDRC1 220 +#define DDRC1LP 221 +#define DDRC2 222 +#define DDRC2LP 223 +#define DDRPHYC 224 +#define DDRPHYCLP 225 +#define DDRCAPB 226 +#define DDRCAPBLP 227 +#define AXIDCG 228 +#define DDRPHYCAPB 229 +#define DDRPHYCAPBLP 230 +#define DDRPERFM 231 + +#define STM32MP1_LAST_CLK 232 + +/* SCMI clock identifiers */ +#define CK_SCMI0_HSE 0 +#define CK_SCMI0_HSI 1 +#define CK_SCMI0_CSI 2 +#define CK_SCMI0_LSE 3 +#define CK_SCMI0_LSI 4 +#define CK_SCMI0_PLL2_Q 5 +#define CK_SCMI0_PLL2_R 6 +#define CK_SCMI0_MPU 7 +#define CK_SCMI0_AXI 8 +#define CK_SCMI0_BSEC 9 +#define CK_SCMI0_CRYP1 10 +#define CK_SCMI0_GPIOZ 11 +#define CK_SCMI0_HASH1 12 +#define CK_SCMI0_I2C4 13 +#define CK_SCMI0_I2C6 14 +#define CK_SCMI0_IWDG1 15 +#define CK_SCMI0_RNG1 16 +#define CK_SCMI0_RTC 17 +#define CK_SCMI0_RTCAPB 18 +#define CK_SCMI0_SPI6 19 +#define CK_SCMI0_USART1 20 + +#define CK_SCMI1_PLL3_Q 0 +#define CK_SCMI1_PLL3_R 1 +#define CK_SCMI1_MCU 2 + +#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp15-clksrc.h b/include/dt-bindings/clock/stm32mp15-clksrc.h new file mode 100644 index 000000000..3a3792da3 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp15-clksrc.h @@ -0,0 +1,282 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved + */ + +#ifndef _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_ +#define _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_ + +/* PLL output is enable when x=1, with x=p,q or r */ +#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) + +/* st,clksrc: mandatory clock source */ +#define CLK_MPU_HSI 0x00000200 +#define CLK_MPU_HSE 0x00000201 +#define CLK_MPU_PLL1P 0x00000202 +#define CLK_MPU_PLL1P_DIV 0x00000203 + +#define CLK_AXI_HSI 0x00000240 +#define CLK_AXI_HSE 0x00000241 +#define CLK_AXI_PLL2P 0x00000242 + +#define CLK_MCU_HSI 0x00000480 +#define CLK_MCU_HSE 0x00000481 +#define CLK_MCU_CSI 0x00000482 +#define CLK_MCU_PLL3P 0x00000483 + +#define CLK_PLL12_HSI 0x00000280 +#define CLK_PLL12_HSE 0x00000281 + +#define CLK_PLL3_HSI 0x00008200 +#define CLK_PLL3_HSE 0x00008201 +#define CLK_PLL3_CSI 0x00008202 + +#define CLK_PLL4_HSI 0x00008240 +#define CLK_PLL4_HSE 0x00008241 +#define CLK_PLL4_CSI 0x00008242 +#define CLK_PLL4_I2SCKIN 0x00008243 + +#define CLK_RTC_DISABLED 0x00001400 +#define CLK_RTC_LSE 0x00001401 +#define CLK_RTC_LSI 0x00001402 +#define CLK_RTC_HSE 0x00001403 + +#define CLK_MCO1_HSI 0x00008000 +#define CLK_MCO1_HSE 0x00008001 +#define CLK_MCO1_CSI 0x00008002 +#define CLK_MCO1_LSI 0x00008003 +#define CLK_MCO1_LSE 0x00008004 +#define CLK_MCO1_DISABLED 0x0000800F + +#define CLK_MCO2_MPU 0x00008040 +#define CLK_MCO2_AXI 0x00008041 +#define CLK_MCO2_MCU 0x00008042 +#define CLK_MCO2_PLL4P 0x00008043 +#define CLK_MCO2_HSE 0x00008044 +#define CLK_MCO2_HSI 0x00008045 +#define CLK_MCO2_DISABLED 0x0000804F + +/* st,pkcs: peripheral kernel clock source */ + +#define CLK_I2C12_PCLK1 0x00008C00 +#define CLK_I2C12_PLL4R 0x00008C01 +#define CLK_I2C12_HSI 0x00008C02 +#define CLK_I2C12_CSI 0x00008C03 +#define CLK_I2C12_DISABLED 0x00008C07 + +#define CLK_I2C35_PCLK1 0x00008C40 +#define CLK_I2C35_PLL4R 0x00008C41 +#define CLK_I2C35_HSI 0x00008C42 +#define CLK_I2C35_CSI 0x00008C43 +#define CLK_I2C35_DISABLED 0x00008C47 + +#define CLK_I2C46_PCLK5 0x00000C00 +#define CLK_I2C46_PLL3Q 0x00000C01 +#define CLK_I2C46_HSI 0x00000C02 +#define CLK_I2C46_CSI 0x00000C03 +#define CLK_I2C46_DISABLED 0x00000C07 + +#define CLK_SAI1_PLL4Q 0x00008C80 +#define CLK_SAI1_PLL3Q 0x00008C81 +#define CLK_SAI1_I2SCKIN 0x00008C82 +#define CLK_SAI1_CKPER 0x00008C83 +#define CLK_SAI1_PLL3R 0x00008C84 +#define CLK_SAI1_DISABLED 0x00008C87 + +#define CLK_SAI2_PLL4Q 0x00008CC0 +#define CLK_SAI2_PLL3Q 0x00008CC1 +#define CLK_SAI2_I2SCKIN 0x00008CC2 +#define CLK_SAI2_CKPER 0x00008CC3 +#define CLK_SAI2_SPDIF 0x00008CC4 +#define CLK_SAI2_PLL3R 0x00008CC5 +#define CLK_SAI2_DISABLED 0x00008CC7 + +#define CLK_SAI3_PLL4Q 0x00008D00 +#define CLK_SAI3_PLL3Q 0x00008D01 +#define CLK_SAI3_I2SCKIN 0x00008D02 +#define CLK_SAI3_CKPER 0x00008D03 +#define CLK_SAI3_PLL3R 0x00008D04 +#define CLK_SAI3_DISABLED 0x00008D07 + +#define CLK_SAI4_PLL4Q 0x00008D40 +#define CLK_SAI4_PLL3Q 0x00008D41 +#define CLK_SAI4_I2SCKIN 0x00008D42 +#define CLK_SAI4_CKPER 0x00008D43 +#define CLK_SAI4_PLL3R 0x00008D44 +#define CLK_SAI4_DISABLED 0x00008D47 + +#define CLK_SPI2S1_PLL4P 0x00008D80 +#define CLK_SPI2S1_PLL3Q 0x00008D81 +#define CLK_SPI2S1_I2SCKIN 0x00008D82 +#define CLK_SPI2S1_CKPER 0x00008D83 +#define CLK_SPI2S1_PLL3R 0x00008D84 +#define CLK_SPI2S1_DISABLED 0x00008D87 + +#define CLK_SPI2S23_PLL4P 0x00008DC0 +#define CLK_SPI2S23_PLL3Q 0x00008DC1 +#define CLK_SPI2S23_I2SCKIN 0x00008DC2 +#define CLK_SPI2S23_CKPER 0x00008DC3 +#define CLK_SPI2S23_PLL3R 0x00008DC4 +#define CLK_SPI2S23_DISABLED 0x00008DC7 + +#define CLK_SPI45_PCLK2 0x00008E00 +#define CLK_SPI45_PLL4Q 0x00008E01 +#define CLK_SPI45_HSI 0x00008E02 +#define CLK_SPI45_CSI 0x00008E03 +#define CLK_SPI45_HSE 0x00008E04 +#define CLK_SPI45_DISABLED 0x00008E07 + +#define CLK_SPI6_PCLK5 0x00000C40 +#define CLK_SPI6_PLL4Q 0x00000C41 +#define CLK_SPI6_HSI 0x00000C42 +#define CLK_SPI6_CSI 0x00000C43 +#define CLK_SPI6_HSE 0x00000C44 +#define CLK_SPI6_PLL3Q 0x00000C45 +#define CLK_SPI6_DISABLED 0x00000C47 + +#define CLK_UART6_PCLK2 0x00008E40 +#define CLK_UART6_PLL4Q 0x00008E41 +#define CLK_UART6_HSI 0x00008E42 +#define CLK_UART6_CSI 0x00008E43 +#define CLK_UART6_HSE 0x00008E44 +#define CLK_UART6_DISABLED 0x00008E47 + +#define CLK_UART24_PCLK1 0x00008E80 +#define CLK_UART24_PLL4Q 0x00008E81 +#define CLK_UART24_HSI 0x00008E82 +#define CLK_UART24_CSI 0x00008E83 +#define CLK_UART24_HSE 0x00008E84 +#define CLK_UART24_DISABLED 0x00008E87 + +#define CLK_UART35_PCLK1 0x00008EC0 +#define CLK_UART35_PLL4Q 0x00008EC1 +#define CLK_UART35_HSI 0x00008EC2 +#define CLK_UART35_CSI 0x00008EC3 +#define CLK_UART35_HSE 0x00008EC4 +#define CLK_UART35_DISABLED 0x00008EC7 + +#define CLK_UART78_PCLK1 0x00008F00 +#define CLK_UART78_PLL4Q 0x00008F01 +#define CLK_UART78_HSI 0x00008F02 +#define CLK_UART78_CSI 0x00008F03 +#define CLK_UART78_HSE 0x00008F04 +#define CLK_UART78_DISABLED 0x00008F07 + +#define CLK_UART1_PCLK5 0x00000C80 +#define CLK_UART1_PLL3Q 0x00000C81 +#define CLK_UART1_HSI 0x00000C82 +#define CLK_UART1_CSI 0x00000C83 +#define CLK_UART1_PLL4Q 0x00000C84 +#define CLK_UART1_HSE 0x00000C85 +#define CLK_UART1_DISABLED 0x00000C87 + +#define CLK_SDMMC12_HCLK6 0x00008F40 +#define CLK_SDMMC12_PLL3R 0x00008F41 +#define CLK_SDMMC12_PLL4P 0x00008F42 +#define CLK_SDMMC12_HSI 0x00008F43 +#define CLK_SDMMC12_DISABLED 0x00008F47 + +#define CLK_SDMMC3_HCLK2 0x00008F80 +#define CLK_SDMMC3_PLL3R 0x00008F81 +#define CLK_SDMMC3_PLL4P 0x00008F82 +#define CLK_SDMMC3_HSI 0x00008F83 +#define CLK_SDMMC3_DISABLED 0x00008F87 + +#define CLK_ETH_PLL4P 0x00008FC0 +#define CLK_ETH_PLL3Q 0x00008FC1 +#define CLK_ETH_DISABLED 0x00008FC3 + +#define CLK_QSPI_ACLK 0x00009000 +#define CLK_QSPI_PLL3R 0x00009001 +#define CLK_QSPI_PLL4P 0x00009002 +#define CLK_QSPI_CKPER 0x00009003 + +#define CLK_FMC_ACLK 0x00009040 +#define CLK_FMC_PLL3R 0x00009041 +#define CLK_FMC_PLL4P 0x00009042 +#define CLK_FMC_CKPER 0x00009043 + +#define CLK_FDCAN_HSE 0x000090C0 +#define CLK_FDCAN_PLL3Q 0x000090C1 +#define CLK_FDCAN_PLL4Q 0x000090C2 +#define CLK_FDCAN_PLL4R 0x000090C3 + +#define CLK_SPDIF_PLL4P 0x00009140 +#define CLK_SPDIF_PLL3Q 0x00009141 +#define CLK_SPDIF_HSI 0x00009142 +#define CLK_SPDIF_DISABLED 0x00009143 + +#define CLK_CEC_LSE 0x00009180 +#define CLK_CEC_LSI 0x00009181 +#define CLK_CEC_CSI_DIV122 0x00009182 +#define CLK_CEC_DISABLED 0x00009183 + +#define CLK_USBPHY_HSE 0x000091C0 +#define CLK_USBPHY_PLL4R 0x000091C1 +#define CLK_USBPHY_HSE_DIV2 0x000091C2 +#define CLK_USBPHY_DISABLED 0x000091C3 + +#define CLK_USBO_PLL4R 0x800091C0 +#define CLK_USBO_USBPHY 0x800091C1 + +#define CLK_RNG1_CSI 0x00000CC0 +#define CLK_RNG1_PLL4R 0x00000CC1 +#define CLK_RNG1_LSE 0x00000CC2 +#define CLK_RNG1_LSI 0x00000CC3 + +#define CLK_RNG2_CSI 0x00009200 +#define CLK_RNG2_PLL4R 0x00009201 +#define CLK_RNG2_LSE 0x00009202 +#define CLK_RNG2_LSI 0x00009203 + +#define CLK_CKPER_HSI 0x00000D00 +#define CLK_CKPER_CSI 0x00000D01 +#define CLK_CKPER_HSE 0x00000D02 +#define CLK_CKPER_DISABLED 0x00000D03 + +#define CLK_STGEN_HSI 0x00000D40 +#define CLK_STGEN_HSE 0x00000D41 +#define CLK_STGEN_DISABLED 0x00000D43 + +#define CLK_DSI_DSIPLL 0x00009240 +#define CLK_DSI_PLL4P 0x00009241 + +#define CLK_ADC_PLL4R 0x00009280 +#define CLK_ADC_CKPER 0x00009281 +#define CLK_ADC_PLL3Q 0x00009282 +#define CLK_ADC_DISABLED 0x00009283 + +#define CLK_LPTIM45_PCLK3 0x000092C0 +#define CLK_LPTIM45_PLL4P 0x000092C1 +#define CLK_LPTIM45_PLL3Q 0x000092C2 +#define CLK_LPTIM45_LSE 0x000092C3 +#define CLK_LPTIM45_LSI 0x000092C4 +#define CLK_LPTIM45_CKPER 0x000092C5 +#define CLK_LPTIM45_DISABLED 0x000092C7 + +#define CLK_LPTIM23_PCLK3 0x00009300 +#define CLK_LPTIM23_PLL4Q 0x00009301 +#define CLK_LPTIM23_CKPER 0x00009302 +#define CLK_LPTIM23_LSE 0x00009303 +#define CLK_LPTIM23_LSI 0x00009304 +#define CLK_LPTIM23_DISABLED 0x00009307 + +#define CLK_LPTIM1_PCLK1 0x00009340 +#define CLK_LPTIM1_PLL4P 0x00009341 +#define CLK_LPTIM1_PLL3Q 0x00009342 +#define CLK_LPTIM1_LSE 0x00009343 +#define CLK_LPTIM1_LSI 0x00009344 +#define CLK_LPTIM1_CKPER 0x00009345 +#define CLK_LPTIM1_DISABLED 0x00009347 + +/* define for st,pll /csg */ +#define SSCG_MODE_CENTER_SPREAD 0 +#define SSCG_MODE_DOWN_SPREAD 1 + +/* define for st,drive */ +#define LSEDRV_LOWEST 0 +#define LSEDRV_MEDIUM_LOW 1 +#define LSEDRV_MEDIUM_HIGH 2 +#define LSEDRV_HIGHEST 3 + +#endif diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index bc71924fa..d40b1a24a 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -1,121 +1,11 @@ -/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez for STMicroelectronics. + * Copyright (C) 2020-2022, STMicroelectronics - All Rights Reserved */ -#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ -#define _DT_BINDINGS_STM32MP1_RESET_H_ - -#define LTDC_R 3072 -#define DSI_R 3076 -#define DDRPERFM_R 3080 -#define USBPHY_R 3088 -#define SPI6_R 3136 -#define I2C4_R 3138 -#define I2C6_R 3139 -#define USART1_R 3140 -#define STGEN_R 3156 -#define GPIOZ_R 3200 -#define CRYP1_R 3204 -#define HASH1_R 3205 -#define RNG1_R 3206 -#define AXIM_R 3216 -#define GPU_R 3269 -#define ETHMAC_R 3274 -#define FMC_R 3276 -#define QSPI_R 3278 -#define SDMMC1_R 3280 -#define SDMMC2_R 3281 -#define CRC1_R 3284 -#define USBH_R 3288 -#define MDMA_R 3328 -#define MCU_R 8225 -#define TIM2_R 19456 -#define TIM3_R 19457 -#define TIM4_R 19458 -#define TIM5_R 19459 -#define TIM6_R 19460 -#define TIM7_R 19461 -#define TIM12_R 16462 -#define TIM13_R 16463 -#define TIM14_R 16464 -#define LPTIM1_R 19465 -#define SPI2_R 19467 -#define SPI3_R 19468 -#define USART2_R 19470 -#define USART3_R 19471 -#define UART4_R 19472 -#define UART5_R 19473 -#define UART7_R 19474 -#define UART8_R 19475 -#define I2C1_R 19477 -#define I2C2_R 19478 -#define I2C3_R 19479 -#define I2C5_R 19480 -#define SPDIF_R 19482 -#define CEC_R 19483 -#define DAC12_R 19485 -#define MDIO_R 19847 -#define TIM1_R 19520 -#define TIM8_R 19521 -#define TIM15_R 19522 -#define TIM16_R 19523 -#define TIM17_R 19524 -#define SPI1_R 19528 -#define SPI4_R 19529 -#define SPI5_R 19530 -#define USART6_R 19533 -#define SAI1_R 19536 -#define SAI2_R 19537 -#define SAI3_R 19538 -#define DFSDM_R 19540 -#define FDCAN_R 19544 -#define LPTIM2_R 19584 -#define LPTIM3_R 19585 -#define LPTIM4_R 19586 -#define LPTIM5_R 19587 -#define SAI4_R 19592 -#define SYSCFG_R 19595 -#define VREF_R 19597 -#define TMPSENS_R 19600 -#define PMBCTRL_R 19601 -#define DMA1_R 19648 -#define DMA2_R 19649 -#define DMAMUX_R 19650 -#define ADC12_R 19653 -#define USBO_R 19656 -#define SDMMC3_R 19664 -#define CAMITF_R 19712 -#define CRYP2_R 19716 -#define HASH2_R 19717 -#define RNG2_R 19718 -#define CRC2_R 19719 -#define HSEM_R 19723 -#define MBOX_R 19724 -#define GPIOA_R 19776 -#define GPIOB_R 19777 -#define GPIOC_R 19778 -#define GPIOD_R 19779 -#define GPIOE_R 19780 -#define GPIOF_R 19781 -#define GPIOG_R 19782 -#define GPIOH_R 19783 -#define GPIOI_R 19784 -#define GPIOJ_R 19785 -#define GPIOK_R 19786 - -/* SCMI reset domain identifiers */ -#define RST_SCMI0_SPI6 0 -#define RST_SCMI0_I2C4 1 -#define RST_SCMI0_I2C6 2 -#define RST_SCMI0_USART1 3 -#define RST_SCMI0_STGEN 4 -#define RST_SCMI0_GPIOZ 5 -#define RST_SCMI0_CRYP1 6 -#define RST_SCMI0_HASH1 7 -#define RST_SCMI0_RNG1 8 -#define RST_SCMI0_MDMA 9 -#define RST_SCMI0_MCU 10 - -#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ +#if STM32MP13 +#include "stm32mp13-resets.h" +#endif +#if STM32MP15 +#include "stm32mp15-resets.h" +#endif diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h new file mode 100644 index 000000000..8a0f80e3c --- /dev/null +++ b/include/dt-bindings/reset/stm32mp13-resets.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ +#define _DT_BINDINGS_STM32MP13_RESET_H_ + +#define TIM2_R 13568 +#define TIM3_R 13569 +#define TIM4_R 13570 +#define TIM5_R 13571 +#define TIM6_R 13572 +#define TIM7_R 13573 +#define LPTIM1_R 13577 +#define SPI2_R 13579 +#define SPI3_R 13580 +#define USART3_R 13583 +#define UART4_R 13584 +#define UART5_R 13585 +#define UART7_R 13586 +#define UART8_R 13587 +#define I2C1_R 13589 +#define I2C2_R 13590 +#define SPDIF_R 13594 +#define TIM1_R 13632 +#define TIM8_R 13633 +#define SPI1_R 13640 +#define USART6_R 13645 +#define SAI1_R 13648 +#define SAI2_R 13649 +#define DFSDM_R 13652 +#define FDCAN_R 13656 +#define LPTIM2_R 13696 +#define LPTIM3_R 13697 +#define LPTIM4_R 13698 +#define LPTIM5_R 13699 +#define SYSCFG_R 13707 +#define VREF_R 13709 +#define DTS_R 13712 +#define PMBCTRL_R 13713 +#define LTDC_R 13760 +#define DCMIPP_R 13761 +#define DDRPERFM_R 13768 +#define USBPHY_R 13776 +#define STGEN_R 13844 +#define USART1_R 13888 +#define USART2_R 13889 +#define SPI4_R 13890 +#define SPI5_R 13891 +#define I2C3_R 13892 +#define I2C4_R 13893 +#define I2C5_R 13894 +#define TIM12_R 13895 +#define TIM13_R 13896 +#define TIM14_R 13897 +#define TIM15_R 13898 +#define TIM16_R 13899 +#define TIM17_R 13900 +#define DMA1_R 13952 +#define DMA2_R 13953 +#define DMAMUX1_R 13954 +#define DMA3_R 13955 +#define DMAMUX2_R 13956 +#define ADC1_R 13957 +#define ADC2_R 13958 +#define USBO_R 13960 +#define GPIOA_R 14080 +#define GPIOB_R 14081 +#define GPIOC_R 14082 +#define GPIOD_R 14083 +#define GPIOE_R 14084 +#define GPIOF_R 14085 +#define GPIOG_R 14086 +#define GPIOH_R 14087 +#define GPIOI_R 14088 +#define TSC_R 14095 +#define PKA_R 14146 +#define SAES_R 14147 +#define CRYP1_R 14148 +#define HASH1_R 14149 +#define RNG1_R 14150 +#define AXIMC_R 14160 +#define MDMA_R 14208 +#define MCE_R 14209 +#define ETH1MAC_R 14218 +#define FMC_R 14220 +#define QSPI_R 14222 +#define SDMMC1_R 14224 +#define SDMMC2_R 14225 +#define CRC1_R 14228 +#define USBH_R 14232 +#define ETH2MAC_R 14238 + +#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ diff --git a/include/dt-bindings/reset/stm32mp15-resets.h b/include/dt-bindings/reset/stm32mp15-resets.h new file mode 100644 index 000000000..2b3486486 --- /dev/null +++ b/include/dt-bindings/reset/stm32mp15-resets.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP15_RESET_H_ +#define _DT_BINDINGS_STM32MP15_RESET_H_ + +#define MCU_HOLD_BOOT_R 2144 +#define LTDC_R 3072 +#define DSI_R 3076 +#define DDRPERFM_R 3080 +#define USBPHY_R 3088 +#define SPI6_R 3136 +#define I2C4_R 3138 +#define I2C6_R 3139 +#define USART1_R 3140 +#define STGEN_R 3156 +#define GPIOZ_R 3200 +#define CRYP1_R 3204 +#define HASH1_R 3205 +#define RNG1_R 3206 +#define AXIM_R 3216 +#define GPU_R 3269 +#define ETHMAC_R 3274 +#define FMC_R 3276 +#define QSPI_R 3278 +#define SDMMC1_R 3280 +#define SDMMC2_R 3281 +#define CRC1_R 3284 +#define USBH_R 3288 +#define MDMA_R 3328 +#define MCU_R 8225 +#define TIM2_R 19456 +#define TIM3_R 19457 +#define TIM4_R 19458 +#define TIM5_R 19459 +#define TIM6_R 19460 +#define TIM7_R 19461 +#define TIM12_R 16462 +#define TIM13_R 16463 +#define TIM14_R 16464 +#define LPTIM1_R 19465 +#define SPI2_R 19467 +#define SPI3_R 19468 +#define USART2_R 19470 +#define USART3_R 19471 +#define UART4_R 19472 +#define UART5_R 19473 +#define UART7_R 19474 +#define UART8_R 19475 +#define I2C1_R 19477 +#define I2C2_R 19478 +#define I2C3_R 19479 +#define I2C5_R 19480 +#define SPDIF_R 19482 +#define CEC_R 19483 +#define DAC12_R 19485 +#define MDIO_R 19847 +#define TIM1_R 19520 +#define TIM8_R 19521 +#define TIM15_R 19522 +#define TIM16_R 19523 +#define TIM17_R 19524 +#define SPI1_R 19528 +#define SPI4_R 19529 +#define SPI5_R 19530 +#define USART6_R 19533 +#define SAI1_R 19536 +#define SAI2_R 19537 +#define SAI3_R 19538 +#define DFSDM_R 19540 +#define FDCAN_R 19544 +#define LPTIM2_R 19584 +#define LPTIM3_R 19585 +#define LPTIM4_R 19586 +#define LPTIM5_R 19587 +#define SAI4_R 19592 +#define SYSCFG_R 19595 +#define VREF_R 19597 +#define TMPSENS_R 19600 +#define PMBCTRL_R 19601 +#define DMA1_R 19648 +#define DMA2_R 19649 +#define DMAMUX_R 19650 +#define ADC12_R 19653 +#define USBO_R 19656 +#define SDMMC3_R 19664 +#define CAMITF_R 19712 +#define CRYP2_R 19716 +#define HASH2_R 19717 +#define RNG2_R 19718 +#define CRC2_R 19719 +#define HSEM_R 19723 +#define MBOX_R 19724 +#define GPIOA_R 19776 +#define GPIOB_R 19777 +#define GPIOC_R 19778 +#define GPIOD_R 19779 +#define GPIOE_R 19780 +#define GPIOF_R 19781 +#define GPIOG_R 19782 +#define GPIOH_R 19783 +#define GPIOI_R 19784 +#define GPIOJ_R 19785 +#define GPIOK_R 19786 + +/* SCMI reset domain identifiers */ +#define RST_SCMI0_SPI6 0 +#define RST_SCMI0_I2C4 1 +#define RST_SCMI0_I2C6 2 +#define RST_SCMI0_USART1 3 +#define RST_SCMI0_STGEN 4 +#define RST_SCMI0_GPIOZ 5 +#define RST_SCMI0_CRYP1 6 +#define RST_SCMI0_HASH1 7 +#define RST_SCMI0_RNG1 8 +#define RST_SCMI0_MDMA 9 +#define RST_SCMI0_MCU 10 +#define RST_SCMI0_MCU_HOLD_BOOT 11 + +#endif /* _DT_BINDINGS_STM32MP15_RESET_H_ */ diff --git a/include/dt-bindings/soc/stm32mp13-tzc400.h b/include/dt-bindings/soc/stm32mp13-tzc400.h new file mode 100644 index 000000000..1cb2326ed --- /dev/null +++ b/include/dt-bindings/soc/stm32mp13-tzc400.h @@ -0,0 +1,35 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + * + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#ifndef _DT_BINDINGS_STM32MP13_TZC400_H +#define _DT_BINDINGS_STM32MP13_TZC400_H + +#include + +#define STM32MP1_TZC_A7_ID U(0) +#define STM32MP1_TZC_LCD_ID U(3) +#define STM32MP1_TZC_MDMA_ID U(5) +#define STM32MP1_TZC_DMA_ID U(6) +#define STM32MP1_TZC_USB_HOST_ID U(7) +#define STM32MP1_TZC_USB_OTG_ID U(8) +#define STM32MP1_TZC_SDMMC_ID U(9) +#define STM32MP1_TZC_ETH_ID U(10) +#define STM32MP1_TZC_DCMIPP_ID U(11) +#define STM32MP1_TZC_DAP_ID U(15) + +#define TZC_REGION_NSEC_ALL_ACCESS_RDWR \ + (TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DCMIPP_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID)) + +#endif /* _DT_BINDINGS_STM32MP13_TZC400_H */ diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index 33ad56f63..88d0f8a8c 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -47,7 +47,9 @@ static const char debug_msg[] = { }; #endif +#if STM32MP15 static struct stm32mp_auth_ops stm32mp1_auth_ops; +#endif static void print_reset_reason(void) { @@ -82,6 +84,7 @@ static void print_reset_reason(void) return; } +#if STM32MP15 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { INFO(" System reset generated by MCU (MCSYSRST)\n"); @@ -90,6 +93,7 @@ static void print_reset_reason(void) } return; } +#endif if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { INFO(" System reset generated by MPU (MPSYSRST)\n"); @@ -116,10 +120,12 @@ static void print_reset_reason(void) return; } +#if STM32MP15 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { INFO(" MPU Processor 1 Reset\n"); return; } +#endif if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { INFO(" Pad Reset from NRST\n"); @@ -171,6 +177,7 @@ void bl2_platform_setup(void) #endif /* STM32MP_USE_STM32IMAGE */ } +#if STM32MP15 static void update_monotonic_counter(void) { uint32_t version; @@ -204,6 +211,7 @@ static void update_monotonic_counter(void) version); } } +#endif void bl2_el3_plat_arch_setup(void) { @@ -271,8 +279,10 @@ void bl2_el3_plat_arch_setup(void) mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); } +#if STM32MP15 /* Disable MCKPROT */ mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); +#endif /* * Set minimum reset pulse duration to 31ms for discrete power @@ -307,7 +317,7 @@ void bl2_el3_plat_arch_setup(void) stm32_save_boot_interface(boot_context->boot_interface_selected, boot_context->boot_interface_instance); -#if STM32MP_USB_PROGRAMMER +#if STM32MP_USB_PROGRAMMER && STM32MP15 /* Deconfigure all UART RX pins configured by ROM code */ stm32mp1_deconfigure_uart_pins(); #endif @@ -338,6 +348,10 @@ skip_console_init: if (dt_pmic_status() > 0) { initialize_pmic(); + if (pmic_voltages_init() != 0) { + ERROR("PMIC voltages init failed\n"); + panic(); + } print_pmic_info_and_debug(); } @@ -359,6 +373,7 @@ skip_console_init: } } +#if STM32MP15 if (stm32mp_is_auth_supported()) { stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; @@ -367,12 +382,15 @@ skip_console_init: stm32mp_init_auth(&stm32mp1_auth_ops); } +#endif stm32mp1_arch_security_setup(); print_reset_reason(); +#if STM32MP15 update_monotonic_counter(); +#endif stm32mp1_syscfg_enable_io_compensation_finish(); diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h index 198ffa9bb..763841823 100644 --- a/plat/st/stm32mp1/include/boot_api.h +++ b/plat/st/stm32mp1/include/boot_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,12 +13,22 @@ /* * Possible value of boot context field 'auth_status' */ +#if STM32MP13 + /* No authentication done */ +#define BOOT_API_CTX_AUTH_NO 0x7CFDD351U + /* Authentication done and failed */ +#define BOOT_API_CTX_AUTH_FAILED 0x51330884U + /* Authentication done and success */ +#define BOOT_API_CTX_AUTH_SUCCESS 0x67E8CAE1U +#endif +#if STM32MP15 /* No authentication done */ #define BOOT_API_CTX_AUTH_NO 0x0U /* Authentication done and failed */ #define BOOT_API_CTX_AUTH_FAILED 0x1U /* Authentication done and succeeded */ #define BOOT_API_CTX_AUTH_SUCCESS 0x2U +#endif /* * Possible value of boot context field 'boot_interface_sel' @@ -70,11 +80,17 @@ #define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_NOT_FOUND 0x5U #define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_SIZE_ZERO 0x6U #define BOOT_API_CTX_EMMC_ERROR_STATUS_IMAGE_NOT_COMPLETE 0x7U +#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_ERROR 0x8U /* Image Header related definitions */ /* Definition of header version */ +#if STM32MP13 +#define BOOT_API_HEADER_VERSION 0x00020000U +#endif +#if STM32MP15 #define BOOT_API_HEADER_VERSION 0x00010000U +#endif /* * Magic number used to detect header in memory @@ -93,6 +109,49 @@ #define BOOT_API_ECDSA_ALGO_TYPE_P256NIST 1 #define BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256 2 +/* + * Extension headers related definitions + */ +/* 'bootapi_image_header_t.extension_flag' used for authentication feature */ +#define BOOT_API_AUTHENTICATION_EXTENSION_BIT BIT(0) +/* 'bootapi_image_header_t.extension_flag' used for FSBL decryption feature */ +#define BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT BIT(1) +/* 'bootapi_image_header_t.extension_flag' used for padding header feature */ +#define BOOT_API_PADDING_EXTENSION_BIT BIT(31) +/* + * mask of bits of field 'bootapi_image_header_t.extension_flag' + * used for extension headers + */ +#define BOOT_API_ALL_EXTENSIONS_MASK \ + (BOOT_API_AUTHENTICATION_EXTENSION_BIT | \ + BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT | \ + BOOT_API_PADDING_EXTENSION_BIT) +/* + * Magic number of FSBL decryption extension header + * The value shall gives the four bytes 'S','T',0x00,0x01 in memory + */ +#define BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB 0x01005453U + +/* + * Magic number of PKH revocation extension header + * The value shall gives the four bytes 'S','T',0x00,0x02 in memory + */ +#define BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB 0x02005453U + +/* Max number of ECDSA public key hash in table */ +#define BOOT_API_AUTHENTICATION_NB_PKH_MAX 8U + +/* ECDSA public key hash table size in bytes */ +#define BOOT_API_AUTHENTICATION_TABLE_SIZE_BYTES \ + (BOOT_API_AUTHENTICATION_NB_PKH_MAX * \ + BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES) + +/* + * Magic number of padding extension header + * The value shall gives the four bytes 'S','T',0xFF,0xFF in memory + */ +#define BOOT_API_PADDING_HEADER_MAGIC_NB 0xFFFF5453U + /* * Cores secure magic numbers * Constant to be stored in bakcup register @@ -157,11 +216,20 @@ typedef struct { */ uint16_t boot_interface_selected; uint16_t boot_interface_instance; +#if STM32MP13 + uint32_t reserved1[12]; +#endif +#if STM32MP15 uint32_t reserved1[13]; +#endif uint32_t otp_afmux_values[3]; - uint32_t reserved[5]; + uint32_t reserved[3]; +#if STM32MP15 + uint32_t reserved2[2]; +#endif uint32_t auth_status; +#if STM32MP15 /* * Pointers to bootROM External Secure Services * - ECDSA check key @@ -179,7 +247,7 @@ typedef struct { uint8_t *signature, uint32_t ecc_algo, uint32_t *entry_in); - +#endif /* * Information specific to an SD boot * Updated each time an SD boot is at least attempted, @@ -227,10 +295,10 @@ typedef struct { uint8_t image_signature[BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES]; /* * Checksum of payload - * 32-bit sum all all payload bytes considered as 8 bit unigned numbers, - * discarding any overflow bits. + * 32-bit sum all payload bytes considered as 8 bit unsigned + * numbers, discarding any overflow bits. * Use to check UART/USB downloaded image integrity when signature - * is not used (i.e bit 0 : 'No_sig_check' = 1 in option flags) + * is not used */ uint32_t payload_checksum; /* Image header version : should have value BOOT_API_HEADER_VERSION */ @@ -255,6 +323,25 @@ typedef struct { * counter value in OTP_CFG4 prior executing the downloaded image */ uint32_t image_version; + +#if STM32MP13 + /* + * Extension flags : + * + * Bit 0 : Authentication extension header + * value 0 : No signature check request + * Bit 1 : Encryption extension header + * Bit 2 : Padding extension header + */ + uint32_t extension_flags; + /* Length in bytes of all extension headers */ + uint32_t extension_headers_length; + /* Add binary type information */ + uint32_t binary_type; + /* Pad up to 128 byte total size */ + uint8_t pad[16]; +#endif +#if STM32MP15 /* * Option flags: * Bit 0 : No signature check request : 'No_sig_check' @@ -280,6 +367,7 @@ typedef struct { uint8_t pad[83]; /* Add binary type information */ uint8_t binary_type; +#endif } __packed boot_api_image_header_t; #endif /* BOOT_API_H */ diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h index 38de1b715..23934e92f 100644 --- a/plat/st/stm32mp1/include/stm32mp1_private.h +++ b/plat/st/stm32mp1/include/stm32mp1_private.h @@ -21,6 +21,16 @@ void stm32mp1_syscfg_init(void); void stm32mp1_syscfg_enable_io_compensation_start(void); void stm32mp1_syscfg_enable_io_compensation_finish(void); void stm32mp1_syscfg_disable_io_compensation(void); +uint32_t stm32mp1_syscfg_get_chip_version(void); +uint32_t stm32mp1_syscfg_get_chip_dev_id(void); +#if STM32MP13 +void stm32mp1_syscfg_boot_mode_enable(void); +void stm32mp1_syscfg_boot_mode_disable(void); +#endif +#if STM32MP15 +static inline void stm32mp1_syscfg_boot_mode_enable(void){} +static inline void stm32mp1_syscfg_boot_mode_disable(void){} +#endif void stm32mp1_deconfigure_uart_pins(void); diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index a4c40c4c4..9e732d6b7 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -24,10 +24,52 @@ STM32_TF_VERSION ?= 0 # Enable dynamic memory mapping PLAT_XLAT_TABLES_DYNAMIC := 1 +# Default Device tree +DTB_FILE_NAME ?= stm32mp157c-ev1.dtb + +STM32MP13 ?= 0 +STM32MP15 ?= 0 + +ifeq ($(STM32MP13),1) +ifeq ($(STM32MP15),1) +$(error Cannot enable both flags STM32MP13 and STM32MP15) +endif +STM32MP13 := 1 +STM32MP15 := 0 +else ifeq ($(STM32MP15),1) +STM32MP13 := 0 +STM32MP15 := 1 +else ifneq ($(findstring stm32mp13,$(DTB_FILE_NAME)),) +STM32MP13 := 1 +STM32MP15 := 0 +else ifneq ($(findstring stm32mp15,$(DTB_FILE_NAME)),) +STM32MP13 := 0 +STM32MP15 := 1 +endif + +ifeq ($(STM32MP13),1) +# DDR controller with single AXI port and 16-bit interface +STM32MP_DDR_DUAL_AXI_PORT:= 0 +STM32MP_DDR_32BIT_INTERFACE:= 0 + +# STM32 image header version v2.0 +STM32_HEADER_VERSION_MAJOR:= 2 +STM32_HEADER_VERSION_MINOR:= 0 +endif + +ifeq ($(STM32MP15),1) # DDR controller with dual AXI port and 32-bit interface STM32MP_DDR_DUAL_AXI_PORT:= 1 STM32MP_DDR_32BIT_INTERFACE:= 1 +# STM32 image header version v1.0 +STM32_HEADER_VERSION_MAJOR:= 1 +STM32_HEADER_VERSION_MINOR:= 0 +endif + +# STM32 image header binary type for BL2 +STM32_HEADER_BL2_BINARY_TYPE:= 0x10 + ifeq ($(AARCH32_SP),sp_min) # Disable Neon support: sp_min runtime may conflict with non-secure world TF_CFLAGS += -mfloat-abi=soft @@ -82,7 +124,10 @@ STM32MP_USB_PROGRAMMER ?= 0 STM32MP_UART_PROGRAMMER ?= 0 # Device tree -DTB_FILE_NAME ?= stm32mp157c-ev1.dtb +ifeq ($(STM32MP13),1) +BL2_DTSI := stm32mp13-bl2.dtsi +FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) +else ifeq ($(STM32MP_USE_STM32IMAGE),1) ifeq ($(AARCH32_SP),optee) BL2_DTSI := stm32mp15-bl2.dtsi @@ -98,6 +143,7 @@ BL32_DTSI := stm32mp15-bl32.dtsi FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME))) endif endif +endif $(eval DTC_V = $(shell $(DTC) -v | awk '{print $$NF}')) $(eval DTC_VERSION = $(shell printf "%d" $(shell echo ${DTC_V} | cut -d- -f1 | sed "s/\./0/g"))) @@ -167,6 +213,8 @@ $(eval $(call assert_booleans,\ STM32MP_UART_PROGRAMMER \ STM32MP_USB_PROGRAMMER \ STM32MP_USE_STM32IMAGE \ + STM32MP13 \ + STM32MP15 \ ))) $(eval $(call assert_numerics,\ @@ -196,6 +244,8 @@ $(eval $(call add_defines,\ STM32MP_UART_PROGRAMMER \ STM32MP_USB_PROGRAMMER \ STM32MP_USE_STM32IMAGE \ + STM32MP13 \ + STM32MP15 \ ))) # Include paths and source files @@ -230,7 +280,6 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/st/bsec/bsec2.c \ drivers/st/clk/stm32mp_clkfunc.c \ - drivers/st/clk/stm32mp1_clk.c \ drivers/st/ddr/stm32mp_ddr.c \ drivers/st/ddr/stm32mp1_ddr_helpers.c \ drivers/st/gpio/stm32_gpio.c \ @@ -246,6 +295,13 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \ plat/st/stm32mp1/stm32mp1_helper.S \ plat/st/stm32mp1/stm32mp1_syscfg.c +ifeq ($(STM32MP13),1) +PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ + drivers/st/clk/clk-stm32mp13.c +else +PLAT_BL_COMMON_SOURCES += drivers/st/clk/stm32mp1_clk.c +endif + ifneq (${STM32MP_USE_STM32IMAGE},1) BL2_SOURCES += ${FCONF_SOURCES} ${FCONF_DYN_SOURCES} @@ -275,9 +331,13 @@ BL2_SOURCES += drivers/io/io_block.c \ drivers/io/io_mtd.c \ drivers/io/io_storage.c \ drivers/st/crypto/stm32_hash.c \ - plat/st/common/stm32mp_auth.c \ plat/st/stm32mp1/bl2_plat_setup.c + +ifeq ($(STM32MP15),1) +BL2_SOURCES += plat/st/common/stm32mp_auth.c +endif + ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) BL2_SOURCES += drivers/mmc/mmc.c \ drivers/partition/gpt.c \ @@ -427,5 +487,8 @@ tf-a-%.stm32: ${STM32IMAGE} tf-a-%.bin $(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}')) ${Q}${STM32IMAGE} -s $(word 2,$^) -d $@ \ -l $(LOADADDR) -e ${ENTRY} \ - -v ${STM32_TF_VERSION} + -v ${STM32_TF_VERSION} \ + -m ${STM32_HEADER_VERSION_MAJOR} \ + -n ${STM32_HEADER_VERSION_MINOR} \ + -b ${STM32_HEADER_BL2_BINARY_TYPE} @echo diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk index b506e9527..c3fc2cb39 100644 --- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk +++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk @@ -4,6 +4,10 @@ # SPDX-License-Identifier: BSD-3-Clause # +ifeq ($(STM32MP13),1) +$(error "SP_min is not supported on STM32MP13 platform") +endif + SP_MIN_WITH_SECURE_FIQ := 1 ifneq ($(STM32MP_USE_STM32IMAGE),1) diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 801b9474a..d8699784f 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -36,6 +36,23 @@ /******************************************************************************* * CHIP ID ******************************************************************************/ +#if STM32MP13 +#define STM32MP1_CHIP_ID U(0x501) + +#define STM32MP135C_PART_NB U(0x05010000) +#define STM32MP135A_PART_NB U(0x05010001) +#define STM32MP133C_PART_NB U(0x050100C0) +#define STM32MP133A_PART_NB U(0x050100C1) +#define STM32MP131C_PART_NB U(0x050106C8) +#define STM32MP131A_PART_NB U(0x050106C9) +#define STM32MP135F_PART_NB U(0x05010800) +#define STM32MP135D_PART_NB U(0x05010801) +#define STM32MP133F_PART_NB U(0x050108C0) +#define STM32MP133D_PART_NB U(0x050108C1) +#define STM32MP131F_PART_NB U(0x05010EC8) +#define STM32MP131D_PART_NB U(0x05010EC9) +#endif +#if STM32MP15 #define STM32MP1_CHIP_ID U(0x500) #define STM32MP157C_PART_NB U(0x05000000) @@ -50,17 +67,25 @@ #define STM32MP153D_PART_NB U(0x050000A5) #define STM32MP151F_PART_NB U(0x050000AE) #define STM32MP151D_PART_NB U(0x050000AF) +#endif #define STM32MP1_REV_B U(0x2000) +#if STM32MP13 +#define STM32MP1_REV_Z U(0x1001) +#endif +#if STM32MP15 #define STM32MP1_REV_Z U(0x2001) +#endif /******************************************************************************* * PACKAGE ID ******************************************************************************/ +#if STM32MP15 #define PKG_AA_LFBGA448 U(4) #define PKG_AB_LFBGA354 U(3) #define PKG_AC_TFBGA361 U(2) #define PKG_AD_TFBGA257 U(1) +#endif /******************************************************************************* * STM32MP1 memory map related constants @@ -69,8 +94,22 @@ #define STM32MP_ROM_SIZE U(0x00020000) #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000) +#if STM32MP13 +#define STM32MP_SYSRAM_BASE U(0x2FFE0000) +#define STM32MP_SYSRAM_SIZE U(0x00020000) +#define SRAM1_BASE U(0x30000000) +#define SRAM1_SIZE U(0x00004000) +#define SRAM2_BASE U(0x30004000) +#define SRAM2_SIZE U(0x00002000) +#define SRAM3_BASE U(0x30006000) +#define SRAM3_SIZE U(0x00002000) +#define SRAMS_BASE SRAM1_BASE +#define SRAMS_SIZE_2MB_ALIGNED U(0x00200000) +#endif /* STM32MP13 */ +#if STM32MP15 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) #define STM32MP_SYSRAM_SIZE U(0x00040000) +#endif /* STM32MP15 */ #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ @@ -98,6 +137,15 @@ enum ddr_type { #endif /* Section used inside TF binaries */ +#if STM32MP13 +/* 512 Octets reserved for header */ +#define STM32MP_HEADER_RESERVED_SIZE U(0x200) + +#define STM32MP_BINARY_BASE STM32MP_SEC_SYSRAM_BASE + +#define STM32MP_BINARY_SIZE STM32MP_SEC_SYSRAM_SIZE +#endif +#if STM32MP15 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ /* 256 Octets reserved for header */ #define STM32MP_HEADER_SIZE U(0x00000100) @@ -111,6 +159,7 @@ enum ddr_type { #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ (STM32MP_PARAM_LOAD_SIZE + \ STM32MP_HEADER_SIZE)) +#endif /* BL2 and BL32/sp_min require finer granularity tables */ #if defined(IMAGE_BL2) @@ -170,9 +219,11 @@ enum ddr_type { #define GPIOG_BASE U(0x50008000) #define GPIOH_BASE U(0x50009000) #define GPIOI_BASE U(0x5000A000) +#if STM32MP15 #define GPIOJ_BASE U(0x5000B000) #define GPIOK_BASE U(0x5000C000) #define GPIOZ_BASE U(0x54004000) +#endif #define GPIO_BANK_OFFSET U(0x1000) /* Bank IDs used in GPIO driver API */ @@ -185,11 +236,13 @@ enum ddr_type { #define GPIO_BANK_G U(6) #define GPIO_BANK_H U(7) #define GPIO_BANK_I U(8) +#if STM32MP15 #define GPIO_BANK_J U(9) #define GPIO_BANK_K U(10) #define GPIO_BANK_Z U(25) #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 +#endif /******************************************************************************* * STM32MP1 UART @@ -205,6 +258,18 @@ enum ddr_type { /* For UART crash console */ #define STM32MP_DEBUG_USART_BASE UART4_BASE +#if STM32MP13 +/* UART4 on HSI@64MHz, TX on GPIOF12 Alternate 8 (Disco board) */ +#define STM32MP_DEBUG_USART_CLK_FRQ 64000000 +#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOD_BASE +#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_S_AHB4ENSETR +#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_S_AHB4ENSETR_GPIODEN +#define DEBUG_UART_TX_GPIO_PORT 6 +#define DEBUG_UART_TX_GPIO_ALTERNATE 8 +#define DEBUG_UART_TX_CLKSRC_REG RCC_UART4CKSELR +#define DEBUG_UART_TX_CLKSRC RCC_UART4CKSELR_HSI +#endif /* STM32MP13 */ +#if STM32MP15 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE @@ -214,6 +279,7 @@ enum ddr_type { #define DEBUG_UART_TX_GPIO_ALTERNATE 6 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI +#endif /* STM32MP15 */ #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN #define DEBUG_UART_RST_REG RCC_APB1RSTSETR @@ -322,8 +388,13 @@ enum ddr_type { ******************************************************************************/ #define STM32MP1_TZC_BASE U(0x5C006000) +#if STM32MP13 +#define STM32MP1_FILTER_BIT_ALL TZC_400_REGION_ATTR_FILTER_BIT(0) +#endif +#if STM32MP15 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ TZC_400_REGION_ATTR_FILTER_BIT(1)) +#endif /******************************************************************************* * STM32MP1 SDMMC @@ -349,7 +420,9 @@ enum ddr_type { /* OTP labels */ #define CFG0_OTP "cfg0_otp" #define PART_NUMBER_OTP "part_number_otp" +#if STM32MP15 #define PACKAGE_OTP "package_otp" +#endif #define HW2_OTP "hw2_otp" #define NAND_OTP "nand_otp" #define MONOTONIC_OTP "monotonic_otp" @@ -358,15 +431,32 @@ enum ddr_type { /* OTP mask */ /* CFG0 */ +#if STM32MP13 +#define CFG0_OTP_MODE_MASK GENMASK_32(9, 0) +#define CFG0_OTP_MODE_SHIFT 0 +#define CFG0_OPEN_DEVICE 0x17U +#define CFG0_CLOSED_DEVICE 0x3FU +#define CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN 0x17FU +#define CFG0_CLOSED_DEVICE_NO_JTAG 0x3FFU +#endif +#if STM32MP15 #define CFG0_CLOSED_DEVICE BIT(6) +#endif /* PART NUMBER */ +#if STM32MP13 +#define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0) +#endif +#if STM32MP15 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) +#endif #define PART_NUMBER_OTP_PART_SHIFT 0 /* PACKAGE */ +#if STM32MP15 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) #define PACKAGE_OTP_PKG_SHIFT 27 +#endif /* IWDG OTP */ #define HW2_OTP_IWDG_HW_POS U(3) @@ -463,34 +553,84 @@ static inline uintptr_t tamp_bkpr(uint32_t idx) * Miscellaneous STM32MP1 peripherals base address ******************************************************************************/ #define BSEC_BASE U(0x5C005000) +#if STM32MP13 +#define CRYP_BASE U(0x54002000) +#endif +#if STM32MP15 #define CRYP1_BASE U(0x54001000) +#endif #define DBGMCU_BASE U(0x50081000) +#if STM32MP13 +#define HASH_BASE U(0x54003000) +#endif +#if STM32MP15 #define HASH1_BASE U(0x54002000) +#endif +#if STM32MP13 +#define I2C3_BASE U(0x4C004000) +#define I2C4_BASE U(0x4C005000) +#define I2C5_BASE U(0x4C006000) +#endif +#if STM32MP15 #define I2C4_BASE U(0x5C002000) #define I2C6_BASE U(0x5c009000) +#endif +#if STM32MP13 +#define RNG_BASE U(0x54004000) +#endif +#if STM32MP15 #define RNG1_BASE U(0x54003000) +#endif #define RTC_BASE U(0x5c004000) +#if STM32MP13 +#define SPI4_BASE U(0x4C002000) +#define SPI5_BASE U(0x4C003000) +#endif +#if STM32MP15 #define SPI6_BASE U(0x5c001000) +#endif #define STGEN_BASE U(0x5c008000) #define SYSCFG_BASE U(0x50020000) +/******************************************************************************* + * STM32MP13 SAES + ******************************************************************************/ +#define SAES_BASE U(0x54005000) + +/******************************************************************************* + * STM32MP13 PKA + ******************************************************************************/ +#define PKA_BASE U(0x54006000) + /******************************************************************************* * REGULATORS ******************************************************************************/ /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ #define PLAT_NB_RDEVS U(19) -/* 1 FIXED */ -#define PLAT_NB_FIXED_REGS U(1) +/* 2 FIXED */ +#define PLAT_NB_FIXED_REGS U(2) /******************************************************************************* * Device Tree defines ******************************************************************************/ #define DT_BSEC_COMPAT "st,stm32mp15-bsec" +#if STM32MP13 +#define DT_DDR_COMPAT "st,stm32mp13-ddr" +#endif +#if STM32MP15 #define DT_DDR_COMPAT "st,stm32mp1-ddr" +#endif #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" #define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout" #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" +#if STM32MP13 +#define DT_RCC_CLK_COMPAT "st,stm32mp13-rcc" +#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp13-rcc-secure" +#endif +#if STM32MP15 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure" +#endif +#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" #endif /* STM32MP1_DEF_H */ diff --git a/plat/st/stm32mp1/stm32mp1_fconf_firewall.c b/plat/st/stm32mp1/stm32mp1_fconf_firewall.c index a1969eb08..f2568ab5a 100644 --- a/plat/st/stm32mp1/stm32mp1_fconf_firewall.c +++ b/plat/st/stm32mp1/stm32mp1_fconf_firewall.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,8 +31,13 @@ struct dt_id_attr { void stm32mp1_arch_security_setup(void) { +#if STM32MP13 + clk_enable(TZC); +#endif +#if STM32MP15 clk_enable(TZC1); clk_enable(TZC2); +#endif tzc400_init(STM32MP1_TZC_BASE); tzc400_disable_filters(); diff --git a/plat/st/stm32mp1/stm32mp1_fip_def.h b/plat/st/stm32mp1/stm32mp1_fip_def.h index 41972e4f8..7a277fdcb 100644 --- a/plat/st/stm32mp1/stm32mp1_fip_def.h +++ b/plat/st/stm32mp1/stm32mp1_fip_def.h @@ -10,29 +10,51 @@ #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ +#if STM32MP13 +#define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */ +#define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */ +#define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */ +#endif /* STM32MP13 */ +#if STM32MP15 #define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */ #define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */ #define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */ +#endif /* STM32MP15 */ #define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */ #define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */ #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */ +#if STM32MP13 +#define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \ + STM32MP_BL2_DTB_SIZE) +#endif /* STM32MP13 */ +#if STM32MP15 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ STM32MP_SEC_SYSRAM_SIZE - \ STM32MP_BL2_SIZE) +#endif /* STM32MP15 */ #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ STM32MP_BL2_RO_SIZE) +#if STM32MP13 +#define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ + STM32MP_SYSRAM_SIZE - \ + STM32MP_BL2_RW_BASE) + +#define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE +#endif /* STM32MP13 */ +#if STM32MP15 #define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \ STM32MP_SEC_SYSRAM_SIZE - \ STM32MP_BL2_RW_BASE) #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ STM32MP_BL2_DTB_SIZE) +#endif /* STM32MP15 */ #define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE @@ -56,9 +78,14 @@ STM32MP_OPTEE_BASE) #endif +#if STM32MP13 +#define STM32MP_FW_CONFIG_BASE SRAM3_BASE +#endif /* STM32MP13 */ +#if STM32MP15 #define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \ STM32MP_SYSRAM_SIZE - \ PAGE_SIZE) +#endif /* STM32MP15 */ #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ STM32MP_BL33_MAX_SIZE) diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index 1125a69e0..a9b9f4c5a 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -37,7 +37,12 @@ BOARD_ID_VARFG_SHIFT) #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) +#if STM32MP13 +#define TAMP_BOOT_MODE_BACKUP_REG_ID U(30) +#endif +#if STM32MP15 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) +#endif #define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00) #define TAMP_BOOT_MODE_ITF_SHIFT 8 @@ -67,6 +72,15 @@ MT_EXECUTE_NEVER) #endif +#if STM32MP13 +#define MAP_SRAM_ALL MAP_REGION_FLAT(SRAMS_BASE, \ + SRAMS_SIZE_2MB_ALIGNED, \ + MT_MEMORY | \ + MT_RW | \ + MT_SECURE | \ + MT_EXECUTE_NEVER) +#endif + #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ STM32MP1_DEVICE1_SIZE, \ MT_DEVICE | \ @@ -84,6 +98,9 @@ #if defined(IMAGE_BL2) static const mmap_region_t stm32mp1_mmap[] = { MAP_SEC_SYSRAM, +#if STM32MP13 + MAP_SRAM_ALL, +#endif MAP_DEVICE1, #if STM32MP_RAW_NAND MAP_DEVICE2, @@ -111,42 +128,62 @@ void configure_mmu(void) uintptr_t stm32_get_gpio_bank_base(unsigned int bank) { +#if STM32MP13 + assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); +#endif +#if STM32MP15 if (bank == GPIO_BANK_Z) { return GPIOZ_BASE; } assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); +#endif return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); } uint32_t stm32_get_gpio_bank_offset(unsigned int bank) { +#if STM32MP13 + assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); +#endif +#if STM32MP15 if (bank == GPIO_BANK_Z) { return 0; } assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); +#endif return bank * GPIO_BANK_OFFSET; } bool stm32_gpio_is_secure_at_reset(unsigned int bank) { +#if STM32MP13 + return true; +#endif +#if STM32MP15 if (bank == GPIO_BANK_Z) { return true; } return false; +#endif } unsigned long stm32_get_gpio_bank_clock(unsigned int bank) { +#if STM32MP13 + assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); +#endif +#if STM32MP15 if (bank == GPIO_BANK_Z) { return GPIOZ; } assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); +#endif return GPIOA + (bank - GPIO_BANK_A); } @@ -163,11 +200,15 @@ int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) case GPIO_BANK_G: case GPIO_BANK_H: case GPIO_BANK_I: +#if STM32MP15 case GPIO_BANK_J: case GPIO_BANK_K: +#endif return fdt_path_offset(fdt, "/soc/pin-controller"); +#if STM32MP15 case GPIO_BANK_Z: return fdt_path_offset(fdt, "/soc/pin-controller-z"); +#endif default: panic(); } @@ -248,6 +289,10 @@ void stm32mp1_deconfigure_uart_pins(void) uint32_t stm32mp_get_chip_version(void) { +#if STM32MP13 + return stm32mp1_syscfg_get_chip_version(); +#endif +#if STM32MP15 uint32_t version = 0U; if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { @@ -256,10 +301,15 @@ uint32_t stm32mp_get_chip_version(void) } return version; +#endif } uint32_t stm32mp_get_chip_dev_id(void) { +#if STM32MP13 + return stm32mp1_syscfg_get_chip_dev_id(); +#endif +#if STM32MP15 uint32_t dev_id; if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { @@ -268,6 +318,7 @@ uint32_t stm32mp_get_chip_dev_id(void) } return dev_id; +#endif } static uint32_t get_part_number(void) @@ -290,6 +341,7 @@ static uint32_t get_part_number(void) return part_number; } +#if STM32MP15 static uint32_t get_cpu_package(void) { uint32_t package; @@ -303,6 +355,7 @@ static uint32_t get_cpu_package(void) return package; } +#endif void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) { @@ -310,6 +363,45 @@ void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) /* MPUs Part Numbers */ switch (get_part_number()) { +#if STM32MP13 + case STM32MP135F_PART_NB: + cpu_s = "135F"; + break; + case STM32MP135D_PART_NB: + cpu_s = "135D"; + break; + case STM32MP135C_PART_NB: + cpu_s = "135C"; + break; + case STM32MP135A_PART_NB: + cpu_s = "135A"; + break; + case STM32MP133F_PART_NB: + cpu_s = "133F"; + break; + case STM32MP133D_PART_NB: + cpu_s = "133D"; + break; + case STM32MP133C_PART_NB: + cpu_s = "133C"; + break; + case STM32MP133A_PART_NB: + cpu_s = "133A"; + break; + case STM32MP131F_PART_NB: + cpu_s = "131F"; + break; + case STM32MP131D_PART_NB: + cpu_s = "131D"; + break; + case STM32MP131C_PART_NB: + cpu_s = "131C"; + break; + case STM32MP131A_PART_NB: + cpu_s = "131A"; + break; +#endif +#if STM32MP15 case STM32MP157C_PART_NB: cpu_s = "157C"; break; @@ -346,12 +438,18 @@ void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) case STM32MP151D_PART_NB: cpu_s = "151D"; break; +#endif default: cpu_s = "????"; break; } /* Package */ +#if STM32MP13 + /* On STM32MP13, package is not present in OTP */ + pkg = ""; +#endif +#if STM32MP15 switch (get_cpu_package()) { case PKG_AA_LFBGA448: pkg = "AA"; @@ -369,6 +467,7 @@ void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) pkg = "??"; break; } +#endif /* REVISION */ switch (stm32mp_get_chip_version()) { @@ -420,6 +519,10 @@ void stm32mp_print_boardinfo(void) /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ bool stm32mp_is_single_core(void) { +#if STM32MP13 + return true; +#endif +#if STM32MP15 bool single_core = false; switch (get_part_number()) { @@ -434,6 +537,7 @@ bool stm32mp_is_single_core(void) } return single_core; +#endif } /* Return true when device is in closed state */ @@ -445,7 +549,23 @@ bool stm32mp_is_closed_device(void) return true; } +#if STM32MP13 + value = (value & CFG0_OTP_MODE_MASK) >> CFG0_OTP_MODE_SHIFT; + + switch (value) { + case CFG0_OPEN_DEVICE: + return false; + case CFG0_CLOSED_DEVICE: + case CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN: + case CFG0_CLOSED_DEVICE_NO_JTAG: + return true; + default: + panic(); + } +#endif +#if STM32MP15 return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE; +#endif } /* Return true when device supports secure boot */ @@ -454,12 +574,22 @@ bool stm32mp_is_auth_supported(void) bool supported = false; switch (get_part_number()) { +#if STM32MP13 + case STM32MP131C_PART_NB: + case STM32MP131F_PART_NB: + case STM32MP133C_PART_NB: + case STM32MP133F_PART_NB: + case STM32MP135C_PART_NB: + case STM32MP135F_PART_NB: +#endif +#if STM32MP15 case STM32MP151C_PART_NB: case STM32MP151F_PART_NB: case STM32MP153C_PART_NB: case STM32MP153F_PART_NB: case STM32MP157C_PART_NB: case STM32MP157F_PART_NB: +#endif supported = true; break; default: diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c index 3f34af15b..ff79428a6 100644 --- a/plat/st/stm32mp1/stm32mp1_syscfg.c +++ b/plat/st/stm32mp1/stm32mp1_syscfg.c @@ -4,11 +4,16 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include +#include + #include #include #include #include #include +#include +#include #include #include @@ -19,11 +24,24 @@ * SYSCFG REGISTER OFFSET (base relative) */ #define SYSCFG_BOOTR 0x00U +#define SYSCFG_BOOTCR 0x0CU +#if STM32MP15 #define SYSCFG_IOCTRLSETR 0x18U #define SYSCFG_ICNR 0x1CU +#endif #define SYSCFG_CMPCR 0x20U #define SYSCFG_CMPENSETR 0x24U #define SYSCFG_CMPENCLRR 0x28U +#if STM32MP13 +#define SYSCFG_CMPSD1CR 0x30U +#define SYSCFG_CMPSD1ENSETR 0x34U +#define SYSCFG_CMPSD1ENCLRR 0x38U +#define SYSCFG_CMPSD2CR 0x40U +#define SYSCFG_CMPSD2ENSETR 0x44U +#define SYSCFG_CMPSD2ENCLRR 0x48U +#define SYSCFG_HSLVEN0R 0x50U +#endif +#define SYSCFG_IDC 0x380U #define CMPCR_CMPENSETR_OFFSET 0x4U #define CMPCR_CMPENCLRR_OFFSET 0x8U @@ -32,8 +50,16 @@ * SYSCFG_BOOTR Register */ #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) +#if STM32MP15 #define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4) #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 +#endif + +/* + * SYSCFG_BOOTCR Register + */ +#define SYSCFG_BOOTCR_BMEN BIT(0) + /* * SYSCFG_IOCTRLSETR Register */ @@ -65,6 +91,32 @@ */ #define SYSCFG_CMPENSETR_MPU_EN BIT(0) +/* + * HSLV definitions + */ +#define HSLV_IDX_TPIU 0U +#define HSLV_IDX_QSPI 1U +#define HSLV_IDX_ETH1 2U +#define HSLV_IDX_ETH2 3U +#define HSLV_IDX_SDMMC1 4U +#define HSLV_IDX_SDMMC2 5U +#define HSLV_IDX_SPI1 6U +#define HSLV_IDX_SPI2 7U +#define HSLV_IDX_SPI3 8U +#define HSLV_IDX_SPI4 9U +#define HSLV_IDX_SPI5 10U +#define HSLV_IDX_LTDC 11U +#define HSLV_NB_IDX 12U + +#define HSLV_KEY 0x1018U + +/* + * SYSCFG_IDC Register + */ +#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_IDC_REV_ID_SHIFT 16 + static void enable_io_comp_cell_finish(uintptr_t cmpcr_off) { uint64_t start; @@ -104,14 +156,107 @@ static void disable_io_comp_cell(uintptr_t cmpcr_off) mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN); } +#if STM32MP13 +static int get_regu_max_voltage(void *fdt, int sdmmc_node, + const char *regu_name, uint32_t *regu_val) +{ + int node; + const fdt32_t *cuint; + + cuint = fdt_getprop(fdt, sdmmc_node, regu_name, NULL); + if (cuint == NULL) { + return -ENODEV; + } + + node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); + if (node < 0) { + return -ENODEV; + } + + cuint = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL); + if (cuint == NULL) { + return -ENODEV; + } + + *regu_val = fdt32_to_cpu(*cuint); + + return 0; +} + +static bool sdmmc_is_low_voltage(uintptr_t sdmmc_base) +{ + int ret; + int node; + void *fdt = NULL; + uint32_t regu_max_val; + + if (fdt_get_address(&fdt) == 0) { + return false; + } + + if (fdt == NULL) { + return false; + } + + node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT, sdmmc_base); + if (node < 0) { + /* No SD or eMMC device on this instance, enable HSLV */ + return true; + } + + ret = get_regu_max_voltage(fdt, node, "vqmmc-supply", ®u_max_val); + if ((ret < 0) || (regu_max_val > 1800000U)) { + /* + * The vqmmc-supply property should always be present for eMMC. + * For SD-card, if it is not, then the card only supports 3.3V. + */ + return false; + } + + return true; +} + +static void enable_hslv_by_index(uint32_t index) +{ + bool apply_hslv; + + assert(index < HSLV_NB_IDX); + + switch (index) { + case HSLV_IDX_SDMMC1: + apply_hslv = sdmmc_is_low_voltage(STM32MP_SDMMC1_BASE); + break; + case HSLV_IDX_SDMMC2: + apply_hslv = sdmmc_is_low_voltage(STM32MP_SDMMC2_BASE); + break; + default: + apply_hslv = true; + break; + } + + if (apply_hslv) { + mmio_write_32(SYSCFG_BASE + SYSCFG_HSLVEN0R + index * sizeof(uint32_t), HSLV_KEY); + } +} +#endif + static void enable_high_speed_mode_low_voltage(void) { +#if STM32MP13 + uint32_t idx; + + for (idx = 0U; idx < HSLV_NB_IDX; idx++) { + enable_hslv_by_index(idx); + } +#endif +#if STM32MP15 mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_TRACE | SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | SYSCFG_IOCTRLSETR_HSLVEN_ETH | SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | SYSCFG_IOCTRLSETR_HSLVEN_SPI); +#endif } static void stm32mp1_syscfg_set_hslv(void) @@ -165,6 +310,7 @@ static void stm32mp1_syscfg_set_hslv(void) void stm32mp1_syscfg_init(void) { +#if STM32MP15 uint32_t bootr; /* @@ -178,6 +324,7 @@ void stm32mp1_syscfg_init(void) SYSCFG_BOOTR_BOOT_MASK; mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK, bootr << SYSCFG_BOOTR_BOOTPD_SHIFT); +#endif stm32mp1_syscfg_set_hslv(); @@ -195,11 +342,22 @@ void stm32mp1_syscfg_enable_io_compensation_start(void) mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPCR, SYSCFG_CMPENSETR_MPU_EN); +#if STM32MP13 + mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPSD1CR, + SYSCFG_CMPENSETR_MPU_EN); + mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPSD2CR, + SYSCFG_CMPENSETR_MPU_EN); + +#endif } void stm32mp1_syscfg_enable_io_compensation_finish(void) { enable_io_comp_cell_finish(SYSCFG_CMPCR); +#if STM32MP13 + enable_io_comp_cell_finish(SYSCFG_CMPSD1CR); + enable_io_comp_cell_finish(SYSCFG_CMPSD2CR); +#endif } void stm32mp1_syscfg_disable_io_compensation(void) @@ -213,6 +371,41 @@ void stm32mp1_syscfg_disable_io_compensation(void) * Disable non-secure SYSCFG clock, we assume non-secure is suspended. */ disable_io_comp_cell(SYSCFG_CMPCR); +#if STM32MP13 + disable_io_comp_cell(SYSCFG_CMPSD1CR); + disable_io_comp_cell(SYSCFG_CMPSD2CR); +#endif clk_disable(SYSCFG); } + +/* + * @brief Get silicon revision from SYSCFG registers. + * @retval chip version (REV_ID). + */ +uint32_t stm32mp1_syscfg_get_chip_version(void) +{ + return (mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) & + SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT; +} + +/* + * @brief Get device ID from SYSCFG registers. + * @retval device ID (DEV_ID). + */ +uint32_t stm32mp1_syscfg_get_chip_dev_id(void) +{ + return mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) & SYSCFG_IDC_DEV_ID_MASK; +} + +#if STM32MP13 +void stm32mp1_syscfg_boot_mode_enable(void) +{ + mmio_setbits_32(SYSCFG_BASE + SYSCFG_BOOTCR, SYSCFG_BOOTCR_BMEN); +} + +void stm32mp1_syscfg_boot_mode_disable(void) +{ + mmio_clrbits_32(SYSCFG_BASE + SYSCFG_BOOTCR, SYSCFG_BOOTCR_BMEN); +} +#endif diff --git a/plat/st/stm32mp1/stm32mp1_usb_dfu.c b/plat/st/stm32mp1/stm32mp1_usb_dfu.c index 33b12d046..0fe2d24ae 100644 --- a/plat/st/stm32mp1/stm32mp1_usb_dfu.c +++ b/plat/st/stm32mp1/stm32mp1_usb_dfu.c @@ -28,7 +28,12 @@ #define USBD_CONFIGURATION_STRING "DFU Config" #define USBD_INTERFACE_STRING "DFU Interface" +#if STM32MP13 +#define USB_DFU_ITF_NUM 2 +#endif +#if STM32MP15 #define USB_DFU_ITF_NUM 6 +#endif #define USB_DFU_CONFIG_DESC_SIZ USB_DFU_DESC_SIZ(USB_DFU_ITF_NUM) @@ -98,11 +103,18 @@ static const uint8_t usb_stm32mp1_config_desc[USB_DFU_CONFIG_DESC_SIZ] = { /* Descriptor of DFU interface 0 Alternate setting 0..N */ USBD_DFU_IF_DESC(0), USBD_DFU_IF_DESC(1), +#if USB_DFU_ITF_NUM > 2 USBD_DFU_IF_DESC(2), +#endif +#if USB_DFU_ITF_NUM > 3 USBD_DFU_IF_DESC(3), +#endif +#if USB_DFU_ITF_NUM > 4 USBD_DFU_IF_DESC(4), +#endif +#if USB_DFU_ITF_NUM > 5 USBD_DFU_IF_DESC(5), - +#endif /* DFU Functional Descriptor */ 0x09, /* blength = 9 Bytes */ DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor */ @@ -115,6 +127,13 @@ static const uint8_t usb_stm32mp1_config_desc[USB_DFU_CONFIG_DESC_SIZ] = { }; /* The user strings: one by alternate as defined in USBD_DFU_IF_DESC */ +#if STM32MP13 +const char *const if_desc_string[USB_DFU_ITF_NUM] = { + "@SSBL /0x03/1*16Me", + "@virtual /0xF1/1*512Ba" +}; +#endif +#if STM32MP15 const char *const if_desc_string[USB_DFU_ITF_NUM] = { "@Partition0 /0x00/1*256Ke", "@FSBL /0x01/1*1Me", @@ -123,6 +142,7 @@ const char *const if_desc_string[USB_DFU_ITF_NUM] = { "@Partition4 /0x04/1*16Me", "@virtual /0xF1/1*512Ba" }; +#endif /* Buffer to build the unicode string provided to USB device stack */ static uint8_t usb_str_dec[USBD_MAX_STR_DESC_SIZ]; @@ -354,9 +374,11 @@ struct usb_handle *usb_dfu_plat_init(void) stm32mp1_usb_init_driver(&usb_core_handle, &pcd_handle, (uint32_t *)USB_OTG_BASE); +#if STM32MP15 /* STM32MP15 = keep the configuration from ROM code */ usb_core_handle.ep0_state = USBD_EP0_DATA_IN; usb_core_handle.dev_state = USBD_STATE_CONFIGURED; +#endif /* Update the serial number string descriptor from the unique ID */ update_serial_num_string(); @@ -376,12 +398,22 @@ uint8_t usb_dfu_get_phase(uint8_t alt) uint8_t ret; switch (alt) { +#if STM32MP13 + case 0: + ret = PHASE_SSBL; + break; + case 1: + ret = PHASE_CMD; + break; +#endif +#if STM32MP15 case 3: ret = PHASE_SSBL; break; case 5: ret = PHASE_CMD; break; +#endif default: ret = PHASE_RESET; break; diff --git a/tools/stm32image/stm32image.c b/tools/stm32image/stm32image.c index fb1dee072..bd4720c5c 100644 --- a/tools/stm32image/stm32image.c +++ b/tools/stm32image/stm32image.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,16 +22,16 @@ #define VER_MINOR 1 #define VER_VARIANT 0 #define HEADER_VERSION_V1 0x1 -#define TF_BINARY_TYPE 0x10 +#define HEADER_VERSION_V2 0x2 +#define PADDING_HEADER_MAGIC __be32_to_cpu(0x5354FFFF) +#define PADDING_HEADER_FLAG (1 << 31) +#define PADDING_HEADER_LENGTH 0x180 -/* Default option : bit0 => no signature */ -#define HEADER_DEFAULT_OPTION (__cpu_to_le32(0x00000001)) - -struct stm32_header { +struct stm32_header_v1 { uint32_t magic_number; uint8_t image_signature[64]; uint32_t image_checksum; - uint8_t header_version[4]; + uint8_t header_version[4]; uint32_t image_length; uint32_t image_entry_point; uint32_t reserved1; @@ -45,31 +45,50 @@ struct stm32_header { uint8_t binary_type; }; -static void stm32image_default_header(struct stm32_header *ptr) +struct stm32_header_v2 { + uint32_t magic_number; + uint8_t image_signature[64]; + uint32_t image_checksum; + uint8_t header_version[4]; + uint32_t image_length; + uint32_t image_entry_point; + uint32_t reserved1; + uint32_t load_address; + uint32_t reserved2; + uint32_t version_number; + uint32_t extension_flags; + uint32_t extension_headers_length; + uint32_t binary_type; + uint8_t padding[16]; + uint32_t extension_header_type; + uint32_t extension_header_length; + uint8_t extension_padding[376]; +}; + +static void stm32image_default_header(void *ptr) { - if (!ptr) { + struct stm32_header_v1 *header = (struct stm32_header_v1 *)ptr; + + if (!header) { return; } - ptr->magic_number = HEADER_MAGIC; - ptr->option_flags = HEADER_DEFAULT_OPTION; - ptr->ecdsa_algorithm = __cpu_to_le32(1); - ptr->version_number = __cpu_to_le32(0); - ptr->binary_type = TF_BINARY_TYPE; + header->magic_number = HEADER_MAGIC; + header->version_number = __cpu_to_le32(0); } -static uint32_t stm32image_checksum(void *start, uint32_t len) +static uint32_t stm32image_checksum(void *start, uint32_t len, + uint32_t header_size) { uint32_t csum = 0; - uint32_t hdr_len = sizeof(struct stm32_header); uint8_t *p; - if (len < hdr_len) { + if (len < header_size) { return 0; } - p = (unsigned char *)start + hdr_len; - len -= hdr_len; + p = (unsigned char *)start + header_size; + len -= header_size; while (len > 0) { csum += *p; @@ -82,7 +101,8 @@ static uint32_t stm32image_checksum(void *start, uint32_t len) static void stm32image_print_header(const void *ptr) { - struct stm32_header *stm32hdr = (struct stm32_header *)ptr; + struct stm32_header_v1 *stm32hdr = (struct stm32_header_v1 *)ptr; + struct stm32_header_v2 *stm32hdr_v2 = (struct stm32_header_v2 *)ptr; printf("Image Type : ST Microelectronics STM32 V%d.%d\n", stm32hdr->header_version[VER_MAJOR], @@ -95,40 +115,87 @@ static void stm32image_print_header(const void *ptr) __le32_to_cpu(stm32hdr->image_entry_point)); printf("Checksum : 0x%08x\n", __le32_to_cpu(stm32hdr->image_checksum)); - printf("Option : 0x%08x\n", - __le32_to_cpu(stm32hdr->option_flags)); - printf("Version : 0x%08x\n", + + switch (stm32hdr->header_version[VER_MAJOR]) { + case HEADER_VERSION_V1: + printf("Option : 0x%08x\n", + __le32_to_cpu(stm32hdr->option_flags)); + break; + + case HEADER_VERSION_V2: + printf("Extension : 0x%08x\n", + __le32_to_cpu(stm32hdr_v2->extension_flags)); + break; + + default: + printf("Incorrect header version\n"); + } + + printf("Version : 0x%08x\n", __le32_to_cpu(stm32hdr->version_number)); } -static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd, - uint32_t loadaddr, uint32_t ep, uint32_t ver, - uint32_t major, uint32_t minor) +static int stm32image_set_header(void *ptr, struct stat *sbuf, int ifd, + uint32_t loadaddr, uint32_t ep, uint32_t ver, + uint32_t major, uint32_t minor, + uint32_t binary_type, uint32_t header_size) { - struct stm32_header *stm32hdr = (struct stm32_header *)ptr; + struct stm32_header_v1 *stm32hdr = (struct stm32_header_v1 *)ptr; + struct stm32_header_v2 *stm32hdr_v2 = (struct stm32_header_v2 *)ptr; + uint32_t ext_size = 0U; + uint32_t ext_flags = 0U; - stm32image_default_header(stm32hdr); + stm32image_default_header(ptr); stm32hdr->header_version[VER_MAJOR] = major; stm32hdr->header_version[VER_MINOR] = minor; stm32hdr->load_address = __cpu_to_le32(loadaddr); stm32hdr->image_entry_point = __cpu_to_le32(ep); stm32hdr->image_length = __cpu_to_le32((uint32_t)sbuf->st_size - - sizeof(struct stm32_header)); + header_size); stm32hdr->image_checksum = - __cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size)); + __cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size, + header_size)); + + switch (stm32hdr->header_version[VER_MAJOR]) { + case HEADER_VERSION_V1: + /* Default option for header v1 : bit0 => no signature */ + stm32hdr->option_flags = __cpu_to_le32(0x00000001); + stm32hdr->ecdsa_algorithm = __cpu_to_le32(1); + stm32hdr->binary_type = (uint8_t)binary_type; + break; + + case HEADER_VERSION_V2: + stm32hdr_v2->binary_type = binary_type; + ext_size += PADDING_HEADER_LENGTH; + ext_flags |= PADDING_HEADER_FLAG; + stm32hdr_v2->extension_flags = + __cpu_to_le32(ext_flags); + stm32hdr_v2->extension_headers_length = + __cpu_to_le32(ext_size); + stm32hdr_v2->extension_header_type = PADDING_HEADER_MAGIC; + stm32hdr_v2->extension_header_length = + __cpu_to_le32(PADDING_HEADER_LENGTH); + break; + + default: + return -1; + } + stm32hdr->version_number = __cpu_to_le32(ver); + + return 0; } static int stm32image_create_header_file(char *srcname, char *destname, uint32_t loadaddr, uint32_t entry, uint32_t version, uint32_t major, - uint32_t minor) + uint32_t minor, uint32_t binary_type) { - int src_fd, dest_fd; + int src_fd, dest_fd, header_size; struct stat sbuf; unsigned char *ptr; - struct stm32_header stm32image_header; + void *stm32image_header; dest_fd = open(destname, O_RDWR | O_CREAT | O_TRUNC | O_APPEND, 0666); if (dest_fd == -1) { @@ -154,15 +221,32 @@ static int stm32image_create_header_file(char *srcname, char *destname, return -1; } - memset(&stm32image_header, 0, sizeof(struct stm32_header)); + switch (major) { + case HEADER_VERSION_V1: + stm32image_header = malloc(sizeof(struct stm32_header_v1)); + header_size = sizeof(struct stm32_header_v1); + break; - if (write(dest_fd, &stm32image_header, sizeof(struct stm32_header)) != - sizeof(struct stm32_header)) { - fprintf(stderr, "Write error %s: %s\n", destname, - strerror(errno)); + case HEADER_VERSION_V2: + stm32image_header = malloc(sizeof(struct stm32_header_v2)); + header_size = sizeof(struct stm32_header_v2); + break; + + default: return -1; } + memset(stm32image_header, 0, header_size); + if (write(dest_fd, stm32image_header, header_size) != + header_size) { + fprintf(stderr, "Write error %s: %s\n", destname, + strerror(errno)); + free(stm32image_header); + return -1; + } + + free(stm32image_header); + if (write(dest_fd, ptr, sbuf.st_size) != sbuf.st_size) { fprintf(stderr, "Write error on %s: %s\n", destname, strerror(errno)); @@ -184,8 +268,11 @@ static int stm32image_create_header_file(char *srcname, char *destname, return -1; } - stm32image_set_header(ptr, &sbuf, dest_fd, loadaddr, entry, version, - major, minor); + if (stm32image_set_header(ptr, &sbuf, dest_fd, loadaddr, + entry, version, major, minor, + binary_type, header_size) != 0) { + return -1; + } stm32image_print_header(ptr); @@ -196,13 +283,22 @@ static int stm32image_create_header_file(char *srcname, char *destname, int main(int argc, char *argv[]) { - int opt, loadaddr = -1, entry = -1, err = 0, version = 0; - int major = HEADER_VERSION_V1; + int opt; + int loadaddr = -1; + int entry = -1; + int err = 0; + int version = 0; + int binary_type = -1; + int major = HEADER_VERSION_V2; int minor = 0; - char *dest = NULL, *src = NULL; + char *dest = NULL; + char *src = NULL; - while ((opt = getopt(argc, argv, ":s:d:l:e:v:m:n:")) != -1) { + while ((opt = getopt(argc, argv, ":b:s:d:l:e:v:m:n:")) != -1) { switch (opt) { + case 'b': + binary_type = strtol(optarg, NULL, 0); + break; case 's': src = optarg; break; @@ -226,7 +322,7 @@ int main(int argc, char *argv[]) break; default: fprintf(stderr, - "Usage : %s [-s srcfile] [-d destfile] [-l loadaddr] [-e entry_point] [-m major] [-n minor]\n", + "Usage : %s [-s srcfile] [-d destfile] [-l loadaddr] [-e entry_point] [-m major] [-n minor] [-b binary_type]\n", argv[0]); return -1; } @@ -252,8 +348,14 @@ int main(int argc, char *argv[]) return -1; } + if (binary_type == -1) { + fprintf(stderr, "Missing -b option\n"); + return -1; + } + err = stm32image_create_header_file(src, dest, loadaddr, - entry, version, major, minor); + entry, version, major, minor, + binary_type); return err; }