Implement {spe,sve}_supported() helpers and refactor code
Implement helpers to test if the core supports SPE/SVE. We have a similar helper for AMU and this patch makes all extensions consistent in their implementation. Change-Id: I3e6f7522535ca358259ad142550b19fcb883ca67 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
This commit is contained in:
Dimitris Papastamos
parent
c7aa7fdf56
commit
2ff8fbf3b0
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,6 +7,7 @@
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#ifndef __SPE_H__
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#define __SPE_H__
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int spe_supported(void);
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void spe_enable(int el2_unused);
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void spe_disable(void);
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,6 +7,7 @@
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#ifndef __SVE_H__
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#define __SVE_H__
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int sve_supported(void);
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void sve_enable(int el2_unused);
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#endif /* __SVE_H__ */
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -14,71 +14,72 @@
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*/
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#define psb_csync() asm volatile("hint #17")
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void spe_enable(int el2_unused)
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int spe_supported(void)
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{
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uint64_t features;
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features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
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if ((features & ID_AA64DFR0_PMS_MASK) == 1) {
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uint64_t v;
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return (features & ID_AA64DFR0_PMS_MASK) == 1;
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}
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if (el2_unused) {
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/*
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* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
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* profiling controls to EL2.
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*
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* MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure
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* state. Accesses to profiling buffer controls at
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* Non-secure EL1 are not trapped to EL2.
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*/
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v = read_mdcr_el2();
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v &= ~MDCR_EL2_TPMS;
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v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
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write_mdcr_el2(v);
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}
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void spe_enable(int el2_unused)
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{
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uint64_t v;
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if (!spe_supported())
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return;
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if (el2_unused) {
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/*
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* MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
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* and disabled in secure state. Accesses to SPE registers at
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* S-EL1 generate trap exceptions to EL3.
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* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
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* profiling controls to EL2.
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*
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* MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure
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* state. Accesses to profiling buffer controls at
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* Non-secure EL1 are not trapped to EL2.
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*/
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v = read_mdcr_el3();
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v |= MDCR_NSPB(MDCR_NSPB_EL1);
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write_mdcr_el3(v);
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v = read_mdcr_el2();
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v &= ~MDCR_EL2_TPMS;
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v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
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write_mdcr_el2(v);
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}
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/*
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* MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
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* and disabled in secure state. Accesses to SPE registers at
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* S-EL1 generate trap exceptions to EL3.
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*/
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v = read_mdcr_el3();
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v |= MDCR_NSPB(MDCR_NSPB_EL1);
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write_mdcr_el3(v);
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}
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void spe_disable(void)
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{
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uint64_t features;
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uint64_t v;
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features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
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if ((features & ID_AA64DFR0_PMS_MASK) == 1) {
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uint64_t v;
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if (!spe_supported())
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return;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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/* Disable profiling buffer */
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v = read_pmblimitr_el1();
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v &= ~(1ULL << 0);
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write_pmblimitr_el1(v);
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isb();
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}
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/* Disable profiling buffer */
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v = read_pmblimitr_el1();
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v &= ~(1ULL << 0);
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write_pmblimitr_el1(v);
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isb();
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}
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static void *spe_drain_buffers_hook(const void *arg)
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{
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uint64_t features;
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features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
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if ((features & ID_AA64DFR0_PMS_MASK) == 1) {
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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}
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if (!spe_supported())
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return (void *)-1;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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return 0;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,117 +9,120 @@
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#include <pubsub.h>
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#include <sve.h>
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static void *disable_sve_hook(const void *arg)
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int sve_supported(void)
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
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uint64_t cptr;
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return (features & ID_AA64PFR0_SVE_MASK) == 1;
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}
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/*
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* Disable SVE, SIMD and FP access for the Secure world.
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* As the SIMD/FP registers are part of the SVE Z-registers, any
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* use of SIMD/FP functionality will corrupt the SVE registers.
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* Therefore it is necessary to prevent use of SIMD/FP support
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* in the Secure world as well as SVE functionality.
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*/
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cptr = read_cptr_el3();
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cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT);
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write_cptr_el3(cptr);
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static void *disable_sve_hook(const void *arg)
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{
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uint64_t cptr;
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/*
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* No explicit ISB required here as ERET to switch to Secure
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* world covers it
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*/
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}
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if (!sve_supported())
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return (void *)-1;
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/*
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* Disable SVE, SIMD and FP access for the Secure world.
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* As the SIMD/FP registers are part of the SVE Z-registers, any
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* use of SIMD/FP functionality will corrupt the SVE registers.
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* Therefore it is necessary to prevent use of SIMD/FP support
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* in the Secure world as well as SVE functionality.
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*/
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cptr = read_cptr_el3();
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cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT);
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write_cptr_el3(cptr);
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/*
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* No explicit ISB required here as ERET to switch to Secure
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* world covers it
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*/
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return 0;
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}
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static void *enable_sve_hook(const void *arg)
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{
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uint64_t features;
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uint64_t cptr;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
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uint64_t cptr;
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if (!sve_supported())
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return (void *)-1;
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/*
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* Enable SVE, SIMD and FP access for the Non-secure world.
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*/
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cptr = read_cptr_el3();
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cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT);
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write_cptr_el3(cptr);
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/*
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* Enable SVE, SIMD and FP access for the Non-secure world.
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*/
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cptr = read_cptr_el3();
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cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT);
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write_cptr_el3(cptr);
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/*
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* No explicit ISB required here as ERET to switch to Non-secure
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* world covers it
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*/
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}
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/*
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* No explicit ISB required here as ERET to switch to Non-secure
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* world covers it
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*/
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return 0;
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}
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void sve_enable(int el2_unused)
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{
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uint64_t features;
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uint64_t cptr;
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if (!sve_supported())
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return;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
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uint64_t cptr;
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#if CTX_INCLUDE_FPREGS
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/*
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* CTX_INCLUDE_FPREGS is not supported on SVE enabled systems.
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*/
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assert(0);
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/*
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* CTX_INCLUDE_FPREGS is not supported on SVE enabled systems.
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*/
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assert(0);
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#endif
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/*
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* Update CPTR_EL3 to enable access to SVE functionality for the
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* Non-secure world.
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* NOTE - assumed that CPTR_EL3.TFP is set to allow access to
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* the SIMD, floating-point and SVE support.
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*
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* CPTR_EL3.EZ: Set to 1 to enable access to SVE functionality
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* in the Non-secure world.
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*/
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cptr = read_cptr_el3();
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cptr |= CPTR_EZ_BIT;
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write_cptr_el3(cptr);
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/*
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* Update CPTR_EL3 to enable access to SVE functionality for the
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* Non-secure world.
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* NOTE - assumed that CPTR_EL3.TFP is set to allow access to
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* the SIMD, floating-point and SVE support.
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*
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* CPTR_EL3.EZ: Set to 1 to enable access to SVE functionality
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* in the Non-secure world.
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*/
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cptr = read_cptr_el3();
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cptr |= CPTR_EZ_BIT;
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write_cptr_el3(cptr);
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/*
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* Need explicit ISB here to guarantee that update to ZCR_ELx
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* and CPTR_EL2.TZ do not result in trap to EL3.
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*/
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isb();
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/*
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* Ensure lower ELs have access to full vector length.
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*/
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write_zcr_el3(ZCR_EL3_LEN_MASK);
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if (el2_unused) {
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/*
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* Need explicit ISB here to guarantee that update to ZCR_ELx
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* and CPTR_EL2.TZ do not result in trap to EL3.
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* Update CPTR_EL2 to enable access to SVE functionality
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* for Non-secure world, EL2 and Non-secure EL1 and EL0.
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* NOTE - assumed that CPTR_EL2.TFP is set to allow
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* access to the SIMD, floating-point and SVE support.
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*
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* CPTR_EL2.TZ: Set to 0 to enable access to SVE support
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* for EL2 and Non-secure EL1 and EL0.
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*/
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isb();
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cptr = read_cptr_el2();
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cptr &= ~(CPTR_EL2_TZ_BIT);
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write_cptr_el2(cptr);
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/*
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* Ensure lower ELs have access to full vector length.
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*/
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write_zcr_el3(ZCR_EL3_LEN_MASK);
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if (el2_unused) {
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/*
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* Update CPTR_EL2 to enable access to SVE functionality
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* for Non-secure world, EL2 and Non-secure EL1 and EL0.
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* NOTE - assumed that CPTR_EL2.TFP is set to allow
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* access to the SIMD, floating-point and SVE support.
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*
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* CPTR_EL2.TZ: Set to 0 to enable access to SVE support
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* for EL2 and Non-secure EL1 and EL0.
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*/
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cptr = read_cptr_el2();
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cptr &= ~(CPTR_EL2_TZ_BIT);
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write_cptr_el2(cptr);
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/*
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* Ensure lower ELs have access to full vector length.
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*/
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write_zcr_el2(ZCR_EL2_LEN_MASK);
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}
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/*
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* No explicit ISB required here as ERET to switch to
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* Non-secure world covers it.
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*/
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write_zcr_el2(ZCR_EL2_LEN_MASK);
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}
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/*
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* No explicit ISB required here as ERET to switch to
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* Non-secure world covers it.
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*/
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}
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SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook);
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