RAS: MISRA fixes
These changes address most of the required MISRA rules. In the process, some from generic code is also fixed. No functional changes. Change-Id: I76cacf6e1d73b09510561b5090c2bb66d81bec88 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
This commit is contained in:
Jeenu Viswambharan
parent
03b645ed86
commit
30a8d96e46
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@ -4,10 +4,10 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __RAS_COMMON__
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#define __RAS_COMMON__
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#ifndef RAS_COMMON
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#define RAS_COMMON
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#define ERR_HANDLER_VERSION 1
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#define ERR_HANDLER_VERSION 1U
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/* Error record access mechanism */
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#define ERR_ACCESS_SYSREG 0
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@ -20,18 +20,18 @@
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* are declared. Only then would ARRAY_SIZE() yield a meaningful value.
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*/
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#define REGISTER_ERR_RECORD_INFO(_records) \
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const struct err_record_mapping err_record_mapping = { \
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.err_records = _records, \
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const struct err_record_mapping err_record_mappings = { \
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.err_records = (_records), \
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.num_err_records = ARRAY_SIZE(_records), \
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}
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/* Error record info iterator */
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#define for_each_err_record_info(_i, _info) \
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for (_i = 0, _info = err_record_mapping.err_records; \
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_i < err_record_mapping.num_err_records; \
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_i++, _info++)
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for ((_i) = 0, (_info) = err_record_mappings.err_records; \
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(_i) < err_record_mappings.num_err_records; \
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(_i)++, (_info)++)
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#define _ERR_RECORD_COMMON(_probe, _handler, _aux) \
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#define ERR_RECORD_COMMON_(_probe, _handler, _aux) \
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.probe = _probe, \
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.handler = _handler, \
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.aux_data = _aux,
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@ -42,7 +42,7 @@
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.sysreg.idx_start = _idx_start, \
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.sysreg.num_idx = _num_idx, \
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.access = ERR_ACCESS_SYSREG, \
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_ERR_RECORD_COMMON(_probe, _handler, _aux) \
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ERR_RECORD_COMMON_(_probe, _handler, _aux) \
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}
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#define ERR_RECORD_MEMMAP_V1(_base_addr, _size_num_k, _probe, _handler, _aux) \
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@ -51,7 +51,7 @@
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.memmap.base_addr = _base_addr, \
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.memmap.size_num_k = _size_num_k, \
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.access = ERR_ACCESS_MEMMAP, \
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_ERR_RECORD_COMMON(_probe, _handler, _aux) \
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ERR_RECORD_COMMON_(_probe, _handler, _aux) \
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}
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/*
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@ -63,8 +63,8 @@
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* array is expected to be sorted in the increasing order of interrupt number.
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*/
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#define REGISTER_RAS_INTERRUPTS(_array) \
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const struct ras_interrupt_mapping ras_interrupt_mapping = { \
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.intrs = _array, \
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const struct ras_interrupt_mapping ras_interrupt_mappings = { \
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.intrs = (_array), \
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.num_intrs = ARRAY_SIZE(_array), \
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}
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@ -165,8 +165,8 @@ struct ras_interrupt_mapping {
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size_t num_intrs;
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};
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extern const struct err_record_mapping err_record_mapping;
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extern const struct ras_interrupt_mapping ras_interrupt_mapping;
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extern const struct err_record_mapping err_record_mappings;
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extern const struct ras_interrupt_mapping ras_interrupt_mappings;
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/*
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@ -196,4 +196,4 @@ int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
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void ras_init(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __RAS_COMMON__ */
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#endif /* RAS_COMMON */
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@ -11,28 +11,28 @@
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* Size of nodes implementing Standard Error Records - currently only 4k is
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* supported.
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*/
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#define STD_ERR_NODE_SIZE_NUM_K 4
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#define STD_ERR_NODE_SIZE_NUM_K 4U
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/*
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* Individual register offsets within an error record in Standard Error Record
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* format when error records are accessed through memory-mapped registers.
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*/
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#define ERR_FR(n) (0x0 + (64 * (n)))
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#define ERR_CTLR(n) (0x8 + (64 * (n)))
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#define ERR_STATUS(n) (0x10 + (64 * (n)))
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#define ERR_ADDR(n) (0x18 + (64 * (n)))
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#define ERR_MISC0(n) (0x20 + (64 * (n)))
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#define ERR_MISC1(n) (0x28 + (64 * (n)))
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#define ERR_FR(n) (0x0ULL + (64ULL * (n)))
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#define ERR_CTLR(n) (0x8ULL + (64ULL * (n)))
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#define ERR_STATUS(n) (0x10ULL + (64ULL * (n)))
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#define ERR_ADDR(n) (0x18ULL + (64ULL * (n)))
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#define ERR_MISC0(n) (0x20ULL + (64ULL * (n)))
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#define ERR_MISC1(n) (0x28ULL + (64ULL * (n)))
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/* Group Status Register (ERR_STATUS) offset */
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#define ERR_GSR(base, size_num_k, n) \
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((base) + (0x380 * (size_num_k)) + (8 * (n)))
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((base) + (0x380ULL * (size_num_k)) + (8ULL * (n)))
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/* Management register offsets */
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#define ERR_DEVID(base, size_num_k) \
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((base) + ((0x400 * (size_num_k)) - 0x100) + 0xc8)
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((base) + ((0x400ULL * (size_num_k)) - 0x100ULL) + 0xc8ULL)
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#define ERR_DEVID_MASK 0xffff
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#define ERR_DEVID_MASK 0xffffUL
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/* Standard Error Record status register fields */
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#define ERR_STATUS_AV_SHIFT 31
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@ -244,7 +244,8 @@ static inline uint64_t ser_get_misc1(uintptr_t base, unsigned int idx)
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*/
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static inline void ser_sys_select_record(unsigned int idx)
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{
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unsigned int max_idx __unused = read_erridr_el1() & ERRIDR_MASK;
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unsigned int max_idx __unused =
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(unsigned int) read_erridr_el1() & ERRIDR_MASK;
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assert(idx < max_idx);
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@ -11,6 +11,7 @@
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#include <platform.h>
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#include <ras.h>
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#include <ras_arch.h>
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#include <stdbool.h>
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#ifndef PLAT_RAS_PRI
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# error Platform must define RAS priority value
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@ -20,15 +21,15 @@
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int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
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void *handle, uint64_t flags)
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{
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unsigned int i, n_handled = 0, ret;
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int probe_data;
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unsigned int i, n_handled = 0;
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int probe_data, ret;
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struct err_record_info *info;
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const struct err_handler_data err_data = {
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.version = ERR_HANDLER_VERSION,
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.ea_reason = ea_reason,
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.interrupt = 0,
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.syndrome = syndrome,
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.syndrome = (uint32_t) syndrome,
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.flags = flags,
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.cookie = cookie,
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.handle = handle
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@ -39,7 +40,7 @@ int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
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assert(info->handler != NULL);
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/* Continue probing until the record group signals no error */
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while (1) {
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while (true) {
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if (info->probe(info, &probe_data) == 0)
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break;
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@ -52,20 +53,20 @@ int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
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}
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}
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return (n_handled != 0);
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return (n_handled != 0U) ? 1 : 0;
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}
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#if ENABLE_ASSERTIONS
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static void assert_interrupts_sorted(void)
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{
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unsigned int i, last;
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struct ras_interrupt *start = ras_interrupt_mapping.intrs;
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struct ras_interrupt *start = ras_interrupt_mappings.intrs;
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if (ras_interrupt_mapping.num_intrs == 0)
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if (ras_interrupt_mappings.num_intrs == 0UL)
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return;
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last = start[0].intr_number;
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for (i = 1; i < ras_interrupt_mapping.num_intrs; i++) {
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for (i = 1; i < ras_interrupt_mappings.num_intrs; i++) {
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assert(start[i].intr_number > last);
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last = start[i].intr_number;
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}
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@ -79,7 +80,7 @@ static void assert_interrupts_sorted(void)
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static int ras_interrupt_handler(uint32_t intr_raw, uint32_t flags,
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void *handle, void *cookie)
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{
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struct ras_interrupt *ras_inrs = ras_interrupt_mapping.intrs;
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struct ras_interrupt *ras_inrs = ras_interrupt_mappings.intrs;
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struct ras_interrupt *selected = NULL;
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int start, end, mid, probe_data, ret __unused;
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@ -91,10 +92,10 @@ static int ras_interrupt_handler(uint32_t intr_raw, uint32_t flags,
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.handle = handle
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};
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assert(ras_interrupt_mapping.num_intrs > 0);
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assert(ras_interrupt_mappings.num_intrs > 0UL);
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start = 0;
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end = ras_interrupt_mapping.num_intrs;
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end = (int) ras_interrupt_mappings.num_intrs;
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while (start <= end) {
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mid = ((end + start) / 2);
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if (intr_raw == ras_inrs[mid].intr_number) {
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@ -114,14 +115,14 @@ static int ras_interrupt_handler(uint32_t intr_raw, uint32_t flags,
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panic();
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}
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if (selected->err_record->probe) {
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if (selected->err_record->probe != NULL) {
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ret = selected->err_record->probe(selected->err_record, &probe_data);
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assert(ret != 0);
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}
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/* Call error handler for the record group */
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assert(selected->err_record->handler != NULL);
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selected->err_record->handler(selected->err_record, probe_data,
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(void) selected->err_record->handler(selected->err_record, probe_data,
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&err_data);
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return 0;
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@ -13,28 +13,29 @@
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*/
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int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data)
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{
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int num_records, num_group_regs, i;
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unsigned int num_records, num_group_regs, i;
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uint64_t gsr;
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assert(base != 0);
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assert(base != 0UL);
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/* Only 4K supported for now */
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assert(size_num_k == STD_ERR_NODE_SIZE_NUM_K);
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num_records = (mmio_read_32(ERR_DEVID(base, size_num_k)) & ERR_DEVID_MASK);
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num_records = (unsigned int)
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(mmio_read_32(ERR_DEVID(base, size_num_k)) & ERR_DEVID_MASK);
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/* A group register shows error status for 2^6 error records */
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num_group_regs = (num_records >> 6) + 1;
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num_group_regs = (num_records >> 6U) + 1U;
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/* Iterate through group registers to find a record in error */
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for (i = 0; i < num_group_regs; i++) {
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gsr = mmio_read_64(ERR_GSR(base, size_num_k, i));
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if (gsr == 0)
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if (gsr == 0ULL)
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continue;
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/* Return the index of the record in error */
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if (probe_data != NULL)
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*probe_data = ((i << 6) + __builtin_ctz(gsr));
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*probe_data = (((int) (i << 6U)) + __builtin_ctzll(gsr));
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return 1;
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}
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@ -49,13 +50,14 @@ int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data)
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*/
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int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data)
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{
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int i;
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unsigned int i;
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uint64_t status;
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unsigned int max_idx __unused = read_erridr_el1() & ERRIDR_MASK;
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unsigned int max_idx __unused =
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((unsigned int) read_erridr_el1()) & ERRIDR_MASK;
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assert(idx_start < max_idx);
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assert(check_u32_overflow(idx_start, num_idx) == 0);
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assert((idx_start + num_idx - 1) < max_idx);
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assert(check_u32_overflow(idx_start, num_idx));
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assert((idx_start + num_idx - 1U) < max_idx);
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for (i = 0; i < num_idx; i++) {
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/* Select the error record */
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@ -65,9 +67,9 @@ int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_da
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status = read_erxstatus_el1();
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/* Check for valid field in status */
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if (ERR_STATUS_GET_FIELD(status, V)) {
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if (ERR_STATUS_GET_FIELD(status, V) != 0U) {
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if (probe_data != NULL)
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*probe_data = i;
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*probe_data = (int) i;
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return 1;
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}
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}
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