RAS: Add helpers to access Standard Error Records
The ARMv8 RAS Extensions introduced Standard Error Records which are a
set of standard registers through which:
- Platform can configure RAS node policy; e.g., notification
mechanism;
- RAS nodes can record and expose error information for error handling
agents.
Standard Error Records can either be accessed via. memory-mapped
or System registers. This patch adds helper functions to access
registers and fields within an error record.
Change-Id: I6594ba799f4a1789d7b1e45b3e17fd40e7e0ba5c
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
This commit is contained in:
Jeenu Viswambharan
parent
14c6016ad5
commit
30d81c36da
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@ -717,4 +717,17 @@
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#define DISR_EL1 S3_0_C12_C1_1
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#define DISR_A_BIT 31
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#define ERRIDR_EL1 S3_0_C5_C3_0
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#define ERRIDR_MASK 0xffff
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#define ERRSELR_EL1 S3_0_C5_C3_1
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/* System register access to Standard Error Record registers */
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#define ERXFR_EL1 S3_0_C5_C4_0
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#define ERXCTLR_EL1 S3_0_C5_C4_1
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#define ERXSTATUS_EL1 S3_0_C5_C4_2
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#define ERXADDR_EL1 S3_0_C5_C4_3
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#define ERXMISC0_EL1 S3_0_C5_C4_4
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#define ERXMISC1_EL1 S3_0_C5_C4_5
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#endif /* __ARCH_H__ */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -333,6 +333,16 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
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DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
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#define IS_IN_EL(x) \
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(GET_EL(read_CurrentEl()) == MODE_EL##x)
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@ -0,0 +1,225 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __RAS_H__
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#define __RAS_H__
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <context.h>
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#include <mmio.h>
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#include <stdint.h>
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/*
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* Size of nodes implementing Standard Error Records - currently only 4k is
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* supported.
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*/
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#define STD_ERR_NODE_SIZE_NUM_K 4
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/*
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* Individual register offsets within an error record in Standard Error Record
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* format when error records are accessed through memory-mapped registers.
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*/
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#define ERR_FR(n) (0x0 + (64 * (n)))
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#define ERR_CTLR(n) (0x8 + (64 * (n)))
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#define ERR_STATUS(n) (0x10 + (64 * (n)))
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#define ERR_ADDR(n) (0x18 + (64 * (n)))
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#define ERR_MISC0(n) (0x20 + (64 * (n)))
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#define ERR_MISC1(n) (0x28 + (64 * (n)))
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/* Group Status Register (ERR_STATUS) offset */
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#define ERR_GSR(base, size_num_k, n) \
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((base) + (0x380 * (size_num_k)) + (8 * (n)))
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/* Management register offsets */
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#define ERR_DEVID(base, size_num_k) \
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((base) + ((0x400 * (size_num_k)) - 0x100) + 0xc8)
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#define ERR_DEVID_MASK 0xffff
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/* Standard Error Record status register fields */
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#define ERR_STATUS_AV_SHIFT 31
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#define ERR_STATUS_AV_MASK U(0x1)
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#define ERR_STATUS_V_SHIFT 30
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#define ERR_STATUS_V_MASK U(0x1)
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#define ERR_STATUS_UE_SHIFT 29
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#define ERR_STATUS_UE_MASK U(0x1)
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#define ERR_STATUS_ER_SHIFT 28
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#define ERR_STATUS_ER_MASK U(0x1)
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#define ERR_STATUS_OF_SHIFT 27
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#define ERR_STATUS_OF_MASK U(0x1)
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#define ERR_STATUS_MV_SHIFT 26
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#define ERR_STATUS_MV_MASK U(0x1)
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#define ERR_STATUS_CE_SHIFT 24
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#define ERR_STATUS_CE_MASK U(0x3)
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#define ERR_STATUS_DE_SHIFT 23
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#define ERR_STATUS_DE_MASK U(0x1)
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#define ERR_STATUS_PN_SHIFT 22
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#define ERR_STATUS_PN_MASK U(0x1)
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#define ERR_STATUS_UET_SHIFT 20
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#define ERR_STATUS_UET_MASK U(0x3)
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#define ERR_STATUS_IERR_SHIFT 8
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#define ERR_STATUS_IERR_MASK U(0xff)
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#define ERR_STATUS_SERR_SHIFT 0
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#define ERR_STATUS_SERR_MASK U(0xff)
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#define ERR_STATUS_GET_FIELD(_status, _field) \
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(((_status) >> ERR_STATUS_ ##_field ##_SHIFT) & ERR_STATUS_ ##_field ##_MASK)
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#define ERR_STATUS_CLR_FIELD(_status, _field) \
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(_status) &= ~(ERR_STATUS_ ##_field ##_MASK << ERR_STATUS_ ##_field ##_SHIFT)
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#define ERR_STATUS_SET_FIELD(_status, _field, _value) \
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(_status) |= (((_value) & ERR_STATUS_ ##_field ##_MASK) << ERR_STATUS_ ##_field ##_SHIFT)
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#define ERR_STATUS_WRITE_FIELD(_status, _field, _value) do { \
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ERR_STATUS_CLR_FIELD(_status, _field, _value); \
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ERR_STATUS_SET_FIELD(_status, _field, _value); \
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} while (0)
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/* Standard Error Record control register fields */
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#define ERR_CTLR_WDUI_SHIFT 11
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#define ERR_CTLR_WDUI_MASK 0x1
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#define ERR_CTLR_RDUI_SHIFT 10
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#define ERR_CTLR_RDUI_MASK 0x1
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#define ERR_CTLR_DUI_SHIFT ERR_CTLR_RDUI_SHIFT
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#define ERR_CTLR_DUI_MASK ERR_CTLR_RDUI_MASK
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#define ERR_CTLR_WCFI_SHIFT 9
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#define ERR_CTLR_WCFI_MASK 0x1
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#define ERR_CTLR_RCFI_SHIFT 8
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#define ERR_CTLR_RCFI_MASK 0x1
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#define ERR_CTLR_CFI_SHIFT ERR_CTLR_RCFI_SHIFT
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#define ERR_CTLR_CFI_MASK ERR_CTLR_RCFI_MASK
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#define ERR_CTLR_WUE_SHIFT 7
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#define ERR_CTLR_WUE_MASK 0x1
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#define ERR_CTLR_WFI_SHIFT 6
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#define ERR_CTLR_WFI_MASK 0x1
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#define ERR_CTLR_WUI_SHIFT 5
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#define ERR_CTLR_WUI_MASK 0x1
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#define ERR_CTLR_RUE_SHIFT 4
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#define ERR_CTLR_RUE_MASK 0x1
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#define ERR_CTLR_UE_SHIFT ERR_CTLR_RUE_SHIFT
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#define ERR_CTLR_UE_MASK ERR_CTLR_RUE_MASK
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#define ERR_CTLR_RFI_SHIFT 3
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#define ERR_CTLR_RFI_MASK 0x1
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#define ERR_CTLR_FI_SHIFT ERR_CTLR_RFI_SHIFT
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#define ERR_CTLR_FI_MASK ERR_CTLR_RFI_MASK
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#define ERR_CTLR_RUI_SHIFT 2
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#define ERR_CTLR_RUI_MASK 0x1
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#define ERR_CTLR_UI_SHIFT ERR_CTLR_RUI_SHIFT
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#define ERR_CTLR_UI_MASK ERR_CTLR_RUI_MASK
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#define ERR_CTLR_ED_SHIFT 0
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#define ERR_CTLR_ED_MASK 0x1
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#define ERR_CTLR_CLR_FIELD(_ctlr, _field) \
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(_ctlr) &= ~(ERR_CTLR_ ##_field _MASK << ERR_CTLR_ ##_field ##_SHIFT)
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#define ERR_CTLR_SET_FIELD(_ctlr, _field, _value) \
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(_ctlr) |= (((_value) & ERR_CTLR_ ##_field ##_MASK) << ERR_CTLR_ ##_field ##_SHIFT)
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#define ERR_CTLR_ENABLE_FIELD(_ctlr, _field) \
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ERR_CTLR_SET_FIELD(_ctlr, _field, ERR_CTLR_ ##_field ##_MASK)
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/* Uncorrected error types */
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#define ERROR_STATUS_UET_UC 0x0 /* Uncontainable */
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#define ERROR_STATUS_UET_UEU 0x1 /* Unrecoverable */
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#define ERROR_STATUS_UET_UEO 0x2 /* Restable */
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#define ERROR_STATUS_UET_UER 0x3 /* Recoverable */
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/*
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* Standard Error Record accessors for memory-mapped registers.
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*/
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static inline uint64_t ser_get_feature(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_FR(idx));
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}
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static inline uint64_t ser_get_control(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_CTLR(idx));
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}
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static inline uint64_t ser_get_status(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_STATUS(idx));
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}
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/*
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* Error handling agent would write to the status register to clear an
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* identified/handled error. Most fields in the status register are
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* conditional write-one-to-clear.
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*
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* Typically, to clear the status, it suffices to write back the same value
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* previously read. However, if there were new, higher-priority errors recorded
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* on the node since status was last read, writing read value won't clear the
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* status. Therefore, an error handling agent must wait on and verify the status
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* has indeed been cleared.
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*/
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static inline void ser_set_status(uintptr_t base, unsigned int idx,
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uint64_t status)
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{
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mmio_write_64(base + ERR_STATUS(idx), status);
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}
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static inline uint64_t ser_get_addr(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_ADDR(idx));
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}
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static inline uint64_t ser_get_misc0(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_MISC0(idx));
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}
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static inline uint64_t ser_get_misc1(uintptr_t base, unsigned int idx)
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{
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return mmio_read_64(base + ERR_MISC1(idx));
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}
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/*
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* Standard Error Record helpers for System registers.
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*/
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static inline void ser_sys_select_record(unsigned int idx)
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{
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unsigned int max_idx __unused = read_erridr_el1() & ERRIDR_MASK;
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assert(idx < max_idx);
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write_errselr_el1(idx);
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isb();
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}
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/* Library functions to probe Standard Error Record */
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int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data);
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int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data);
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#endif /* __RAS_H__ */
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@ -67,6 +67,13 @@
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#define check_uptr_overflow(ptr, inc) \
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(((ptr) > UINTPTR_MAX - (inc)) ? 1 : 0)
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/*
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* Evaluates to 1 if (u32 + inc) overflows, 0 otherwise.
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* Both arguments must be 32-bit unsigned integers (i.e. effectively uint32_t).
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*/
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#define check_u32_overflow(u32, inc) \
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((u32) > (UINT32_MAX - (inc)) ? 1 : 0)
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/*
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* For those constants to be shared between C and other sources, apply a 'u'
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* or 'ull' suffix to the argument only in C, to avoid undefined or unintended
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@ -0,0 +1,76 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <ras_arch.h>
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#include <utils_def.h>
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/*
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* Probe for error in memory-mapped registers containing error records
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* implemented Standard Error Record format. Upon detecting an error, set probe
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* data to the index of the record in error, and return 1; otherwise, return 0.
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*/
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int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data)
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{
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int num_records, num_group_regs, i;
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uint64_t gsr;
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assert(base != 0);
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/* Only 4K supported for now */
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assert(size_num_k == STD_ERR_NODE_SIZE_NUM_K);
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num_records = (mmio_read_32(ERR_DEVID(base, size_num_k)) & ERR_DEVID_MASK);
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/* A group register shows error status for 2^6 error records */
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num_group_regs = (num_records >> 6) + 1;
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/* Iterate through group registers to find a record in error */
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for (i = 0; i < num_group_regs; i++) {
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gsr = mmio_read_64(ERR_GSR(base, size_num_k, i));
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if (gsr == 0)
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continue;
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/* Return the index of the record in error */
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if (probe_data != NULL)
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*probe_data = ((i << 6) + __builtin_ctz(gsr));
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return 1;
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}
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return 0;
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}
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/*
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* Probe for error in System Registers where error records are implemented in
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* Standard Error Record format. Upon detecting an error, set probe data to the
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* index of the record in error, and return 1; otherwise, return 0.
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*/
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int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data)
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{
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int i;
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uint64_t status;
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unsigned int max_idx __unused = read_erridr_el1() & ERRIDR_MASK;
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assert(idx_start < max_idx);
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assert(check_u32_overflow(idx_start, num_idx) == 0);
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assert((idx_start + num_idx - 1) < max_idx);
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for (i = 0; i < num_idx; i++) {
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/* Select the error record */
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ser_sys_select_record(idx_start + i);
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/* Retrieve status register from the error record */
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status = read_erxstatus_el1();
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/* Check for valid field in status */
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if (ERR_STATUS_GET_FIELD(status, V)) {
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if (probe_data != NULL)
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*probe_data = i;
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return 1;
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}
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}
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return 0;
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}
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