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fix(mediatek/mt8192/spm): add missing bit define for debug purpose 

Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I6dbf6d4ea6310c3371ca15d1e7cce249a05af2fb
This commit is contained in:
Roger Lu 2021-06-24 15:17:48 +08:00 committed by roger.lu
parent e2a16044ad
commit 310c3a26e1
2 changed files with 10 additions and 14 deletions
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5
plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
View File

@ -143,6 +143,11 @@ unsigned int mt_spm_cond_check(int state_id,
blocked |= SPM_COND_CHECK_BLOCKED_PLL;
}
if (is_system_suspend && (blocked != 0U)) {
INFO("suspend: %s total blocked = 0x%08x\n",
dest->name, blocked);
}
return blocked;
}

19
plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
View File

@ -23,20 +23,11 @@ enum PLAT_SPM_COND {
PLAT_SPM_COND_MAX,
};
enum PLAT_SPM_COND_PLL {
PLAT_SPM_COND_PLL_UNIVPLL = 0,
PLAT_SPM_COND_PLL_MFGPLL,
PLAT_SPM_COND_PLL_MSDCPLL,
PLAT_SPM_COND_PLL_TVDPLL,
PLAT_SPM_COND_PLL_MMPLL,
PLAT_SPM_COND_PLL_MAX,
};
#define PLL_BIT_MFGPLL (PLAT_SPM_COND_PLL_MFGPLL)
#define PLL_BIT_MMPLL (PLAT_SPM_COND_PLL_MMPLL)
#define PLL_BIT_UNIVPLL (PLAT_SPM_COND_PLL_UNIVPLL)
#define PLL_BIT_MSDCPLL (PLAT_SPM_COND_PLL_MSDCPLL)
#define PLL_BIT_TVDPLL (PLAT_SPM_COND_PLL_TVDPLL)
#define PLL_BIT_UNIVPLL BIT(0)
#define PLL_BIT_MFGPLL BIT(1)
#define PLL_BIT_MSDCPLL BIT(2)
#define PLL_BIT_TVDPLL BIT(3)
#define PLL_BIT_MMPLL BIT(4)
/* Definition about SPM_COND_CHECK_BLOCKED
* bit [00 ~ 15]: cg blocking index