feat(board/rdn2): add tzc master source ids for soc dma
Add TZC master source id for DMA in the SoC space and for the DMAs behind the I/O Virtualization block to allow the non-secure transactions from these DMAs targeting DRAM. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I77a2947b01b4b49a7c1940f09cf62b7b5257657c
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@ -44,6 +44,8 @@
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#define TZC_NSAID_ALL_AP U(0)
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#define TZC_NSAID_ALL_AP U(0)
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#define TZC_NSAID_PCI U(1)
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#define TZC_NSAID_PCI U(1)
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#define TZC_NSAID_HDLCD0 U(2)
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#define TZC_NSAID_HDLCD0 U(2)
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#define TZC_NSAID_DMA U(5)
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#define TZC_NSAID_DMA2 U(8)
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#define TZC_NSAID_CLCD U(7)
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#define TZC_NSAID_CLCD U(7)
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#define TZC_NSAID_AP U(9)
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#define TZC_NSAID_AP U(9)
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#define TZC_NSAID_VIRTIO U(15)
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#define TZC_NSAID_VIRTIO U(15)
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@ -52,6 +54,8 @@
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA2)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
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