xilinx: versal: PLM to ATF handover
Parse the parameter structure the PLM populates, to populate the bl32 and bl33 image structures. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443
This commit is contained in:
Venkatesh Yadav Abbarapu
parent
4d9f825a56
commit
31ce893ec2
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@ -33,3 +33,11 @@ Xilinx Versal platform specific build options
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* `VERSAL_PLATFORM`: Select the platform. Options:
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- `versal_virt` : Versal Virtual platform
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# PLM->TF-A Parameter Passing
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------------------------------
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The PLM populates a data structure with image information for the TF-A. The TF-A
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uses that data to hand off to the loaded images. The address of the handoff
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data structure is passed in the ```PMC_GLOBAL_GLOB_GEN_STORAGE4``` register.
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The register is free to be used by other software once the TF-A is bringing up
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further firmware images.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -67,11 +67,3 @@ unsigned int plat_get_syscnt_freq2(void)
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return VERSAL_CPU_CLOCK;
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}
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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#ifdef PRELOADED_BL33_BASE
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return PRELOADED_BL33_BASE;
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#else
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return PLAT_VERSAL_NS_IMAGE_OFFSET;
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#endif
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -13,8 +13,12 @@
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#include <common/debug.h>
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#include <drivers/arm/pl011.h>
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#include <drivers/console.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat/common/platform.h>
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#include <versal_def.h>
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#include <plat_private.h>
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#include <plat_startup.h>
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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@ -36,6 +40,18 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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return &bl32_image_ep_info;
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}
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/*
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* Set the build time defaults,if we can't find any config data.
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*/
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static inline void bl31_set_default_config(void)
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{
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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/*
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* Perform any BL31 specific platform actions. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
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@ -45,6 +61,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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uint64_t atf_handoff_addr;
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/* Initialize the console to provide early debug support */
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int rc = console_pl011_register(VERSAL_UART_BASE,
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@ -76,12 +93,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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/* use build time defaults in JTAG boot mode */
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = 0;
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4);
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enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
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&bl33_image_ep_info,
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atf_handoff_addr);
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if (ret == FSBL_HANDOFF_NO_STRUCT) {
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bl31_set_default_config();
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} else if (ret != FSBL_HANDOFF_SUCCESS) {
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panic();
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}
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NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
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NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -56,9 +56,9 @@
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* BL33 specific defines.
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******************************************************************************/
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#ifndef PRELOADED_BL33_BASE
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# define PLAT_VERSAL_NS_IMAGE_OFFSET 0x8000000
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# define PLAT_ARM_NS_IMAGE_BASE 0x8000000
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#else
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# define PLAT_VERSAL_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
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# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
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#endif
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/*******************************************************************************
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -121,6 +121,10 @@
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#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1
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#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2
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/* PMC registers and bitfields */
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#define PMC_GLOBAL_BASE 0xF1110000
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#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40)
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/* IPI registers and bitfields */
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#define IPI0_REG_BASE 0xFF330000
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#define IPI0_TRIG_BIT (1 << 2)
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@ -1,4 +1,4 @@
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# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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@ -55,6 +55,7 @@ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
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drivers/arm/pl011/aarch64/pl011_console.S \
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plat/common/aarch64/crash_console_helpers.S \
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plat/arm/common/arm_cci.c \
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plat/arm/common/arm_common.c \
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plat/common/plat_gicv3.c \
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plat/xilinx/versal/aarch64/versal_helpers.S \
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plat/xilinx/versal/aarch64/versal_common.c
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@ -64,6 +65,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
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lib/cpus/aarch64/cortex_a72.S \
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plat/common/plat_psci_common.c \
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plat/xilinx/common/ipi.c \
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plat/xilinx/common/plat_startup.c \
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plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
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plat/xilinx/common/pm_service/pm_ipi.c \
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plat/xilinx/versal/bl31_versal_setup.c \
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