Merge pull request #1405 from dp-arm/dp/cve_2017_5715
Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32
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commit
31ece1e025
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@ -12,10 +12,11 @@
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.globl wa_cve_2017_5715_mmu_vbar
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.globl wa_cve_2017_5715_mmu_vbar
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#define ESR_EL3_A64_SMC0 0x5e000000
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#define ESR_EL3_A64_SMC0 0x5e000000
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#define ESR_EL3_A32_SMC0 0x4e000000
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vector_base wa_cve_2017_5715_mmu_vbar
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vector_base wa_cve_2017_5715_mmu_vbar
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.macro apply_cve_2017_5715_wa _is_sync_exception
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.macro apply_cve_2017_5715_wa _is_sync_exception _esr_el3_val
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stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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mrs x1, sctlr_el3
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mrs x1, sctlr_el3
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/* Disable MMU */
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/* Disable MMU */
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@ -32,7 +33,7 @@ vector_base wa_cve_2017_5715_mmu_vbar
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*/
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*/
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/*
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/*
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* Ensure SMC is coming from A64 state on #0
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* Ensure SMC is coming from A64/A32 state on #0
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* with W0 = SMCCC_ARCH_WORKAROUND_1
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* with W0 = SMCCC_ARCH_WORKAROUND_1
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*
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*
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* This sequence evaluates as:
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* This sequence evaluates as:
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@ -43,7 +44,7 @@ vector_base wa_cve_2017_5715_mmu_vbar
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orr w1, wzr, #SMCCC_ARCH_WORKAROUND_1
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orr w1, wzr, #SMCCC_ARCH_WORKAROUND_1
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cmp w0, w1
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cmp w0, w1
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mrs x0, esr_el3
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mrs x0, esr_el3
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mov_imm w1, ESR_EL3_A64_SMC0
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mov_imm w1, \_esr_el3_val
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ccmp w0, w1, #0, eq
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ccmp w0, w1, #0, eq
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/* Static predictor will predict a fall through */
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/* Static predictor will predict a fall through */
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bne 1f
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bne 1f
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@ -104,22 +105,22 @@ vector_entry mmu_serror_sp_elx
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* ---------------------------------------------------------------------
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* ---------------------------------------------------------------------
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*/
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*/
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vector_entry mmu_sync_exception_aarch64
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vector_entry mmu_sync_exception_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=1
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apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A64_SMC0
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b sync_exception_aarch64
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b sync_exception_aarch64
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check_vector_size mmu_sync_exception_aarch64
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check_vector_size mmu_sync_exception_aarch64
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vector_entry mmu_irq_aarch64
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vector_entry mmu_irq_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=0
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b irq_aarch64
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b irq_aarch64
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check_vector_size mmu_irq_aarch64
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check_vector_size mmu_irq_aarch64
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vector_entry mmu_fiq_aarch64
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vector_entry mmu_fiq_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=0
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b fiq_aarch64
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b fiq_aarch64
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check_vector_size mmu_fiq_aarch64
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check_vector_size mmu_fiq_aarch64
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vector_entry mmu_serror_aarch64
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vector_entry mmu_serror_aarch64
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apply_cve_2017_5715_wa _is_sync_exception=0
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A64_SMC0
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b serror_aarch64
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b serror_aarch64
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check_vector_size mmu_serror_aarch64
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check_vector_size mmu_serror_aarch64
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@ -128,21 +129,21 @@ vector_entry mmu_serror_aarch64
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* ---------------------------------------------------------------------
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* ---------------------------------------------------------------------
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*/
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*/
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vector_entry mmu_sync_exception_aarch32
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vector_entry mmu_sync_exception_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=1
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apply_cve_2017_5715_wa _is_sync_exception=1 _esr_el3_val=ESR_EL3_A32_SMC0
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b sync_exception_aarch32
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b sync_exception_aarch32
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check_vector_size mmu_sync_exception_aarch32
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check_vector_size mmu_sync_exception_aarch32
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vector_entry mmu_irq_aarch32
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vector_entry mmu_irq_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=0
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b irq_aarch32
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b irq_aarch32
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check_vector_size mmu_irq_aarch32
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check_vector_size mmu_irq_aarch32
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vector_entry mmu_fiq_aarch32
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vector_entry mmu_fiq_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=0
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b fiq_aarch32
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b fiq_aarch32
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check_vector_size mmu_fiq_aarch32
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check_vector_size mmu_fiq_aarch32
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vector_entry mmu_serror_aarch32
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vector_entry mmu_serror_aarch32
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apply_cve_2017_5715_wa _is_sync_exception=0
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apply_cve_2017_5715_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b serror_aarch32
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b serror_aarch32
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check_vector_size mmu_serror_aarch32
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check_vector_size mmu_serror_aarch32
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