Tegra186: clean CPU wake times from L2 cache
When entering C7, ATF disables caches and flushes the L1 cache. However, wake_time[cpu] can still remain in the L2 cache, causing later reads to it to fetch from DRAM. This will read stale values. Fix this by aligning wake_time[cpu] to cache lines, and explicitly cleaning it before disabling caches. Change-Id: Id73d095b479677595a6b3dd0abb240a1fef5f311 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -63,7 +63,9 @@ extern uint32_t __tegra186_cpu_reset_handler_data,
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#define TEGRA186_SE_CONTEXT_SIZE 3
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static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE];
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static unsigned int wake_time[PLATFORM_CORE_COUNT];
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static struct t18x_psci_percpu_data {
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unsigned int wake_time;
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} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT];
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/* System power down state */
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uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF;
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@ -75,9 +77,19 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
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int cpu = plat_my_core_pos();
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/* save the core wake time (us) */
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wake_time[cpu] = (power_state >> TEGRA186_WAKE_TIME_SHIFT) &
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percpu_data[cpu].wake_time = (power_state >> TEGRA186_WAKE_TIME_SHIFT) &
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TEGRA186_WAKE_TIME_MASK;
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/*
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* Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
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* the correct value is read in tegra_soc_pwr_domain_suspend(), which
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* is called with caches disabled. It is possible to read a stale value
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* from DRAM in that function, because the L2 cache is not flushed
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* unless the cluster is entering CC6/CC7.
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*/
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clean_dcache_range((uint64_t)&percpu_data[cpu],
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sizeof(percpu_data[cpu]));
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/* Sanity check the requested state id */
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switch (state_id) {
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case PSTATE_ID_CORE_IDLE:
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@ -121,7 +133,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
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TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7;
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(void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val,
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wake_time[cpu], 0);
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percpu_data[cpu].wake_time, 0);
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} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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@ -193,7 +205,8 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
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/* Check if CCx state is allowed. */
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ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED,
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TEGRA_ARI_CORE_C7, wake_time[cpu], 0);
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TEGRA_ARI_CORE_C7, percpu_data[cpu].wake_time,
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0);
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if (ret)
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return PSTATE_ID_CORE_POWERDN;
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}
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