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ddr: a80x0: add DDR 32-bit ECC mode support 

Change a topology map from internal database
to SPD based for 32bit bus width mode

Change-Id: I803166893ddc2fd916fc8a1c27fffd34b6ec0c72
Signed-off-by: Alex Leibovich <alexl@marvell.com>
This commit is contained in:
Alex Leibovich 2019-03-10 16:45:02 +02:00 committed by Marcin Wojtas
parent 615d859b2e
commit 32b3b99918
1 changed files with 1 additions and 2 deletions
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3
plat/marvell/armada/a8k/a80x0/board/dram_port.c
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@ -54,11 +54,10 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TEMP_LOW} }, /* temperature */
#if DDR32
MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
#else
MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
MV_DDR_CFG_SPD, /* ddr configuration data source */
#endif
MV_DDR_CFG_SPD, /* ddr configuration data source */
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ /* electrical configuration */