intel: Implement platform specific system reset 2
Add support for platform specific warm-reset through psci system reset 2. - system_reset2 implementation that calls for l2 cache reset - Check for magic number and request for warm reset in bl2 - Create a shared reset manager header file for Agilex and Stratix 10 - Clean up parameter info in plat_get_next_bl_params Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726
This commit is contained in:
Hadi Asyrafi
parent
13d33d52ce
commit
32cf34acac
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@ -66,12 +66,34 @@ func plat_my_core_pos
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ret
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endfunc plat_my_core_pos
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func warm_reset_req
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str xzr, [x4]
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bl plat_is_my_cpu_primary
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cbz x0, cpu_in_wfi
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mov_imm x1, PLAT_SEC_ENTRY
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str xzr, [x1]
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mrs x1, rmr_el3
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orr x1, x1, #0x02
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msr rmr_el3, x1
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isb
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dsb sy
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cpu_in_wfi:
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wfi
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b cpu_in_wfi
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endfunc warm_reset_req
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func plat_get_my_entrypoint
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ldr x4, =L2_RESET_DONE_REG
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ldr x5, [x4]
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ldr x1, =L2_RESET_DONE_STATUS
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cmp x1, x5
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b.eq warm_reset_req
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mov_imm x1, PLAT_SEC_ENTRY
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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@ -19,6 +19,15 @@
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/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
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#define PLAT_CPU_RELEASE_ADDR 0xffd12210
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/*
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* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
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* is done and HPS should trigger warm reset via RMR_EL3.
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*/
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#define L2_RESET_DONE_REG 0xFFD12218
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/* Magic word to indicate L2 reset is completed */
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#define L2_RESET_DONE_STATUS 0x1228E5E7
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/* Define next boot image name and offset */
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#define PLAT_NS_IMAGE_OFFSET 0x50000
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#define PLAT_HANDOFF_OFFSET 0xFFE3F000
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_RESETMANAGER_H
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#define SOCFPGA_RESETMANAGER_H
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#define SOCFPGA_RSTMGR_STAT 0xffd11000
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#define SOCFPGA_RSTMGR_HDSKEN 0xffd11010
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#define SOCFPGA_RSTMGR_COLDMODRST 0xffd11034
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#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0xffd11064
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#define SOCFPGA_RSTMGR_HDSKEN_SET 0x0000010D
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#define SOCFPGA_RSTMGR_SDMWARMRST 0x00000002
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#endif /* SOCFPGA_RESETMANAGER_H */
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@ -28,5 +28,31 @@ bl_load_info_t *plat_get_bl_image_load_info(void)
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******************************************************************************/
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bl_params_t *plat_get_next_bl_params(void)
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{
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unsigned int count;
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unsigned int img_id = 0U;
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unsigned int link_index = 0U;
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bl_params_node_t *bl_exec_node = NULL;
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bl_mem_params_node_t *desc_ptr;
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/* If there is no image to start with, return NULL */
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if (bl_mem_params_desc_num == 0U)
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return NULL;
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/* Clean next_params_info in BL image node */
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for (count = 0U; count < bl_mem_params_desc_num; count++) {
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desc_ptr = &bl_mem_params_desc_ptr[link_index];
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bl_exec_node = &desc_ptr->params_node_mem;
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bl_exec_node->next_params_info = NULL;
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/* If no next hand-off image then break out */
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img_id = desc_ptr->next_handoff_image_id;
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if (img_id == INVALID_IMAGE_ID)
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break;
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/* Get the index for the next hand-off image */
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link_index = get_bl_params_node_index(img_id);
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}
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return get_next_bl_params_from_mem_params_desc();
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}
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@ -13,6 +13,7 @@
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#include "socfpga_mailbox.h"
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#include "socfpga_plat_def.h"
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#include "socfpga_reset_manager.h"
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@ -75,6 +76,7 @@ void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state)
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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/* assert core reset */
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mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
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@ -136,6 +138,31 @@ static void __dead2 socfpga_system_reset(void)
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wfi();
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}
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static int socfpga_system_reset2(int is_vendor, int reset_type,
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u_register_t cookie)
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{
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/* disable cpuif */
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gicv2_cpuif_disable();
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/* Store magic number */
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mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS);
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/* Increase timeout */
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mmio_write_32(SOCFPGA_RSTMGR_HDSKTIMEOUT, 0xffffff);
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/* Enable handshakes */
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mmio_setbits_32(SOCFPGA_RSTMGR_HDSKEN, SOCFPGA_RSTMGR_HDSKEN_SET);
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/* Reset L2 module */
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mmio_setbits_32(SOCFPGA_RSTMGR_COLDMODRST, 0x100);
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while (1)
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wfi();
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/* Should not reach here */
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return 0;
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}
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int socfpga_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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@ -169,6 +196,7 @@ const plat_psci_ops_t socfpga_psci_pm_ops = {
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.pwr_domain_suspend_finish = socfpga_pwr_domain_suspend_finish,
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.system_off = socfpga_system_off,
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.system_reset = socfpga_system_reset,
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.system_reset2 = socfpga_system_reset2,
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.validate_power_state = socfpga_validate_power_state,
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.validate_ns_entrypoint = socfpga_validate_ns_entrypoint,
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.get_sys_suspend_power_state = socfpga_get_sys_suspend_power_state
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