Merge pull request #1236 from dbasehore/gic-save-restore
RK3399 GIC save/restore
This commit is contained in:
davidcunado-arm
GitHub
commit
334e1ceb48
|
|
@ -83,6 +83,15 @@ void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num)
|
|||
gicr_base = gicv3_driver_data->rdistif_base_addrs[rdist_proc_num];
|
||||
assert(gicr_base);
|
||||
|
||||
/*
|
||||
* If the GIC had power removed, the GICR_WAKER state will be reset.
|
||||
* Since the GICR_WAKER.Sleep and GICR_WAKER.Quiescent bits are cleared,
|
||||
* we can exit early. This also prevents the following assert from
|
||||
* erroneously triggering.
|
||||
*/
|
||||
if (!(gicr_read_waker(gicr_base) & WAKER_SL_BIT))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Writes to GICR_WAKER.Sleep bit are ignored if GICR_WAKER.Quiescent
|
||||
* bit is not set. We should be alright on power on path, therefore
|
||||
|
|
|
|||
|
|
@ -246,14 +246,14 @@ void rockchip_pwr_domain_suspend(const psci_power_state_t *target_state)
|
|||
if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
|
||||
return;
|
||||
|
||||
/* Prevent interrupts from spuriously waking up this cpu */
|
||||
plat_rockchip_gic_cpuif_disable();
|
||||
|
||||
if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
|
||||
rockchip_soc_sys_pwr_dm_suspend();
|
||||
else
|
||||
rockchip_soc_cores_pwr_dm_suspend();
|
||||
|
||||
/* Prevent interrupts from spuriously waking up this cpu */
|
||||
plat_rockchip_gic_cpuif_disable();
|
||||
|
||||
/* Perform the common cluster specific operations */
|
||||
if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
|
||||
plat_cci_disable();
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <delay_timer.h>
|
||||
#include <dfs.h>
|
||||
#include <errno.h>
|
||||
#include <gicv3.h>
|
||||
#include <gpio.h>
|
||||
#include <m0_ctl.h>
|
||||
#include <mmio.h>
|
||||
|
|
@ -45,6 +46,8 @@ static uint32_t store_grf_soc_con7;
|
|||
static uint32_t store_grf_ddrc_con[4];
|
||||
static uint32_t store_wdt0[2];
|
||||
static uint32_t store_wdt1[2];
|
||||
static gicv3_dist_ctx_t dist_ctx;
|
||||
static gicv3_redist_ctx_t rdist_ctx;
|
||||
|
||||
/*
|
||||
* There are two ways to powering on or off on core.
|
||||
|
|
@ -79,9 +82,12 @@ static void pmu_bus_idle_req(uint32_t bus, uint32_t state)
|
|||
do {
|
||||
bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id;
|
||||
bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id;
|
||||
if (bus_state == bus_req && bus_ack == bus_req)
|
||||
break;
|
||||
|
||||
wait_cnt++;
|
||||
} while ((bus_state != bus_req || bus_ack != bus_req) &&
|
||||
(wait_cnt < MAX_WAIT_COUNT));
|
||||
udelay(1);
|
||||
} while (wait_cnt < MAX_WAIT_COUNT);
|
||||
|
||||
if (bus_state != bus_req || bus_ack != bus_req) {
|
||||
INFO("%s:st=%x(%x)\n", __func__,
|
||||
|
|
@ -95,7 +101,7 @@ static void pmu_bus_idle_req(uint32_t bus, uint32_t state)
|
|||
|
||||
struct pmu_slpdata_s pmu_slpdata;
|
||||
|
||||
static void qos_save(void)
|
||||
static void qos_restore(void)
|
||||
{
|
||||
if (pmu_power_domain_st(PD_GPU) == pmu_pd_on)
|
||||
RESTORE_QOS(pmu_slpdata.gpu_qos, GPU);
|
||||
|
|
@ -161,7 +167,7 @@ static void qos_save(void)
|
|||
}
|
||||
}
|
||||
|
||||
static void qos_restore(void)
|
||||
static void qos_save(void)
|
||||
{
|
||||
if (pmu_power_domain_st(PD_GPU) == pmu_pd_on)
|
||||
SAVE_QOS(pmu_slpdata.gpu_qos, GPU);
|
||||
|
|
@ -430,6 +436,7 @@ static void pmu_scu_b_pwrdn(void)
|
|||
while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) &
|
||||
BIT(STANDBY_BY_WFIL2_CLUSTER_B))) {
|
||||
wait_cnt++;
|
||||
udelay(1);
|
||||
if (wait_cnt >= MAX_WAIT_COUNT)
|
||||
ERROR("%s:wait cluster-b l2(%x)\n", __func__,
|
||||
mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
|
||||
|
|
@ -1327,6 +1334,9 @@ int rockchip_soc_sys_pwr_dm_suspend(void)
|
|||
dmc_suspend();
|
||||
pmu_scu_b_pwrdn();
|
||||
|
||||
gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
|
||||
gicv3_distif_save(&dist_ctx);
|
||||
|
||||
/* need to save usbphy before shutdown PERIHP PD */
|
||||
save_usbphy();
|
||||
|
||||
|
|
@ -1369,6 +1379,7 @@ int rockchip_soc_sys_pwr_dm_suspend(void)
|
|||
mmio_read_32(PMU_BASE + PMU_ADB400_ST));
|
||||
panic();
|
||||
}
|
||||
udelay(1);
|
||||
}
|
||||
mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
|
||||
|
||||
|
|
@ -1462,6 +1473,7 @@ int rockchip_soc_sys_pwr_dm_resume(void)
|
|||
mmio_read_32(PMU_BASE + PMU_ADB400_ST));
|
||||
panic();
|
||||
}
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
pmu_sgrf_rst_hld_release();
|
||||
|
|
@ -1481,6 +1493,8 @@ int rockchip_soc_sys_pwr_dm_resume(void)
|
|||
BIT(PMU_CLR_PERILPM0) |
|
||||
BIT(PMU_CLR_GIC));
|
||||
|
||||
gicv3_distif_init_restore(&dist_ctx);
|
||||
gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
|
||||
plat_rockchip_gic_cpuif_enable();
|
||||
m0_stop();
|
||||
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ enum pmu_core_pwrst_shift {
|
|||
#define TSADC_INT_PIN 38
|
||||
#define CORES_PM_DISABLE 0x0
|
||||
|
||||
#define PD_CTR_LOOP 500
|
||||
#define PD_CTR_LOOP 10000
|
||||
#define CHK_CPU_LOOP 500
|
||||
#define MAX_WAIT_COUNT 1000
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@ PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \
|
|||
-I${RK_PLAT_SOC}/include/shared/ \
|
||||
|
||||
RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v3/arm_gicv3_common.c \
|
||||
drivers/arm/gic/v3/gic500.c \
|
||||
drivers/arm/gic/v3/gicv3_main.c \
|
||||
drivers/arm/gic/v3/gicv3_helpers.c \
|
||||
plat/common/plat_gicv3.c \
|
||||
|
|
|
|||
Loading…
Reference in New Issue