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feat(st): use newly introduced clock framework 

Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().

Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
This commit is contained in:
Yann Gautier 2021-08-30 15:06:54 +02:00 committed by Yann Gautier
parent 847c6bc8e6
commit 33667d299b
18 changed files with 133 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

63
drivers/st/clk/stm32mp1_clk.c
View File

@ -17,6 +17,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <common/fdt_wrappers.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/st/stm32mp_clkfunc.h>
@ -1157,17 +1158,19 @@ void __stm32mp1_clk_disable(unsigned long id, bool secure)
stm32mp1_clk_unlock(&refcount_lock);
}
void stm32mp_clk_enable(unsigned long id)
static int stm32mp_clk_enable(unsigned long id)
{
__stm32mp1_clk_enable(id, true);
return 0;
}
void stm32mp_clk_disable(unsigned long id)
static void stm32mp_clk_disable(unsigned long id)
{
__stm32mp1_clk_disable(id, true);
}
bool stm32mp_clk_is_enabled(unsigned long id)
static bool stm32mp_clk_is_enabled(unsigned long id)
{
int i;
@ -1183,15 +1186,55 @@ bool stm32mp_clk_is_enabled(unsigned long id)
return __clk_is_enabled(gate_ref(i));
}
unsigned long stm32mp_clk_get_rate(unsigned long id)
static unsigned long stm32mp_clk_get_rate(unsigned long id)
{
uintptr_t rcc_base = stm32mp_rcc_base();
int p = stm32mp1_clk_get_parent(id);
uint32_t prescaler, timpre;
unsigned long parent_rate;
if (p < 0) {
return 0;
}
return get_clock_rate(p);
parent_rate = get_clock_rate(p);
switch (id) {
case TIM2_K:
case TIM3_K:
case TIM4_K:
case TIM5_K:
case TIM6_K:
case TIM7_K:
case TIM12_K:
case TIM13_K:
case TIM14_K:
prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) &
RCC_APBXDIV_MASK;
timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) &
RCC_TIMGXPRER_TIMGXPRE;
break;
case TIM1_K:
case TIM8_K:
case TIM15_K:
case TIM16_K:
case TIM17_K:
prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) &
RCC_APBXDIV_MASK;
timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) &
RCC_TIMGXPRER_TIMGXPRE;
break;
default:
return parent_rate;
}
if (prescaler == 0U) {
return parent_rate;
}
return parent_rate * (timpre + 1U) * 2U;
}
static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on)
@ -2264,11 +2307,21 @@ static void sync_earlyboot_clocks_state(void)
}
}
static const struct clk_ops stm32mp_clk_ops = {
.enable = stm32mp_clk_enable,
.disable = stm32mp_clk_disable,
.is_enabled = stm32mp_clk_is_enabled,
.get_rate = stm32mp_clk_get_rate,
.get_parent = stm32mp1_clk_get_parent,
};
int stm32mp1_clk_probe(void)
{
stm32mp1_osc_init();
sync_earlyboot_clocks_state();
clk_register(&stm32mp_clk_ops);
return 0;
}

3
drivers/st/clk/stm32mp_clkfunc.c
View File

@ -11,6 +11,7 @@
#include <platform_def.h>
#include <common/fdt_wrappers.h>
#include <drivers/clk.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
@ -325,5 +326,5 @@ unsigned long fdt_get_uart_clock_freq(uintptr_t instance)
return 0UL;
}
return stm32mp_clk_get_rate((unsigned long)clk_id);
return clk_get_rate((unsigned long)clk_id);
}

21
drivers/st/crypto/stm32_hash.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -14,6 +14,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_hash.h>
#include <drivers/st/stm32mp_reset.h>
@ -189,7 +190,7 @@ int stm32_hash_update(const uint8_t *buffer, size_t length)
return 0;
}
stm32mp_clk_enable(stm32_hash.clock);
clk_enable(stm32_hash.clock);
if (stm32_remain.length != 0U) {
uint32_t copysize;
@ -231,7 +232,7 @@ int stm32_hash_update(const uint8_t *buffer, size_t length)
}
exit:
stm32mp_clk_disable(stm32_hash.clock);
clk_disable(stm32_hash.clock);
return ret;
}
@ -240,12 +241,12 @@ int stm32_hash_final(uint8_t *digest)
{
int ret;
stm32mp_clk_enable(stm32_hash.clock);
clk_enable(stm32_hash.clock);
if (stm32_remain.length != 0U) {
ret = hash_write_data(stm32_remain.buffer);
if (ret != 0) {
stm32mp_clk_disable(stm32_hash.clock);
clk_disable(stm32_hash.clock);
return ret;
}
@ -260,7 +261,7 @@ int stm32_hash_final(uint8_t *digest)
ret = hash_get_digest(digest);
stm32mp_clk_disable(stm32_hash.clock);
clk_disable(stm32_hash.clock);
return ret;
}
@ -280,11 +281,11 @@ int stm32_hash_final_update(const uint8_t *buffer, uint32_t length,
void stm32_hash_init(enum stm32_hash_algo_mode mode)
{
stm32mp_clk_enable(stm32_hash.clock);
clk_enable(stm32_hash.clock);
hash_hw_init(mode);
stm32mp_clk_disable(stm32_hash.clock);
clk_disable(stm32_hash.clock);
zeromem(&stm32_remain, sizeof(stm32_remain));
}
@ -321,7 +322,7 @@ int stm32_hash_register(void)
stm32_hash.base = hash_info.base;
stm32_hash.clock = hash_info.clock;
stm32mp_clk_enable(stm32_hash.clock);
clk_enable(stm32_hash.clock);
if (hash_info.reset >= 0) {
uint32_t id = (uint32_t)hash_info.reset;
@ -335,7 +336,7 @@ int stm32_hash_register(void)
}
}
stm32mp_clk_disable(stm32_hash.clock);
clk_disable(stm32_hash.clock);
return 0;
}

5
drivers/st/ddr/stm32mp1_ddr.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -12,6 +12,7 @@
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32mp1_ddr.h>
@ -627,7 +628,7 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
*/
/* Change Bypass Mode Frequency Range */
if (stm32mp_clk_get_rate(DDRPHYC) < 100000000U) {
if (clk_get_rate(DDRPHYC) < 100000000U) {
mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
DDRPHYC_DLLGCR_BPS200);
} else {

5
drivers/st/ddr/stm32mp1_ram.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -13,6 +13,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <common/fdt_wrappers.h>
#include <drivers/clk.h>
#include <drivers/st/stm32mp1_ddr.h>
#include <drivers/st/stm32mp1_ddr_helpers.h>
#include <drivers/st/stm32mp1_ram.h>
@ -29,7 +30,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
ddr_enable_clock();
ddrphy_clk = stm32mp_clk_get_rate(DDRPHYC);
ddrphy_clk = clk_get_rate(DDRPHYC);
VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n",
mem_speed, ddrphy_clk / 1000U);

5
drivers/st/fmc/stm32_fmc2_nand.c
View File

@ -14,6 +14,7 @@
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/raw_nand.h>
#include <drivers/st/stm32_fmc2_nand.h>
@ -162,7 +163,7 @@ static uintptr_t fmc2_base(void)
static void stm32_fmc2_nand_setup_timing(void)
{
struct stm32_fmc2_nand_timings tims;
unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id);
unsigned long hclk = clk_get_rate(stm32_fmc2.clock_id);
unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U);
unsigned long timing, tar, tclr, thiz, twait;
unsigned long tset_mem, tset_att, thold_mem, thold_att;
@ -909,7 +910,7 @@ int stm32_fmc2_init(void)
}
/* Enable Clock */
stm32mp_clk_enable(stm32_fmc2.clock_id);
clk_enable(stm32_fmc2.clock_id);
/* Reset IP */
ret = stm32mp_reset_assert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS);

9
drivers/st/gpio/stm32_gpio.c
View File

@ -14,6 +14,7 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <lib/mmio.h>
@ -208,7 +209,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
assert(pin <= GPIO_PIN_MAX);
stm32mp_clk_enable(clock);
clk_enable(clock);
mmio_clrbits_32(base + GPIO_MODE_OFFSET,
((uint32_t)GPIO_MODE_MASK << (pin << 1)));
@ -254,7 +255,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
mmio_read_32(base + GPIO_AFRH_OFFSET));
stm32mp_clk_disable(clock);
clk_disable(clock);
if (status == DT_SECURE) {
stm32mp_register_secure_gpio(bank, pin);
@ -273,7 +274,7 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
assert(pin <= GPIO_PIN_MAX);
stm32mp_clk_enable(clock);
clk_enable(clock);
if (secure) {
mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
@ -281,7 +282,7 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
}
stm32mp_clk_disable(clock);
clk_disable(clock);
}
void set_gpio_reset_cfg(uint32_t bank, uint32_t pin)

21
drivers/st/i2c/stm32_i2c.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,6 +13,7 @@
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32_i2c.h>
@ -158,7 +159,7 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c,
hi2c->i2c_state = I2C_STATE_BUSY;
stm32mp_clk_enable(hi2c->clock);
clk_enable(hi2c->clock);
/* Disable the selected I2C peripheral */
mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
@ -220,11 +221,11 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c,
I2C_ANALOGFILTER_DISABLE);
if (rc != 0) {
ERROR("Cannot initialize I2C analog filter (%d)\n", rc);
stm32mp_clk_disable(hi2c->clock);
clk_disable(hi2c->clock);
return rc;
}
stm32mp_clk_disable(hi2c->clock);
clk_disable(hi2c->clock);
return rc;
}
@ -548,7 +549,7 @@ static int i2c_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
return -EINVAL;
}
stm32mp_clk_enable(hi2c->clock);
clk_enable(hi2c->clock);
hi2c->lock = 1;
@ -648,7 +649,7 @@ static int i2c_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
bail:
hi2c->lock = 0;
stm32mp_clk_disable(hi2c->clock);
clk_disable(hi2c->clock);
return rc;
}
@ -729,7 +730,7 @@ static int i2c_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
return -EINVAL;
}
stm32mp_clk_enable(hi2c->clock);
clk_enable(hi2c->clock);
hi2c->lock = 1;
@ -817,7 +818,7 @@ static int i2c_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
bail:
hi2c->lock = 0;
stm32mp_clk_disable(hi2c->clock);
clk_disable(hi2c->clock);
return rc;
}
@ -882,7 +883,7 @@ bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c,
return rc;
}
stm32mp_clk_enable(hi2c->clock);
clk_enable(hi2c->clock);
hi2c->lock = 1;
hi2c->i2c_mode = I2C_MODE_NONE;
@ -974,7 +975,7 @@ bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c,
bail:
hi2c->lock = 0;
stm32mp_clk_disable(hi2c->clock);
clk_disable(hi2c->clock);
return rc;
}

7
drivers/st/iwdg/stm32_iwdg.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -15,6 +15,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/arm/gicv2.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_iwdg.h>
#include <drivers/st/stm32mp_clkfunc.h>
@ -61,12 +62,12 @@ void stm32_iwdg_refresh(void)
/* 0x00000000 is not a valid address for IWDG peripherals */
if (iwdg->base != 0U) {
stm32mp_clk_enable(iwdg->clock);
clk_enable(iwdg->clock);
mmio_write_32(iwdg->base + IWDG_KR_OFFSET,
IWDG_KR_RELOAD_KEY);
stm32mp_clk_disable(iwdg->clock);
clk_disable(iwdg->clock);
}
}
}

7
drivers/st/mmc/stm32_sdmmc2.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, STMicroelectronics - All Rights Reserved
* Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -15,6 +15,7 @@
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/mmc.h>
#include <drivers/st/stm32_gpio.h>
@ -714,7 +715,7 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
return -ENOMEM;
}
stm32mp_clk_enable(sdmmc2_params.clock_id);
clk_enable(sdmmc2_params.clock_id);
rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
if (rc != 0) {
@ -727,7 +728,7 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
}
mdelay(1);
sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id);
sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id);
sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4;
return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,

7
drivers/st/spi/stm32_qspi.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -11,6 +11,7 @@
#include <common/debug.h>
#include <common/fdt_wrappers.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/spi_mem.h>
#include <drivers/st/stm32_gpio.h>
@ -364,7 +365,7 @@ static void stm32_qspi_release_bus(void)
static int stm32_qspi_set_speed(unsigned int hz)
{
unsigned long qspi_clk = stm32mp_clk_get_rate(stm32_qspi.clock_id);
unsigned long qspi_clk = clk_get_rate(stm32_qspi.clock_id);
uint32_t prescaler = UINT8_MAX;
uint32_t csht;
int ret;
@ -494,7 +495,7 @@ int stm32_qspi_init(void)
stm32_qspi.clock_id = (unsigned long)info.clock;
stm32_qspi.reset_id = (unsigned int)info.reset;
stm32mp_clk_enable(stm32_qspi.clock_id);
clk_enable(stm32_qspi.clock_id);
ret = stm32mp_reset_assert(stm32_qspi.reset_id, TIMEOUT_US_1_MS);
if (ret != 0) {

9
plat/st/common/include/stm32mp_common.h
View File

@ -92,15 +92,6 @@ void stm32mp_print_cpuinfo(void);
/* Print board information */
void stm32mp_print_boardinfo(void);
/*
* Util for clock gating and to get clock rate for stm32 and platform drivers
* @id: Target clock ID, ID used in clock DT bindings
*/
bool stm32mp_clk_is_enabled(unsigned long id);
void stm32mp_clk_enable(unsigned long id);
void stm32mp_clk_disable(unsigned long id);
unsigned long stm32mp_clk_get_rate(unsigned long id);
/* Initialise the IO layer and register platform IO devices */
void stm32mp_io_setup(void);

5
plat/st/common/stm32mp_common.c
View File

@ -9,6 +9,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32mp_clkfunc.h>
@ -188,13 +189,13 @@ int stm32mp_uart_console_setup(void)
}
#endif
stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
clk_enable((unsigned long)dt_uart_info.clock);
#if defined(IMAGE_BL2)
reset_uart((uint32_t)dt_uart_info.reset);
#endif
clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock);
if (console_stm32_register(dt_uart_info.base, clk_rate,
STM32MP_UART_BAUDRATE, &console) == 0) {

6
plat/st/stm32mp1/stm32mp1_fconf_firewall.c
View File

@ -9,7 +9,7 @@
#include <common/debug.h>
#include <common/fdt_wrappers.h>
#include <drivers/arm/tzc400.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/clk.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/fconf/fconf.h>
#include <lib/object_pool.h>
@ -31,8 +31,8 @@ struct dt_id_attr {
void stm32mp1_arch_security_setup(void)
{
stm32mp_clk_enable(TZC1);
stm32mp_clk_enable(TZC2);
clk_enable(TZC1);
clk_enable(TZC2);
tzc400_init(STM32MP1_TZC_BASE);
tzc400_disable_filters();

8
plat/st/stm32mp1/stm32mp1_pm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -14,7 +14,7 @@
#include <common/debug.h>
#include <drivers/arm/gic_common.h>
#include <drivers/arm/gicv2.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/clk.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
@ -74,7 +74,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
return PSCI_E_INVALID_ADDRESS;
}
stm32mp_clk_enable(RTCAPB);
clk_enable(RTCAPB);
cntfrq_core0 = read_cntfrq_el0();
@ -84,7 +84,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
/* Write magic number in backup register */
mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER);
stm32mp_clk_disable(RTCAPB);
clk_disable(RTCAPB);
/* Generate an IT to core 1 */
gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU);

9
plat/st/stm32mp1/stm32mp1_private.c
View File

@ -6,6 +6,7 @@
#include <assert.h>
#include <drivers/clk.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32_iwdg.h>
#include <lib/mmio.h>
@ -566,14 +567,14 @@ void stm32_save_boot_interface(uint32_t interface, uint32_t instance)
{
uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
stm32mp_clk_enable(RTCAPB);
clk_enable(RTCAPB);
mmio_clrsetbits_32(bkpr_itf_idx,
TAMP_BOOT_MODE_ITF_MASK,
((interface << 4) | (instance & 0xFU)) <<
TAMP_BOOT_MODE_ITF_SHIFT);
stm32mp_clk_disable(RTCAPB);
clk_disable(RTCAPB);
}
void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
@ -583,12 +584,12 @@ void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
if (itf == 0U) {
uint32_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
stm32mp_clk_enable(RTCAPB);
clk_enable(RTCAPB);
itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >>
TAMP_BOOT_MODE_ITF_SHIFT;
stm32mp_clk_disable(RTCAPB);
clk_disable(RTCAPB);
}
*interface = itf >> 4;

13
plat/st/stm32mp1/stm32mp1_scmi.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -8,6 +8,7 @@
#include <platform_def.h>
#include <drivers/clk.h>
#include <drivers/scmi-msg.h>
#include <drivers/scmi.h>
#include <drivers/st/stm32mp1_clk.h>
@ -274,7 +275,7 @@ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
if (array == NULL) {
*nb_elts = 1U;
} else if (*nb_elts == 1U) {
*array = stm32mp_clk_get_rate(clock->clock_id);
*array = clk_get_rate(clock->clock_id);
} else {
return SCMI_GENERIC_ERROR;
}
@ -292,7 +293,7 @@ unsigned long plat_scmi_clock_get_rate(unsigned int agent_id,
return 0U;
}
return stm32mp_clk_get_rate(clock->clock_id);
return clk_get_rate(clock->clock_id);
}
int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id)
@ -323,13 +324,13 @@ int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id,
if (enable_not_disable) {
if (!clock->enabled) {
VERBOSE("SCMI clock %u enable\n", scmi_id);
stm32mp_clk_enable(clock->clock_id);
clk_enable(clock->clock_id);
clock->enabled = true;
}
} else {
if (clock->enabled) {
VERBOSE("SCMI clock %u disable\n", scmi_id);
stm32mp_clk_disable(clock->clock_id);
clk_disable(clock->clock_id);
clock->enabled = false;
}
}
@ -461,7 +462,7 @@ void stm32mp1_init_scmi_server(void)
/* Sync SCMI clocks with their targeted initial state */
if (clk->enabled &&
stm32mp_nsec_can_access_clock(clk->clock_id)) {
stm32mp_clk_enable(clk->clock_id);
clk_enable(clk->clock_id);
}
}

5
plat/st/stm32mp1/stm32mp1_security.c
View File

@ -10,6 +10,7 @@
#include <common/debug.h>
#include <drivers/arm/tzc400.h>
#include <drivers/clk.h>
#include <drivers/st/stm32mp1_clk.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/soc/stm32mp15-tzc400.h>
@ -106,8 +107,8 @@ static void init_tzc400(void)
******************************************************************************/
static void early_init_tzc400(void)
{
stm32mp_clk_enable(TZC1);
stm32mp_clk_enable(TZC2);
clk_enable(TZC1);
clk_enable(TZC2);
/* Region 0 set to cover all DRAM secure at 0xC000_0000 */
init_tzc400_begin(TZC_REGION_S_RDWR);