andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge changes I36e4d672,I47610cee into integration 

* changes:
  Workaround for Cortex N1 erratum 1946160
  Workaround for Cortex A78 erratum 1951500
This commit is contained in:
Lauren Wehrmeister 2021-01-14 22:45:20 +00:00 committed by TrustedFirmware Code Review
parent 65d227c3a2 263ee781c6
commit 337e493306
5 changed files with 153 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
docs/design/cpu-specific-build-macros.rst
View File

@ -268,6 +268,10 @@ For Cortex-A78, the following errata build flags are defined :
- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78
CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
issue but there is no workaround for that revision.
For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
@ -306,6 +310,10 @@ For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
revisions r0p0, r1p0, and r2p0 there is no workaround.
DSU Errata Workarounds
----------------------

3
include/lib/cpus/errata_report.h
View File

@ -30,4 +30,7 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported);
#define ERRATA_APPLIES 1
#define ERRATA_MISSING 2
/* Macro to get CPU revision code for checking errata version compatibility. */
#define CPU_REV(r, p) ((r << 4) | p)
#endif /* ERRATA_REPORT_H */

60
lib/cpus/aarch64/cortex_a78.S
View File

@ -72,6 +72,60 @@ func check_errata_1941498
b cpu_rev_var_ls
endfunc check_errata_1941498
/* --------------------------------------------------
* Errata Workaround for A78 Erratum 1951500.
* This applies to revisions r1p0 and r1p1 of A78.
* The issue also exists in r0p0 but there is no fix
* in that revision.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_1951500_wa
/* Compare x0 against revisions r1p0 - r1p1 */
mov x17, x30
bl check_errata_1951500
cbz x0, 1f
msr S3_6_c15_c8_0, xzr
ldr x0, =0x10E3900002
msr S3_6_c15_c8_2, x0
ldr x0, =0x10FFF00083
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
mov x0, #1
msr S3_6_c15_c8_0, x0
ldr x0, =0x10E3800082
msr S3_6_c15_c8_2, x0
ldr x0, =0x10FFF00083
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
mov x0, #2
msr S3_6_c15_c8_0, x0
ldr x0, =0x10E3800200
msr S3_6_c15_c8_2, x0
ldr x0, =0x10FFF003E0
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
isb
1:
ret x17
endfunc errata_a78_1951500_wa
func check_errata_1951500
/* Applies to revisions r1p0 and r1p1. */
mov x1, #CPU_REV(1, 0)
mov x2, #CPU_REV(1, 1)
b cpu_rev_var_range
endfunc check_errata_1951500
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A78
* -------------------------------------------------
@ -91,6 +145,11 @@ func cortex_a78_reset_func
bl errata_a78_1941498_wa
#endif
#if ERRATA_A78_1951500
mov x0, x18
bl errata_a78_1951500_wa
#endif
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@ -147,6 +206,7 @@ func cortex_a78_errata_report
*/
report_errata ERRATA_A78_1688305, cortex_a78, 1688305
report_errata ERRATA_A78_1941498, cortex_a78, 1941498
report_errata ERRATA_A78_1951500, cortex_a78, 1951500
ldp x8, x30, [sp], #16
ret

65
lib/cpus/aarch64/neoverse_n1.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -407,6 +407,63 @@ func check_errata_1868343
b cpu_rev_var_ls
endfunc check_errata_1868343
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1946160.
* This applies to revisions r3p0, r3p1, r4p0, and
* r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
* and r2p0 but there is no fix in these revisions.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1946160_wa
/*
* Compare x0 against r3p0 - r4p1
*/
mov x17, x30
bl check_errata_1946160
cbz x0, 1f
mov x0, #3
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
msr S3_6_C15_C8_2, x0
ldr x0, =0x10FFF00083
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
mov x0, #4
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800082
msr S3_6_C15_C8_2, x0
ldr x0, =0x10FFF00083
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
mov x0, #5
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800200
msr S3_6_C15_C8_2, x0
ldr x0, =0x10FFF003E0
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
isb
1:
ret x17
endfunc errata_n1_1946160_wa
func check_errata_1946160
/* Applies to r3p0 - r4p1. */
mov x1, #0x30
mov x2, #0x41
b cpu_rev_var_range
endfunc check_errata_1946160
func neoverse_n1_reset_func
mov x19, x30
@ -486,6 +543,11 @@ func neoverse_n1_reset_func
bl errata_n1_1868343_wa
#endif
#if ERRATA_N1_1946160
mov x0, x18
bl errata_n1_1946160_wa
#endif
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@ -560,6 +622,7 @@ func neoverse_n1_errata_report
report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
ldp x8, x30, [sp], #16

18
lib/cpus/cpu-ops.mk
View File

@ -298,6 +298,11 @@ ERRATA_A78_1688305 ?=0
# to revisions r0p0, r1p0, and r1p1 of the A78 cpu.
ERRATA_A78_1941498 ?=0
# Flag to apply erratum 1951500 workaround during reset. This erratum applies
# to revisions r1p0 and r1p1 of the A78 cpu. The issue is present in r0p0 as
# well but there is no workaround for that revision.
ERRATA_A78_1951500 ?=0
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_N1_1043202 ?=0
@ -350,6 +355,11 @@ ERRATA_N1_1542419 ?=0
# to revision <= r4p0 of the Neoverse N1 cpu.
ERRATA_N1_1868343 ?=0
# Flag to apply erratum 1946160 workaround during reset. This erratum applies
# to revisions r3p0, r3p1, r4p0, and r4p1 of the Neoverse N1 cpu. The issue
# exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround.
ERRATA_N1_1946160 ?=0
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
ERRATA_DSU_798953 ?=0
@ -583,6 +593,10 @@ $(eval $(call add_define,ERRATA_A78_1688305))
$(eval $(call assert_boolean,ERRATA_A78_1941498))
$(eval $(call add_define,ERRATA_A78_1941498))
# Process ERRATA_A78_1951500 flag
$(eval $(call assert_boolean,ERRATA_A78_1951500))
$(eval $(call add_define,ERRATA_A78_1951500))
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_N1_1043202))
@ -635,6 +649,10 @@ $(eval $(call add_define,ERRATA_N1_1542419))
$(eval $(call assert_boolean,ERRATA_N1_1868343))
$(eval $(call add_define,ERRATA_N1_1868343))
# Process ERRATA_N1_1946160 flag
$(eval $(call assert_boolean,ERRATA_N1_1946160))
$(eval $(call add_define,ERRATA_N1_1946160))
# Process ERRATA_DSU_798953 flag
$(eval $(call assert_boolean,ERRATA_DSU_798953))
$(eval $(call add_define,ERRATA_DSU_798953))