rcar_gen3: drivers: serial controller interface
Signed-off-by: ldts <jramirez@baylibre.com>
This commit is contained in:
Jorge Ramirez-Ortiz
ldts
parent
b3bd0731fd
commit
33947f2e4f
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/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#define SCIF_INTERNAL_CLK 0
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#define SCIF_EXTARNAL_CLK 1
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#define SCIF_CLK SCIF_INTERNAL_CLK
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/* product register */
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#define PRR (0xFFF00044)
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#define PRR_PRODUCT_MASK (0x00007F00)
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#define PRR_CUT_MASK (0x000000FF)
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#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
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#define PRR_PRODUCT_E3 (0x00005700)
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/* module stop */
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#define CPG_BASE (0xE6150000)
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#define CPG_SMSTPCR3 (0x013C)
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#define CPG_MSTPSR3 (0x0048)
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#define MSTP310 (1 << 10)
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#define CPG_CPGWPR (0x0900)
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/* scif */
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#define SCIF2_BASE (0xE6E88000)
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#define SCIF_SCSMR (0x00)
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#define SCIF_SCBRR (0x04)
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#define SCIF_SCSCR (0x08)
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#define SCIF_SCFTDR (0x0C)
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#define SCIF_SCFSR (0x10)
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#define SCIF_SCFRDR (0x14)
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#define SCIF_SCFCR (0x18)
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#define SCIF_SCFDR (0x1C)
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#define SCIF_SCSPTR (0x20)
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#define SCIF_SCLSR (0x24)
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#define SCIF_DL (0x30)
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#define SCIF_CKS (0x34)
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/* mode pin */
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#define RST_MODEMR (0xE6160060)
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#define MODEMR_MD12 (0x00001000)
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#define SCSMR_CA_MASK (1 << 7)
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#define SCSMR_CA_ASYNC (0x0000)
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#define SCSMR_CHR_MASK (1 << 6)
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#define SCSMR_CHR_8 (0x0000)
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#define SCSMR_PE_MASK (1 << 5)
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#define SCSMR_PE_DIS (0x0000)
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#define SCSMR_STOP_MASK (1 << 3)
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#define SCSMR_STOP_1 (0x0000)
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#define SCSMR_CKS_MASK (3 << 0)
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#define SCSMR_CKS_DIV1 (0x0000)
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#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
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SCSMR_CHR_8 + \
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SCSMR_PE_DIS + \
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SCSMR_STOP_1 + \
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SCSMR_CKS_DIV1)
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#define SCBRR_115200BPS (17)
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#define SCBRR_115200BPS_E3_SSCG (15)
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#define SCBRR_230400BPS (8)
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#define SCSCR_TE_MASK (1 << 5)
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#define SCSCR_TE_DIS (0x0000)
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#define SCSCR_TE_EN (0x0020)
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#define SCSCR_RE_MASK (1 << 4)
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#define SCSCR_RE_DIS (0x0000)
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#define SCSCR_RE_EN (0x0010)
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#define SCSCR_CKE_MASK (3 << 0)
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#define SCSCR_CKE_INT (0x0000)
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#define SCSCR_CKE_BRG (0x0002)
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#if SCIF_CLK == SCIF_EXTARNAL_CLK
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#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
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#else
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#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
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#endif
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#define SCFSR_INIT_DATA (0x0000)
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#define SCFCR_TTRG_MASK (3 << 4)
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#define SCFCR_TTRG_8 (0x0000)
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#define SCFCR_TTRG_0 (0x0030)
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#define SCFCR_TFRST_MASK (1 << 2)
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#define SCFCR_TFRST_DIS (0x0000)
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#define SCFCR_TFRST_EN (0x0004)
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#define SCFCR_RFRS_MASK (1 << 1)
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#define SCFCR_RFRS_DIS (0x0000)
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#define SCFCR_RFRS_EN (0x0002)
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#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
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#define SCFDR_T_MASK (0x1f << 8)
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#define DL_INIT_DATA (8)
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#define CKS_CKS_DIV_MASK (1 << 15)
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#define CKS_CKS_DIV_CLK (0x0000)
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#define CKS_XIN_MASK (1 << 14)
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#define CKS_XIN_SCIF_CLK (0x0000)
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#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
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.globl console_init
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.globl console_uninit
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.globl console_putc
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.globl console_core_init
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.globl console_core_putc
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.globl console_getc
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.globl console_flush
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/*
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* The console base is in the data section and not in .bss
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* even though it is zero-init. In particular, this allows
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* the console functions to start using this variable before
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* the runtime memory is initialized for images which do not
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* need to copy the .data section from ROM to RAM.
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*/
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/* -----------------------------------------------
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* int console_init(unsigned long base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the console without a
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* C Runtime to print debug information. It saves
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* the console base to the data section.
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* In: x0 - console base address
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* w1 - Uart clock in Hz
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* w2 - Baud rate
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* out: return 1 on success.
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* Clobber list : x1 - x3
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* -----------------------------------------------
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*/
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func console_init
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b console_core_init
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endfunc console_init
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func console_uninit
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ret
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endfunc console_uninit
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/* -----------------------------------------------
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* int console_core_init(unsigned long base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the console without a
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* C Runtime to print debug information. This
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* function will be accessed by console_init and
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* crash reporting.
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* In: x0 - console base address
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* w1 - Uart clock in Hz
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* w2 - Baud rate
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* Out: return 1 on success
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* Clobber list : x1, x2
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* -----------------------------------------------
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*/
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func console_core_init
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ldr x0, =CPG_BASE
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ldr w1, [x0, #CPG_SMSTPCR3]
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and w1, w1, #~MSTP310 /* MSTP310=0 */
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mvn w2, w1
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str w2, [x0, #CPG_CPGWPR]
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str w1, [x0, #CPG_SMSTPCR3]
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5:
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ldr w1, [x0, #CPG_MSTPSR3]
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and w1, w1, #MSTP310
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cbnz w1, 5b
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ldr x0, =SCIF2_BASE
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/* Clear bits TE and RE in SCSCR to 0 */
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mov w1, #(SCSCR_TE_DIS + SCSCR_RE_DIS)
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strh w1, [x0, #SCIF_SCSCR]
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/* Set bits TFRST and RFRST in SCFCR to 1 */
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ldrh w1, [x0, #SCIF_SCFCR]
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orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN)
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strh w1, [x0, #SCIF_SCFCR]
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/* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
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in SCLSR, then clear them to 0 */
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mov w1, #SCFSR_INIT_DATA
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strh w1, [x0, #SCIF_SCFSR]
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mov w1, #0
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strh w1, [x0, #SCIF_SCLSR]
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/* Set bits CKE[1:0] in SCSCR */
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ldrh w1, [x0, #SCIF_SCSCR]
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and w1, w1, #~SCSCR_CKE_MASK
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mov w2, #SCSCR_CKE_INT_CLK
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orr w1, w1, w2
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strh w1, [x0, #SCIF_SCSCR]
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/* Set data transfer format in SCSMR */
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mov w1, #SCSMR_INIT_DATA
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strh w1, [x0, #SCIF_SCSMR]
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/* Set value in SCBRR */
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#if SCIF_CLK == SCIF_INTERNAL_CLK
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ldr x1, =PRR
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ldr w1, [x1]
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and w1, w1, #(PRR_PRODUCT_MASK | PRR_CUT_MASK)
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mov w2, #PRR_PRODUCT_H3_VER_10
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cmp w1, w2
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beq 3f
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and w1, w1, #PRR_PRODUCT_MASK
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mov w2, #PRR_PRODUCT_E3
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cmp w1, w2
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bne 4f
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ldr x1, =RST_MODEMR
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ldr w1, [x1]
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and w1, w1, #MODEMR_MD12
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mov w2, #MODEMR_MD12
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cmp w1, w2
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bne 4f
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mov w1, #SCBRR_115200BPS_E3_SSCG
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b 2f
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4:
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mov w1, #SCBRR_115200BPS
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b 2f
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3:
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mov w1, #SCBRR_230400BPS
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2:
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strb w1, [x0, SCIF_SCBRR]
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#else
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mov w1, #DL_INIT_DATA
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strh w1, [x0, #SCIF_DL]
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mov w1, #CKS_INIT_DATA
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strh w1, [x0, #SCIF_CKS]
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#endif
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/* 1-bit interval elapsed */
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mov w1, #100
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1:
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subs w1, w1, #1
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cbnz w1, 1b
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/*
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* Set bits RTRG[1:0], TTRG[1:0], and MCE in SCFCR
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* Clear bits FRST and RFRST to 0
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*/
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mov w1, #SCFCR_INIT_DATA
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strh w1, [x0, #SCIF_SCFCR]
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/* Set bits TE and RE in SCSCR to 1 */
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ldrh w1, [x0, #SCIF_SCSCR]
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orr w1, w1, #(SCSCR_TE_EN + SCSCR_RE_EN)
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strh w1, [x0, #SCIF_SCSCR]
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mov x0, #1
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ret
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endfunc console_core_init
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/* ---------------------------------------------
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* int console_putc(int c)
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* Function to output a character over the
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* console. It returns the character printed on
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* success or -1 on error.
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* In : x0 - character to be printed
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* Out : return -1 on error else return character.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func console_putc
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b console_core_putc
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endfunc console_putc
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/* --------------------------------------------------------
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* int console_core_putc(int c, unsigned int base_addr)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In : w0 - character to be printed
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* x1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : x2
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* --------------------------------------------------------
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*/
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func console_core_putc
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ldr x1, =SCIF2_BASE
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cmp w0, #0xA
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/* Prepend '\r' to '\n' */
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bne 2f
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1:
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/* Check if the transmit FIFO is full */
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ldrh w2, [x1, #SCIF_SCFDR]
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ubfx w2, w2, #8, #5
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cmp w2, #16
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bcs 1b
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mov w2, #0x0D
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strb w2, [x1, #SCIF_SCFTDR]
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2:
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/* Check if the transmit FIFO is full */
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ldrh w2, [x1, #SCIF_SCFDR]
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ubfx w2, w2, #8, #5
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cmp w2, #16
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bcs 2b
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strb w0, [x1, #SCIF_SCFTDR]
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ret
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endfunc console_core_putc
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/* ---------------------------------------------
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* int console_getc(void)
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* Function to get a character from the console.
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* It returns the character grabbed on success
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* or -1 on error.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_getc
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mov w0, #-1
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ret
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endfunc console_getc
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/* ---------------------------------------------
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* int console_flush(void)
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* Function to force a write of all buffered
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* data that hasn't been output. It returns 0
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* upon successful completion, otherwise it
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* returns -1.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_flush
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ldr x0, =SCIF2_BASE
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1:
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ldrh w1, [x0, #SCIF_SCFDR]
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ubfx w1, w1, #8, #5
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cmp w1, #0
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bne 1b
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mov x0, #100
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mov x3, x30
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bl rcar_micro_delay
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mov x30, x3
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ldr x0, =SCIF2_BASE
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ldrh w1, [x0, #SCIF_SCSCR]
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and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)
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strh w1, [x0, #SCIF_SCSCR]
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mov w0, #0
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ret
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endfunc console_flush
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