feat(plat/mediatek/apu): add mt8195 APU iommap regions

Add APU iommap settings for reviser, apu_ao and
clock/pll register ranges.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If24cf21318813babfc2c11f38891521c7106b58c
This commit is contained in:
Flora Fu 2021-11-01 16:33:22 +08:00
parent d605439900
commit 339e4924a7
2 changed files with 18 additions and 0 deletions

View File

@ -21,6 +21,14 @@ const mmap_region_t plat_mmap[] = {
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(eDP_SEC_BASE, eDP_SEC_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(APUSYS_APU_PLL_BASE, APUSYS_APU_PLL_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(APUSYS_APU_ACC_BASE, APUSYS_APU_ACC_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};

View File

@ -21,6 +21,16 @@
#define MTK_MCDI_SRAM_BASE 0x11B000
#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
#define APUSYS_BASE 0x19000000
#define APUSYS_SCTRL_REVISER_BASE 0x19021000
#define APUSYS_SCTRL_REVISER_SIZE 0x1000
#define APUSYS_APU_S_S_4_BASE 0x190F2000
#define APUSYS_APU_S_S_4_SIZE 0x1000
#define APUSYS_APU_PLL_BASE 0x190F3000
#define APUSYS_APU_PLL_SIZE 0x1000
#define APUSYS_APU_ACC_BASE 0x190F4000
#define APUSYS_APU_ACC_SIZE 0x1000
#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define SPM_BASE (IO_PHYS + 0x00006000)