Merge "drivers: stm32mp1 clocks: allow tree lookup for several system clocks" into integration
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343580e59a
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@ -106,10 +106,61 @@ enum stm32mp1_parent_sel {
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_MCUS_SEL,
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_USBPHY_SEL,
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_USBO_SEL,
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_MPU_SEL,
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_PER_SEL,
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_PARENT_SEL_NB,
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_UNKNOWN_SEL = 0xff,
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};
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/* State the parent clock ID straight related to a clock */
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static const uint8_t parent_id_clock_id[_PARENT_NB] = {
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[_HSE] = CK_HSE,
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[_HSI] = CK_HSI,
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[_CSI] = CK_CSI,
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[_LSE] = CK_LSE,
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[_LSI] = CK_LSI,
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[_I2S_CKIN] = _UNKNOWN_ID,
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[_USB_PHY_48] = _UNKNOWN_ID,
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[_HSI_KER] = CK_HSI,
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[_HSE_KER] = CK_HSE,
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[_HSE_KER_DIV2] = CK_HSE_DIV2,
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[_CSI_KER] = CK_CSI,
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[_PLL1_P] = PLL1_P,
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[_PLL1_Q] = PLL1_Q,
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[_PLL1_R] = PLL1_R,
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[_PLL2_P] = PLL2_P,
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[_PLL2_Q] = PLL2_Q,
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[_PLL2_R] = PLL2_R,
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[_PLL3_P] = PLL3_P,
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[_PLL3_Q] = PLL3_Q,
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[_PLL3_R] = PLL3_R,
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[_PLL4_P] = PLL4_P,
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[_PLL4_Q] = PLL4_Q,
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[_PLL4_R] = PLL4_R,
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[_ACLK] = CK_AXI,
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[_PCLK1] = CK_AXI,
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[_PCLK2] = CK_AXI,
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[_PCLK3] = CK_AXI,
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[_PCLK4] = CK_AXI,
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[_PCLK5] = CK_AXI,
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[_CK_PER] = CK_PER,
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[_CK_MPU] = CK_MPU,
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[_CK_MCU] = CK_MCU,
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};
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static unsigned int clock_id2parent_id(unsigned long id)
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{
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unsigned int n;
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for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) {
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if (parent_id_clock_id[n] == id) {
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return n;
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}
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}
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return _UNKNOWN_ID;
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}
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enum stm32mp1_pll_id {
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_PLL1,
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_PLL2,
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@ -281,19 +332,6 @@ struct stm32mp1_clk_pll {
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.refclk[3] = (p4), \
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}
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static const uint8_t stm32mp1_clks[][2] = {
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{ CK_PER, _CK_PER },
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{ CK_MPU, _CK_MPU },
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{ CK_AXI, _ACLK },
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{ CK_MCU, _CK_MCU },
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{ CK_HSE, _HSE },
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{ CK_CSI, _CSI },
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{ CK_LSI, _LSI },
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{ CK_LSE, _LSE },
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{ CK_HSI, _HSI },
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{ CK_HSE_DIV2, _HSE_KER_DIV2 },
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};
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#define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
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static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
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@ -440,6 +478,14 @@ static const uint8_t usbo_parents[] = {
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_PLL4_R, _USB_PHY_48
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};
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static const uint8_t mpu_parents[] = {
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_HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */
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};
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static const uint8_t per_parents[] = {
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_HSI, _HSE, _CSI,
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};
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static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
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_CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents),
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_CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents),
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@ -448,6 +494,8 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
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_CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents),
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_CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents),
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_CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents),
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_CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents),
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_CLK_PARENT_SEL(PER, RCC_CPERCKSELR, per_parents),
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_CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents),
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_CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents),
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_CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents),
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@ -618,16 +666,16 @@ static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i)
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static int stm32mp1_clk_get_parent(unsigned long id)
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{
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const struct stm32mp1_clk_sel *sel;
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uint32_t j, p_sel;
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uint32_t p_sel;
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int i;
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enum stm32mp1_parent_id p;
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enum stm32mp1_parent_sel s;
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uintptr_t rcc_base = stm32mp_rcc_base();
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for (j = 0U; j < ARRAY_SIZE(stm32mp1_clks); j++) {
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if (stm32mp1_clks[j][0] == id) {
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return (int)stm32mp1_clks[j][1];
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}
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/* Few non gateable clock have a static parent ID, find them */
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i = (int)clock_id2parent_id(id);
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if (i != _UNKNOWN_ID) {
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return i;
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}
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i = stm32mp1_clk_get_gated_id(id);
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@ -250,6 +250,8 @@
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#define RCC_MPCKSELR_HSE 0x00000001
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#define RCC_MPCKSELR_PLL 0x00000002
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#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003
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#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0)
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#define RCC_MPCKSELR_MPUSRC_SHIFT 0
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/* Values of RCC_ASSCKSELR register */
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#define RCC_ASSCKSELR_HSI 0x00000000
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@ -266,6 +268,8 @@
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#define RCC_CPERCKSELR_HSI 0x00000000
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#define RCC_CPERCKSELR_CSI 0x00000001
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#define RCC_CPERCKSELR_HSE 0x00000002
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#define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0)
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#define RCC_CPERCKSELR_PERSRC_SHIFT 0
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/* Used for most of DIVR register: max div for RTC */
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#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
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