Merge changes from topic "stm32-etzpc" into integration
* changes: plat/stm32mp1: sp_min relies on etzpc driver dts: stm32mp157c: add etzpc node drivers: introduce ST ETZPC driver
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
34a66d80be
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@ -0,0 +1,258 @@
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/*
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* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdint.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/st/etzpc.h>
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#include <dt-bindings/soc/st,stm32-etzpc.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <libfdt.h>
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#include <platform_def.h>
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/* Device Tree related definitions */
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#define ETZPC_COMPAT "st,stm32-etzpc"
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#define ETZPC_LOCK_MASK 0x1U
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#define ETZPC_MODE_SHIFT 8
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#define ETZPC_MODE_MASK GENMASK(1, 0)
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#define ETZPC_ID_SHIFT 16
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#define ETZPC_ID_MASK GENMASK(7, 0)
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/* ID Registers */
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#define ETZPC_TZMA0_SIZE 0x000U
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#define ETZPC_DECPROT0 0x010U
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#define ETZPC_DECPROT_LOCK0 0x030U
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#define ETZPC_HWCFGR 0x3F0U
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#define ETZPC_VERR 0x3F4U
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/* ID Registers fields */
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#define ETZPC_TZMA0_SIZE_LOCK BIT(31)
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#define ETZPC_DECPROT0_MASK GENMASK(1, 0)
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#define ETZPC_HWCFGR_NUM_TZMA_SHIFT 0
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#define ETZPC_HWCFGR_NUM_PER_SEC_SHIFT 8
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#define ETZPC_HWCFGR_NUM_AHB_SEC_SHIFT 16
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#define ETZPC_HWCFGR_CHUNCKS1N4_SHIFT 24
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#define DECPROT_SHIFT 1
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#define IDS_PER_DECPROT_REGS 16U
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#define IDS_PER_DECPROT_LOCK_REGS 32U
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/*
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* etzpc_instance.
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* base : register base address set during init given by user
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* chunk_size : supported TZMA size steps
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* num_tzma: number of TZMA zone read from register at init
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* num_ahb_sec : number of securable AHB master zone read from register
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* num_per_sec : number of securable AHB & APB Peripherals read from register
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* revision : IP revision read from register at init
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*/
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struct etzpc_instance {
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uintptr_t base;
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uint8_t chunck_size;
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uint8_t num_tzma;
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uint8_t num_per_sec;
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uint8_t num_ahb_sec;
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uint8_t revision;
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};
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/* Only 1 instance of the ETZPC is expected per platform */
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static struct etzpc_instance etzpc_dev;
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/*
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* Implementation uses uint8_t to store each securable DECPROT configuration.
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* When resuming from deep suspend, the DECPROT configurations are restored.
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*/
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#define PERIPH_LOCK_BIT BIT(7)
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#define PERIPH_ATTR_MASK GENMASK(2, 0)
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#if ENABLE_ASSERTIONS
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static bool valid_decprot_id(unsigned int id)
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{
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return id < (unsigned int)etzpc_dev.num_per_sec;
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}
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static bool valid_tzma_id(unsigned int id)
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{
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return id < (unsigned int)etzpc_dev.num_tzma;
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}
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#endif
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/*
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* etzpc_configure_decprot : Load a DECPROT configuration
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* decprot_id : ID of the IP
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* decprot_attr : Restriction access attribute
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*/
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void etzpc_configure_decprot(uint32_t decprot_id,
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enum etzpc_decprot_attributes decprot_attr)
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{
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uintptr_t offset = 4U * (decprot_id / IDS_PER_DECPROT_REGS);
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uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT;
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uint32_t masked_decprot = (uint32_t)decprot_attr & ETZPC_DECPROT0_MASK;
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assert(valid_decprot_id(decprot_id));
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mmio_clrsetbits_32(etzpc_dev.base + ETZPC_DECPROT0 + offset,
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(uint32_t)ETZPC_DECPROT0_MASK << shift,
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masked_decprot << shift);
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}
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/*
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* etzpc_get_decprot : Get the DECPROT attribute
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* decprot_id : ID of the IP
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* return : Attribute of this DECPROT
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*/
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enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id)
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{
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uintptr_t offset = 4U * (decprot_id / IDS_PER_DECPROT_REGS);
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uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT;
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uintptr_t base_decprot = etzpc_dev.base + offset;
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uint32_t value;
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assert(valid_decprot_id(decprot_id));
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value = (mmio_read_32(base_decprot + ETZPC_DECPROT0) >> shift) &
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ETZPC_DECPROT0_MASK;
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return (enum etzpc_decprot_attributes)value;
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}
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/*
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* etzpc_lock_decprot : Lock access to the DECPROT attribute
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* decprot_id : ID of the IP
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*/
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void etzpc_lock_decprot(uint32_t decprot_id)
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{
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uintptr_t offset = 4U * (decprot_id / IDS_PER_DECPROT_LOCK_REGS);
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uint32_t shift = BIT(decprot_id % IDS_PER_DECPROT_LOCK_REGS);
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uintptr_t base_decprot = etzpc_dev.base + offset;
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assert(valid_decprot_id(decprot_id));
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mmio_write_32(base_decprot + ETZPC_DECPROT_LOCK0, shift);
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}
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/*
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* etzpc_configure_tzma : Configure the target TZMA read only size
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* tzma_id : ID of the memory
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* tzma_value : read-only size
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*/
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void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value)
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{
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assert(valid_tzma_id(tzma_id));
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mmio_write_32(etzpc_dev.base + ETZPC_TZMA0_SIZE +
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(sizeof(uint32_t) * tzma_id), tzma_value);
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}
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/*
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* etzpc_get_tzma : Get the target TZMA read only size
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* tzma_id : TZMA ID
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* return : Size of read only size
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*/
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uint16_t etzpc_get_tzma(uint32_t tzma_id)
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{
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assert(valid_tzma_id(tzma_id));
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return (uint16_t)mmio_read_32(etzpc_dev.base + ETZPC_TZMA0_SIZE +
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(sizeof(uint32_t) * tzma_id));
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}
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/*
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* etzpc_lock_tzma : Lock the target TZMA
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* tzma_id : TZMA ID
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*/
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void etzpc_lock_tzma(uint32_t tzma_id)
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{
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assert(valid_tzma_id(tzma_id));
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mmio_setbits_32(etzpc_dev.base + ETZPC_TZMA0_SIZE +
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(sizeof(uint32_t) * tzma_id), ETZPC_TZMA0_SIZE_LOCK);
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}
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/*
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* etzpc_get_lock_tzma : Return the lock status of the target TZMA
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* tzma_id : TZMA ID
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* return : True if TZMA is locked, false otherwise
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*/
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bool etzpc_get_lock_tzma(uint32_t tzma_id)
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{
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uint32_t tzma_size;
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assert(valid_tzma_id(tzma_id));
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tzma_size = mmio_read_32(etzpc_dev.base + ETZPC_TZMA0_SIZE +
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(sizeof(uint32_t) * tzma_id));
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return (tzma_size & ETZPC_TZMA0_SIZE_LOCK) != 0;
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}
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/*
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* etzpc_get_num_per_sec : Return the DECPROT ID limit value
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*/
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uint8_t etzpc_get_num_per_sec(void)
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{
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return etzpc_dev.num_per_sec;
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}
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/*
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* etzpc_get_revision : Return the ETZPC IP revision
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*/
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uint8_t etzpc_get_revision(void)
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{
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return etzpc_dev.revision;
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}
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/*
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* etzpc_get_base_address : Return the ETZPC IP base address
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*/
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uintptr_t etzpc_get_base_address(void)
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{
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return etzpc_dev.base;
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}
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/*
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* etzpc_init : Initialize the ETZPC driver
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* Return 0 on success and a negative errno on failure
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*/
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int etzpc_init(void)
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{
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uint32_t hwcfg;
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int node;
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struct dt_node_info etzpc_info;
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node = dt_get_node(&etzpc_info, -1, ETZPC_COMPAT);
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if (node < 0) {
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return -EIO;
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}
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/* Check ETZPC is secure only */
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if (etzpc_info.status != DT_SECURE) {
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return -EACCES;
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}
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etzpc_dev.base = etzpc_info.base;
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hwcfg = mmio_read_32(etzpc_dev.base + ETZPC_HWCFGR);
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etzpc_dev.num_tzma = (uint8_t)(hwcfg >> ETZPC_HWCFGR_NUM_TZMA_SHIFT);
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etzpc_dev.num_per_sec = (uint8_t)(hwcfg >>
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ETZPC_HWCFGR_NUM_PER_SEC_SHIFT);
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etzpc_dev.num_ahb_sec = (uint8_t)(hwcfg >>
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ETZPC_HWCFGR_NUM_AHB_SEC_SHIFT);
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etzpc_dev.chunck_size = (uint8_t)(hwcfg >>
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ETZPC_HWCFGR_CHUNCKS1N4_SHIFT);
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etzpc_dev.revision = mmio_read_8(etzpc_dev.base + ETZPC_VERR);
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VERBOSE("ETZPC version 0x%x", etzpc_dev.revision);
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return 0;
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}
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@ -362,5 +362,13 @@
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#size-cells = <0>;
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status = "disabled";
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};
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etzpc: etzpc@5c007000 {
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compatible = "st,stm32-etzpc";
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reg = <0x5C007000 0x400>;
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clocks = <&rcc TZPC>;
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status = "disabled";
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secure-status = "okay";
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};
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};
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};
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@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRIVERS_ST_ETZPC_H
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#define DRIVERS_ST_ETZPC_H
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/* Define security level for each peripheral (DECPROT) */
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enum etzpc_decprot_attributes {
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ETZPC_DECPROT_S_RW = 0,
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ETZPC_DECPROT_NS_R_S_W = 1,
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ETZPC_DECPROT_MCU_ISOLATION = 2,
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ETZPC_DECPROT_NS_RW = 3,
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ETZPC_DECPROT_MAX = 4,
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};
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void etzpc_configure_decprot(uint32_t decprot_id,
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enum etzpc_decprot_attributes decprot_attr);
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enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id);
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void etzpc_lock_decprot(uint32_t decprot_id);
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void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value);
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uint16_t etzpc_get_tzma(uint32_t tzma_id);
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void etzpc_lock_tzma(uint32_t tzma_id);
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bool etzpc_get_lock_tzma(uint32_t tzma_id);
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uint8_t etzpc_get_num_per_sec(void);
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uint8_t etzpc_get_revision(void);
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uintptr_t etzpc_get_base_address(void);
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int etzpc_init(void);
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#endif /* DRIVERS_ST_ETZPC_H */
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@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2017-2020, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#ifndef _DT_BINDINGS_STM32_ETZPC_H
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#define _DT_BINDINGS_STM32_ETZPC_H
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/* DECPROT modes */
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#define DECPROT_S_RW 0x0
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#define DECPROT_NS_R_S_W 0x1
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#define DECPROT_MCU_ISOLATION 0x2
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#define DECPROT_NS_RW 0x3
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/* DECPROT lock */
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#define DECPROT_UNLOCK 0x0
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#define DECPROT_LOCK 0x1
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#endif /* _DT_BINDINGS_STM32_ETZPC_H */
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@ -6,10 +6,12 @@
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SP_MIN_WITH_SECURE_FIQ := 1
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BL32_SOURCES += plat/common/aarch32/platform_mp_stack.S \
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BL32_SOURCES += drivers/st/etzpc/etzpc.c \
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plat/common/aarch32/platform_mp_stack.S \
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plat/st/stm32mp1/sp_min/sp_min_setup.c \
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plat/st/stm32mp1/stm32mp1_pm.c \
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plat/st/stm32mp1/stm32mp1_topology.c
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# Generic GIC v2
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BL32_SOURCES += drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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@ -17,6 +17,7 @@
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#include <drivers/arm/tzc400.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/st/bsec.h>
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#include <drivers/st/etzpc.h>
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#include <drivers/st/stm32_console.h>
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#include <drivers/st/stm32_gpio.h>
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#include <drivers/st/stm32_iwdg.h>
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@ -76,6 +77,26 @@ entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
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return next_image_info;
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}
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#define TZMA1_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
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#define TZMA0_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
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static void stm32mp1_etzpc_early_setup(void)
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{
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unsigned int n;
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if (etzpc_init() != 0) {
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panic();
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}
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etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_ROM, TZMA0_SECURE_RANGE);
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etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_SYSRAM, TZMA1_SECURE_RANGE);
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/* Release security on all shared resources */
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for (n = 0; n < STM32MP1_ETZPC_SEC_ID_LIMIT; n++) {
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etzpc_configure_decprot(n, ETZPC_DECPROT_NS_RW);
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}
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}
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/*******************************************************************************
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* Perform any BL32 specific platform actions.
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******************************************************************************/
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@ -144,6 +165,8 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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#endif
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console_set_scope(&console, console_flags);
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}
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stm32mp1_etzpc_early_setup();
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}
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/*******************************************************************************
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@ -158,11 +181,6 @@ void sp_min_platform_setup(void)
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stm32mp1_gic_init();
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/* Unlock ETZPC securable peripherals */
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#define STM32MP1_ETZPC_BASE 0x5C007000U
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#define ETZPC_DECPROT0 0x010U
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mmio_write_32(STM32MP1_ETZPC_BASE + ETZPC_DECPROT0, 0xFFFFFFFF);
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/* Set GPIO bank Z as non secure */
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for (uint32_t pin = 0U; pin < STM32MP_GPIOZ_PIN_MAX_COUNT; pin++) {
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set_gpio_secure_cfg(GPIO_BANK_Z, pin, false);
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@ -246,6 +246,104 @@ enum ddr_type {
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#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
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#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
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/*******************************************************************************
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* STM32MP1 ETZPC
|
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******************************************************************************/
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#define STM32MP1_ETZPC_BASE U(0x5C007000)
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/* ETZPC TZMA IDs */
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#define STM32MP1_ETZPC_TZMA_ROM U(0)
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#define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
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#define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
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/* ETZPC DECPROT IDs */
|
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#define STM32MP1_ETZPC_STGENC_ID 0
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#define STM32MP1_ETZPC_BKPSRAM_ID 1
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#define STM32MP1_ETZPC_IWDG1_ID 2
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#define STM32MP1_ETZPC_USART1_ID 3
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#define STM32MP1_ETZPC_SPI6_ID 4
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#define STM32MP1_ETZPC_I2C4_ID 5
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#define STM32MP1_ETZPC_RNG1_ID 7
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#define STM32MP1_ETZPC_HASH1_ID 8
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#define STM32MP1_ETZPC_CRYP1_ID 9
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#define STM32MP1_ETZPC_DDRCTRL_ID 10
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#define STM32MP1_ETZPC_DDRPHYC_ID 11
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#define STM32MP1_ETZPC_I2C6_ID 12
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#define STM32MP1_ETZPC_SEC_ID_LIMIT 13
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|
||||
#define STM32MP1_ETZPC_TIM2_ID 16
|
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#define STM32MP1_ETZPC_TIM3_ID 17
|
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#define STM32MP1_ETZPC_TIM4_ID 18
|
||||
#define STM32MP1_ETZPC_TIM5_ID 19
|
||||
#define STM32MP1_ETZPC_TIM6_ID 20
|
||||
#define STM32MP1_ETZPC_TIM7_ID 21
|
||||
#define STM32MP1_ETZPC_TIM12_ID 22
|
||||
#define STM32MP1_ETZPC_TIM13_ID 23
|
||||
#define STM32MP1_ETZPC_TIM14_ID 24
|
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#define STM32MP1_ETZPC_LPTIM1_ID 25
|
||||
#define STM32MP1_ETZPC_WWDG1_ID 26
|
||||
#define STM32MP1_ETZPC_SPI2_ID 27
|
||||
#define STM32MP1_ETZPC_SPI3_ID 28
|
||||
#define STM32MP1_ETZPC_SPDIFRX_ID 29
|
||||
#define STM32MP1_ETZPC_USART2_ID 30
|
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#define STM32MP1_ETZPC_USART3_ID 31
|
||||
#define STM32MP1_ETZPC_UART4_ID 32
|
||||
#define STM32MP1_ETZPC_UART5_ID 33
|
||||
#define STM32MP1_ETZPC_I2C1_ID 34
|
||||
#define STM32MP1_ETZPC_I2C2_ID 35
|
||||
#define STM32MP1_ETZPC_I2C3_ID 36
|
||||
#define STM32MP1_ETZPC_I2C5_ID 37
|
||||
#define STM32MP1_ETZPC_CEC_ID 38
|
||||
#define STM32MP1_ETZPC_DAC_ID 39
|
||||
#define STM32MP1_ETZPC_UART7_ID 40
|
||||
#define STM32MP1_ETZPC_UART8_ID 41
|
||||
#define STM32MP1_ETZPC_MDIOS_ID 44
|
||||
#define STM32MP1_ETZPC_TIM1_ID 48
|
||||
#define STM32MP1_ETZPC_TIM8_ID 49
|
||||
#define STM32MP1_ETZPC_USART6_ID 51
|
||||
#define STM32MP1_ETZPC_SPI1_ID 52
|
||||
#define STM32MP1_ETZPC_SPI4_ID 53
|
||||
#define STM32MP1_ETZPC_TIM15_ID 54
|
||||
#define STM32MP1_ETZPC_TIM16_ID 55
|
||||
#define STM32MP1_ETZPC_TIM17_ID 56
|
||||
#define STM32MP1_ETZPC_SPI5_ID 57
|
||||
#define STM32MP1_ETZPC_SAI1_ID 58
|
||||
#define STM32MP1_ETZPC_SAI2_ID 59
|
||||
#define STM32MP1_ETZPC_SAI3_ID 60
|
||||
#define STM32MP1_ETZPC_DFSDM_ID 61
|
||||
#define STM32MP1_ETZPC_TT_FDCAN_ID 62
|
||||
#define STM32MP1_ETZPC_LPTIM2_ID 64
|
||||
#define STM32MP1_ETZPC_LPTIM3_ID 65
|
||||
#define STM32MP1_ETZPC_LPTIM4_ID 66
|
||||
#define STM32MP1_ETZPC_LPTIM5_ID 67
|
||||
#define STM32MP1_ETZPC_SAI4_ID 68
|
||||
#define STM32MP1_ETZPC_VREFBUF_ID 69
|
||||
#define STM32MP1_ETZPC_DCMI_ID 70
|
||||
#define STM32MP1_ETZPC_CRC2_ID 71
|
||||
#define STM32MP1_ETZPC_ADC_ID 72
|
||||
#define STM32MP1_ETZPC_HASH2_ID 73
|
||||
#define STM32MP1_ETZPC_RNG2_ID 74
|
||||
#define STM32MP1_ETZPC_CRYP2_ID 75
|
||||
#define STM32MP1_ETZPC_SRAM1_ID 80
|
||||
#define STM32MP1_ETZPC_SRAM2_ID 81
|
||||
#define STM32MP1_ETZPC_SRAM3_ID 82
|
||||
#define STM32MP1_ETZPC_SRAM4_ID 83
|
||||
#define STM32MP1_ETZPC_RETRAM_ID 84
|
||||
#define STM32MP1_ETZPC_OTG_ID 85
|
||||
#define STM32MP1_ETZPC_SDMMC3_ID 86
|
||||
#define STM32MP1_ETZPC_DLYBSD3_ID 87
|
||||
#define STM32MP1_ETZPC_DMA1_ID 88
|
||||
#define STM32MP1_ETZPC_DMA2_ID 89
|
||||
#define STM32MP1_ETZPC_DMAMUX_ID 90
|
||||
#define STM32MP1_ETZPC_FMC_ID 91
|
||||
#define STM32MP1_ETZPC_QSPI_ID 92
|
||||
#define STM32MP1_ETZPC_DLYBQ_ID 93
|
||||
#define STM32MP1_ETZPC_ETH_ID 94
|
||||
#define STM32MP1_ETZPC_RSV_ID 95
|
||||
|
||||
#define STM32MP_ETZPC_MAX_ID 96
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP1 TZC (TZ400)
|
||||
******************************************************************************/
|
||||
|
|
|
|||
Loading…
Reference in New Issue