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feat(plat/nxp/common): define common macro for ARM registers 

Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I485661bfe3ed4f214c403ff6af53dc6af1ddf089
This commit is contained in:
Jiafei Pan 2021-09-10 18:54:56 +08:00
parent 6cad59c429
commit 35efe7a4ce
3 changed files with 19 additions and 15 deletions
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24
plat/nxp/common/psci/aarch64/psci_utils.S
View File

@ -1,6 +1,6 @@
/*
* Copyright 2018-2020 NXP
* Copyright 2018-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
@ -234,7 +234,7 @@ func _psci_cpu_prep_off
msr DAIFSet, #0xF
/* read cpuectlr and save current value */
mrs x4, CORTEX_A72_ECTLR_EL1
mrs x4, CPUECTLR_EL1
mov x1, #CPUECTLR_DATA
mov x2, x4
mov x0, x10
@ -242,7 +242,7 @@ func _psci_cpu_prep_off
/* remove the core from coherency */
bic x4, x4, #CPUECTLR_SMPEN_MASK
msr CORTEX_A72_ECTLR_EL1, x4
msr CPUECTLR_EL1, x4
/* save scr_el3 */
mov x0, x10
@ -339,7 +339,7 @@ func _psci_wakeup
mov x1, #CPUECTLR_DATA
bl _getCoreData
orr x0, x0, #CPUECTLR_SMPEN_MASK
msr CORTEX_A72_ECTLR_EL1, x0
msr CPUECTLR_EL1, x0
/* x4 = core mask */
@ -563,7 +563,7 @@ func _psci_core_prep_pwrdn
/* save cpuectlr */
mov x0, x6
mov x1, #CPUECTLR_DATA
mrs x2, CORTEX_A72_ECTLR_EL1
mrs x2, CPUECTLR_EL1
bl _setCoreData
/* x6 = core mask */
@ -640,7 +640,7 @@ func _psci_core_exit_pwrdn
bl _getCoreData
/* make sure smp is set */
orr x0, x0, #CPUECTLR_SMPEN_MASK
msr CORTEX_A72_ECTLR_EL1, x0
msr CPUECTLR_EL1, x0
/* x5 = core mask */
@ -780,13 +780,13 @@ func _psci_clstr_prep_pwrdn
/* save cpuectlr */
mov x0, x6
mov x1, #CPUECTLR_DATA
mrs x2, CORTEX_A72_ECTLR_EL1
mrs x2, CPUECTLR_EL1
mov x4, x2
bl _setCoreData
/* remove core from coherency */
bic x4, x4, #CPUECTLR_SMPEN_MASK
msr CORTEX_A72_ECTLR_EL1, x4
msr CPUECTLR_EL1, x4
/* x6 = core mask */
@ -844,7 +844,7 @@ func _psci_clstr_exit_pwrdn
bl _getCoreData
/* make sure smp is set */
orr x0, x0, #CPUECTLR_SMPEN_MASK
msr CORTEX_A72_ECTLR_EL1, x0
msr CPUECTLR_EL1, x0
/* x4 = core mask */
@ -985,13 +985,13 @@ func _psci_sys_prep_pwrdn
/* save cpuectlr */
mov x0, x6
mov x1, #CPUECTLR_DATA
mrs x2, CORTEX_A72_ECTLR_EL1
mrs x2, CPUECTLR_EL1
mov x4, x2
bl _setCoreData
/* remove core from coherency */
bic x4, x4, #CPUECTLR_SMPEN_MASK
msr CORTEX_A72_ECTLR_EL1, x4
msr CPUECTLR_EL1, x4
/* x6 = core mask */
@ -1071,7 +1071,7 @@ func _psci_sys_exit_pwrdn
/* make sure smp is set */
orr x0, x0, #CPUECTLR_SMPEN_MASK
msr CORTEX_A72_ECTLR_EL1, x0
msr CPUECTLR_EL1, x0
/* x4 = core mask */

4
plat/nxp/common/psci/include/plat_psci.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2018-2020 NXP
* Copyright 2018-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
@ -7,6 +7,8 @@
#ifndef PLAT_PSCI_H
#define PLAT_PSCI_H
#include <cortex_a53.h>
#include <cortex_a72.h>
/* core abort current op */
#define CORE_ABORT_OP 0x1

6
plat/nxp/common/setup/core.mk
View File

@ -1,4 +1,4 @@
# Copyright 2018-2020 NXP
# Copyright 2018-2021 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -11,9 +11,11 @@
CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
ifeq (,$(filter $(CORE_TYPE),a53 a55 a57 a72 a75))
ifeq (,$(filter $(CORE_TYPE),a53 a72))
$(error "CORE_TYPE not specified or incorrect")
else
UPPER_CORE_TYPE=$(shell echo $(CORE_TYPE) | tr a-z A-Z)
$(eval $(call add_define_val,CPUECTLR_EL1,CORTEX_$(UPPER_CORE_TYPE)_ECTLR_EL1))
CPU_LIBS += lib/cpus/${ARCH}/cortex_$(CORE_TYPE).S
endif